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29 lines
671 B
Verilog
29 lines
671 B
Verilog
module RAM_512x64 (
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input CLK,
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input [7:0] WE,
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input EN,
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input [63:0] Di,
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output [63:0] Do,
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input [8:0] A
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);
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DFFRAM #(.COLS(2), .filename("even.hex")) LBANK (
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.CLK(CLK),
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.WE(WE[3:0]),
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.EN(EN),
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.Di(Di[31:0]),
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.Do(Do[31:0]),
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.A(A[8:0])
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);
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DFFRAM #(.COLS(2), .filename("odd.hex")) HBANK (
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.CLK(CLK),
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.WE(WE[7:4]),
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.EN(EN),
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.Di(Di[63:32]),
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.Do(Do[63:32]),
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.A(A[8:0])
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);
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endmodule
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