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59 lines
1.2 KiB
VHDL
59 lines
1.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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-- 2 cycle LSU
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-- We calculate the address in the first cycle
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entity loadstore1 is
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port (
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clk : in std_ulogic;
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l_in : in Decode2ToLoadstore1Type;
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l_out : out Loadstore1ToLoadstore2Type
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);
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end loadstore1;
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architecture behave of loadstore1 is
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signal r, rin : Loadstore1ToLoadstore2Type;
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signal lsu_sum : std_ulogic_vector(63 downto 0);
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begin
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-- Calculate the address in the first cycle
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lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0');
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loadstore1_0: process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process;
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loadstore1_1: process(all)
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variable v : Loadstore1ToLoadstore2Type;
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begin
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v := r;
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v.valid := l_in.valid;
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v.load := l_in.load;
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v.data := l_in.data;
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v.write_reg := l_in.write_reg;
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v.length := l_in.length;
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v.byte_reverse := l_in.byte_reverse;
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v.sign_extend := l_in.sign_extend;
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v.update := l_in.update;
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v.update_reg := l_in.update_reg;
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v.addr := lsu_sum;
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-- Update registers
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rin <= v;
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-- Update outputs
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l_out <= r;
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end process;
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end;
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