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92 lines
2.5 KiB
VHDL
92 lines
2.5 KiB
VHDL
-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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library ieee;
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use ieee.std_logic_1164.all;
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--! @brief A generic FIFO module.
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--! Adopted from the FIFO module in <https://github.com/skordal/smallthings>.
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entity pp_fifo is
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generic(
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DEPTH : natural := 64;
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WIDTH : natural := 32
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);
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port(
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-- Control lines:
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clk : in std_logic;
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reset : in std_logic;
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-- Status lines:
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full : out std_logic;
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empty : out std_logic;
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-- Data in:
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data_in : in std_logic_vector(WIDTH - 1 downto 0);
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data_out : out std_logic_vector(WIDTH - 1 downto 0);
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push, pop : in std_logic
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);
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end entity pp_fifo;
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architecture behaviour of pp_fifo is
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type memory_array is array(0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
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signal memory : memory_array := (others => (others => '0'));
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subtype index_type is integer range 0 to DEPTH - 1;
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signal top, bottom : index_type;
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type fifo_op is (FIFO_POP, FIFO_PUSH);
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signal prev_op : fifo_op := FIFO_POP;
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begin
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empty <= '1' when top = bottom and prev_op = FIFO_POP else '0';
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full <= '1' when top = bottom and prev_op = FIFO_PUSH else '0';
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read: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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bottom <= 0;
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else
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if pop = '1' then
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data_out <= memory(bottom);
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bottom <= (bottom + 1) mod DEPTH;
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end if;
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end if;
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end if;
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end process read;
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write: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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top <= 0;
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else
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if push = '1' then
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memory(top) <= data_in;
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top <= (top + 1) mod DEPTH;
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end if;
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end if;
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end if;
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end process write;
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set_prev_op: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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prev_op <= FIFO_POP;
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else
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if push = '1' and pop = '1' then
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-- Keep the same value for prev_op
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elsif push = '1' then
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prev_op <= FIFO_PUSH;
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elsif pop = '1' then
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prev_op <= FIFO_POP;
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end if;
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end if;
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end if;
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end process set_prev_op;
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end architecture behaviour;
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