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microwatt/litedram/generated/orangecrab-85-0.2
Matt Johnston 8901e84d8d litedram: Add orangecrab-85-0.2 target
Parameters are based on
https://github.com/gregdavill/OrangeCrab-test-sw/blob/main/hw/OrangeCrab-bitstream.py
and litex-boards orangecrab.py

rtt_nom and cmd_delay are overridden for OrangeCrab, we do the same here.

Generated with litedram and litex
62abf9c ("litedram_gen: Add block_until_ready port parameter to control blocking behaviour.")
add2746a ("tools/litex_cli: Rename wb to bus.")

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
3 years ago
..
litedram-initmem.vhdl litedram: Add orangecrab-85-0.2 target 3 years ago
litedram_core.init litedram: Add orangecrab-85-0.2 target 3 years ago
litedram_core.v litedram: Add orangecrab-85-0.2 target 3 years ago