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fcb783a0fb
This is necessary for the upcoming Arctic Tern system enablement, since Arctic Tern uses two DRAM devices and a separate clock line is routed to each device. LiteX handles this behavior correctly, therefore we assume other hardware exists that uses a similar DRAM clock design. Updates from Mikey to fix some compile issues. Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Michael Neuling <mikey@neuling.org> |
3 years ago | |
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| .. | ||
| fusesoc-add-files.py | 5 years ago | |
| litedram-wrapper-l2.vhdl | 3 years ago | |
| sim_dram_verilate.mk | ||
| sim_litedram.vhdl | 3 years ago | |
| sim_litedram_c.cpp | ||
| wave.gtkw | ||
| wave.opt | ||
| wave_tb.gtkw | 5 years ago | |