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270d7b1b9a
This adds support for the Digilane Cmod A7-35. I had to use the MMCM because the clock (12 MHz) is below the PLL minimum of 19 MHz. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> |
5 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| arty_a7-35.xdc | 5 years ago | |
| clk_gen_bypass.vhd | 5 years ago | |
| clk_gen_mcmm.vhd | 5 years ago | |
| clk_gen_plle2.vhd | 5 years ago | |
| cmod_a7-35.xdc | 5 years ago | |
| firmware.hex | 5 years ago | |
| hello_world.hex | 5 years ago | |
| nexys-video.xdc | 5 years ago | |
| nexys_a7.xdc | 5 years ago | |
| nodivide.patch | 5 years ago | |
| pp_fifo.vhd | ||
| pp_soc_memory.vhd | 5 years ago | |
| pp_soc_uart.vhd | ||
| pp_utilities.vhd | ||
| soc_reset.vhdl | 5 years ago | |
| soc_reset_tb.vhdl | 5 years ago | |
| toplevel.vhd | 5 years ago | |