forked from cores/microwatt
ad6c6790f9
The shared variable used for FIFO memory is not VHDL 2008 compliant. I can't see why it needs to be a shared variable since reads and writes update top and bottom synchronously, meaning they don't need same cycle access to the FIFO memory. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> |
6 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| arty_a7.xdc | ||
| clk_gen_bypass.vhd | ||
| clk_gen_mcmm.vhd | 6 years ago | |
| clk_gen_plle2.vhd | 6 years ago | |
| cmod_a7-35.xdc | ||
| firmware.hex | ||
| hello_world.hex | ||
| mw_soc_memory.vhdl | ||
| nexys-video.xdc | ||
| nexys_a7.xdc | ||
| pp_fifo.vhd | 6 years ago | |
| pp_soc_uart.vhd | ||
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| toplevel.vhdl | 6 years ago | |