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fpu-init
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icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
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caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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cache-tlb-parameters-2
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microwatt/litedram/extras
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Benjamin Herrenschmidt b23fd6c5f1 litedram: Defer clearing of tags & valids to improve timing 
Currently, there's a huge mux gathering the output of all the PLRUs
to select the victim way on cache miss. This is fed combinationally
into the clearing of the valid and tags.

In order to help timing, let's store it instead and perform the
clearing on the next cycle. The L2 doesn't respond to requests
when not in IDLE state so this should have no negative effects.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
fusesoc-add-files.py litedram: Remove old "VexRiscV" based initializations 4 years ago
litedram-wrapper-l2.vhdl litedram: Defer clearing of tags & valids to improve timing 4 years ago
sim_dram_verilate.mk litedram: Add simulation support 4 years ago
sim_litedram.vhdl litedram: Add simulation support 4 years ago
sim_litedram_c.cpp litedram: Add simulation support 4 years ago
wave.gtkw litedram: Add an L2 cache with store queue 4 years ago
wave.opt litedram: Add an L2 cache with store queue 4 years ago
wave_tb.gtkw litedram: Test bench 4 years ago