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370 lines
13 KiB
VHDL
370 lines
13 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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package common is
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-- SPR numbers
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subtype spr_num_t is integer range 0 to 1023;
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function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
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constant SPR_XER : spr_num_t := 1;
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constant SPR_LR : spr_num_t := 8;
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constant SPR_CTR : spr_num_t := 9;
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constant SPR_TB : spr_num_t := 268;
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constant SPR_SRR0 : spr_num_t := 26;
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constant SPR_SRR1 : spr_num_t := 27;
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constant SPR_HSRR0 : spr_num_t := 314;
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constant SPR_HSRR1 : spr_num_t := 315;
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constant SPR_SPRG0 : spr_num_t := 272;
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constant SPR_SPRG1 : spr_num_t := 273;
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constant SPR_SPRG2 : spr_num_t := 274;
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constant SPR_SPRG3 : spr_num_t := 275;
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constant SPR_SPRG3U : spr_num_t := 259;
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constant SPR_HSPRG0 : spr_num_t := 304;
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constant SPR_HSPRG1 : spr_num_t := 305;
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-- GPR indices in the register file (GPR only)
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subtype gpr_index_t is std_ulogic_vector(4 downto 0);
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-- Extended GPR indice (can hold an SPR)
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subtype gspr_index_t is std_ulogic_vector(5 downto 0);
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-- Some SPRs are stored in the register file, they use the magic
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-- GPR numbers above 31.
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--
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-- The function fast_spr_num() returns the corresponding fast
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-- pseudo-GPR number for a given SPR number. The result MSB
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-- indicates if this is indeed a fast SPR. If clear, then
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-- the SPR is not stored in the GPR file.
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--
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function fast_spr_num(spr: spr_num_t) return gspr_index_t;
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-- Indices conversion functions
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function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
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function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
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function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
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function is_fast_spr(s: gspr_index_t) return std_ulogic;
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-- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
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-- in the CR file as a kind of CR extension (with a separate write
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-- control). The rest is stored as a fast SPR.
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type xer_common_t is record
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ca : std_ulogic;
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ca32 : std_ulogic;
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ov : std_ulogic;
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ov32 : std_ulogic;
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so : std_ulogic;
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end record;
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constant xerc_init : xer_common_t := (others => '0');
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-- This needs to die...
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type ctrl_t is record
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tb: std_ulogic_vector(63 downto 0);
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end record;
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type Fetch1ToIcacheType is record
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req: std_ulogic;
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stop_mark: std_ulogic;
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nia: std_ulogic_vector(63 downto 0);
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end record;
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type IcacheToFetch2Type is record
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valid: std_ulogic;
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stop_mark: std_ulogic;
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nia: std_ulogic_vector(63 downto 0);
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insn: std_ulogic_vector(31 downto 0);
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end record;
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type Fetch2ToDecode1Type is record
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valid: std_ulogic;
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stop_mark : std_ulogic;
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nia: std_ulogic_vector(63 downto 0);
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insn: std_ulogic_vector(31 downto 0);
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end record;
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constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', stop_mark => '0', others => (others => '0'));
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type Decode1ToDecode2Type is record
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valid: std_ulogic;
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stop_mark : std_ulogic;
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nia: std_ulogic_vector(63 downto 0);
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insn: std_ulogic_vector(31 downto 0);
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ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
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ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
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decode: decode_rom_t;
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end record;
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constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', decode => decode_rom_init, others => (others => '0'));
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type Decode2ToExecute1Type is record
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valid: std_ulogic;
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insn_type: insn_type_t;
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nia: std_ulogic_vector(63 downto 0);
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write_reg: gspr_index_t;
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read_reg1: gspr_index_t;
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read_reg2: gspr_index_t;
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read_data1: std_ulogic_vector(63 downto 0);
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read_data2: std_ulogic_vector(63 downto 0);
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read_data3: std_ulogic_vector(63 downto 0);
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bypass_data1: std_ulogic;
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bypass_data2: std_ulogic;
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bypass_data3: std_ulogic;
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cr: std_ulogic_vector(31 downto 0);
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xerc: xer_common_t;
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lr: std_ulogic;
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rc: std_ulogic;
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oe: std_ulogic;
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invert_a: std_ulogic;
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invert_out: std_ulogic;
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input_carry: carry_in_t;
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output_carry: std_ulogic;
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input_cr: std_ulogic;
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output_cr: std_ulogic;
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is_32bit: std_ulogic;
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is_signed: std_ulogic;
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insn: std_ulogic_vector(31 downto 0);
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data_len: std_ulogic_vector(3 downto 0);
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byte_reverse : std_ulogic;
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sign_extend : std_ulogic; -- do we need to sign extend?
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update : std_ulogic; -- is this an update instruction?
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reserve : std_ulogic; -- set for larx/stcx
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end record;
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constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
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(valid => '0', insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
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lr => '0', rc => '0', oe => '0', invert_a => '0',
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invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
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is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0',
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byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
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type Execute1ToMultiplyType is record
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valid: std_ulogic;
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insn_type: insn_type_t;
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data1: std_ulogic_vector(64 downto 0);
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data2: std_ulogic_vector(64 downto 0);
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is_32bit: std_ulogic;
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end record;
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constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL,
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is_32bit => '0',
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others => (others => '0'));
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type Execute1ToDividerType is record
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valid: std_ulogic;
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dividend: std_ulogic_vector(63 downto 0);
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divisor: std_ulogic_vector(63 downto 0);
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is_signed: std_ulogic;
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is_32bit: std_ulogic;
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is_extended: std_ulogic;
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is_modulus: std_ulogic;
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neg_result: std_ulogic;
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end record;
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constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
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is_extended => '0', is_modulus => '0',
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neg_result => '0', others => (others => '0'));
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type Decode2ToRegisterFileType is record
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read1_enable : std_ulogic;
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read1_reg : gspr_index_t;
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read2_enable : std_ulogic;
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read2_reg : gspr_index_t;
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read3_enable : std_ulogic;
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read3_reg : gpr_index_t;
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end record;
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type RegisterFileToDecode2Type is record
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read1_data : std_ulogic_vector(63 downto 0);
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read2_data : std_ulogic_vector(63 downto 0);
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read3_data : std_ulogic_vector(63 downto 0);
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end record;
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type Decode2ToCrFileType is record
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read : std_ulogic;
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end record;
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type CrFileToDecode2Type is record
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read_cr_data : std_ulogic_vector(31 downto 0);
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read_xerc_data : xer_common_t;
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end record;
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type Execute1ToFetch1Type is record
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redirect: std_ulogic;
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redirect_nia: std_ulogic_vector(63 downto 0);
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end record;
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constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', others => (others => '0'));
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type Execute1ToLoadstore1Type is record
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valid : std_ulogic;
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load : std_ulogic; -- is this a load or store
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addr1 : std_ulogic_vector(63 downto 0);
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addr2 : std_ulogic_vector(63 downto 0);
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data : std_ulogic_vector(63 downto 0); -- data to write, unused for read
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write_reg : gpr_index_t;
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length : std_ulogic_vector(3 downto 0);
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byte_reverse : std_ulogic;
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sign_extend : std_ulogic; -- do we need to sign extend?
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update : std_ulogic; -- is this an update instruction?
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update_reg : gpr_index_t; -- if so, the register to update
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xerc : xer_common_t;
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reserve : std_ulogic; -- set for larx/stcx.
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rc : std_ulogic; -- set for stcx.
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end record;
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constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', load => '0', byte_reverse => '0',
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sign_extend => '0', update => '0', xerc => xerc_init,
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reserve => '0', rc => '0', others => (others => '0'));
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type Loadstore1ToDcacheType is record
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valid : std_ulogic;
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load : std_ulogic;
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nc : std_ulogic;
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reserve : std_ulogic;
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addr : std_ulogic_vector(63 downto 0);
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data : std_ulogic_vector(63 downto 0);
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byte_sel : std_ulogic_vector(7 downto 0);
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end record;
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type DcacheToLoadstore1Type is record
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valid : std_ulogic;
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data : std_ulogic_vector(63 downto 0);
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store_done : std_ulogic;
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error : std_ulogic;
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end record;
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type Loadstore1ToWritebackType is record
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valid : std_ulogic;
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write_enable: std_ulogic;
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write_reg : gpr_index_t;
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write_data : std_ulogic_vector(63 downto 0);
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write_len : std_ulogic_vector(3 downto 0);
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write_shift : std_ulogic_vector(2 downto 0);
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sign_extend : std_ulogic;
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byte_reverse : std_ulogic;
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second_word : std_ulogic;
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xerc : xer_common_t;
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rc : std_ulogic;
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store_done : std_ulogic;
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end record;
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constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', sign_extend => '0',
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byte_reverse => '0', second_word => '0', xerc => xerc_init,
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rc => '0', store_done => '0', others => (others => '0'));
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type Execute1ToWritebackType is record
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valid: std_ulogic;
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rc : std_ulogic;
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write_enable : std_ulogic;
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write_reg: gspr_index_t;
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write_data: std_ulogic_vector(63 downto 0);
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write_cr_enable : std_ulogic;
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write_cr_mask : std_ulogic_vector(7 downto 0);
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write_cr_data : std_ulogic_vector(31 downto 0);
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write_xerc_enable : std_ulogic;
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xerc : xer_common_t;
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end record;
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constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
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write_cr_enable => '0',
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write_xerc_enable => '0', xerc => xerc_init,
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others => (others => '0'));
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type MultiplyToExecute1Type is record
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valid: std_ulogic;
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write_reg_data: std_ulogic_vector(63 downto 0);
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overflow : std_ulogic;
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end record;
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constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
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others => (others => '0'));
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type DividerToExecute1Type is record
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valid: std_ulogic;
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write_reg_data: std_ulogic_vector(63 downto 0);
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overflow : std_ulogic;
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end record;
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constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
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others => (others => '0'));
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type WritebackToRegisterFileType is record
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write_reg : gspr_index_t;
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write_data : std_ulogic_vector(63 downto 0);
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write_enable : std_ulogic;
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end record;
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constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', others => (others => '0'));
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type WritebackToCrFileType is record
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write_cr_enable : std_ulogic;
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write_cr_mask : std_ulogic_vector(7 downto 0);
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write_cr_data : std_ulogic_vector(31 downto 0);
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write_xerc_enable : std_ulogic;
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write_xerc_data : xer_common_t;
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end record;
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constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
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write_xerc_data => xerc_init,
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others => (others => '0'));
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end common;
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package body common is
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function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
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begin
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return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
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end;
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function fast_spr_num(spr: spr_num_t) return gspr_index_t is
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variable n : integer range 0 to 31;
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begin
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case spr is
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when SPR_LR =>
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n := 0;
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when SPR_CTR =>
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n:= 1;
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when SPR_SRR0 =>
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n := 2;
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when SPR_SRR1 =>
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n := 3;
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when SPR_HSRR0 =>
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n := 4;
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when SPR_HSRR1 =>
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n := 5;
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when SPR_SPRG0 =>
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n := 6;
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when SPR_SPRG1 =>
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n := 7;
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when SPR_SPRG2 =>
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n := 8;
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when SPR_SPRG3 | SPR_SPRG3U =>
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n := 9;
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when SPR_HSPRG0 =>
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n := 10;
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when SPR_HSPRG1 =>
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n := 11;
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when SPR_XER =>
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n := 12;
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when others =>
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n := 0;
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return "000000";
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end case;
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return "1" & std_ulogic_vector(to_unsigned(n, 5));
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end;
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function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
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begin
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return i(4 downto 0);
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end;
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function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
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begin
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return "0" & i;
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end;
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function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
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begin
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if s(5) = '1' then
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return s;
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else
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return gpr_to_gspr(g);
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end if;
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end;
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function is_fast_spr(s: gspr_index_t) return std_ulogic is
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begin
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return s(5);
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end;
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end common;
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