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fpu-init
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microwatt/litedram
History
Benjamin Herrenschmidt b58ff724f6 litedram: Add stash buffer to the L2 cache wishbone interface 
This breaks the long stall signal coming back to the processor
and helps improve overall timing.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
extras litedram: Add stash buffer to the L2 cache wishbone interface 4 years ago
gen-src litedram: Fix DRAM init mem using too many address bits 4 years ago
generated litedram: Fix DRAM init mem using too many address bits 4 years ago
litedram.core litedram: Add basic support for LiteX LiteDRAM 4 years ago