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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
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microwatt/litedram/gen-src
History
Benjamin Herrenschmidt 6aadad5a75 spi: Add booting from flash to litedram init 
It will look for an ELF binary at the flash offset specified
for the board (currently 0x300000 on Arty but that could be
changed).

Note: litedram is regenerated in order to rebuild the init code,
which was done using a newer version of litedram from LiteX.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		5 years ago
..
sdram_init spi: Add booting from flash to litedram init 5 years ago
arty.yml litedram: Remove old "VexRiscV" based initializations 5 years ago
dram-init-mem.vhdl litedram: Fix DRAM init mem using too many address bits 5 years ago
generate.py litedram: Remove old "VexRiscV" based initializations 5 years ago
nexys-video.yml litedram: Remove old "VexRiscV" based initializations 5 years ago
no-init-mem.vhdl litedram: Split the init memory from the main wrapper 5 years ago
sim.yml litedram: Remove old "VexRiscV" based initializations 5 years ago