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8e0389b973
This replaces the simple_ram_behavioural and mw_soc_memory modules with a common wishbone_bram_wrapper.vhdl that interfaces the pipelined WB with a lower-level RAM module, along with an FPGA and a sim variants of the latter. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
5 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| arty_a7.xdc | ||
| clk_gen_bypass.vhd | 5 years ago | |
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | ||
| cmod_a7-35.xdc | ||
| firmware.hex | ||
| hello_world.hex | ||
| main_bram.vhdl | 5 years ago | |
| nexys-video.xdc | ||
| nexys_a7.xdc | ||
| pp_fifo.vhd | 5 years ago | |
| pp_soc_uart.vhd | 5 years ago | |
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| toplevel.vhdl | 5 years ago | |