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625 lines
23 KiB
VHDL
625 lines
23 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_types.all;
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entity spi_flash_ctrl is
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generic (
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-- Default config for auto-mode
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DEF_CLK_DIV : natural := 2; -- Clock divider SCK = CLK/((CLK_DIV+1)*2)
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DEF_QUAD_READ : boolean := false; -- Use quad read with 8 clk dummy
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-- Dummy clocks after boot
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BOOT_CLOCKS : boolean := false; -- Send 8 dummy clocks after boot
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-- Number of data lines (1=MISO/MOSI, otherwise 2 or 4)
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DATA_LINES : positive := 1
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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-- Wishbone ports:
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wb_in : in wb_io_master_out;
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wb_out : out wb_io_slave_out;
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-- Wishbone extra selects
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wb_sel_reg : in std_ulogic;
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wb_sel_map : in std_ulogic;
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-- SPI port
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sck : out std_ulogic;
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cs_n : out std_ulogic;
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sdat_o : out std_ulogic_vector(DATA_LINES-1 downto 0);
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sdat_oe : out std_ulogic_vector(DATA_LINES-1 downto 0);
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sdat_i : in std_ulogic_vector(DATA_LINES-1 downto 0)
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);
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end entity spi_flash_ctrl;
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architecture rtl of spi_flash_ctrl is
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-- Register indices
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constant SPI_REG_BITS : positive := 3;
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-- Register addresses (matches wishbone addr downto 2, ie, 4 bytes per reg)
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constant SPI_REG_DATA : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "000";
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constant SPI_REG_CTRL : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "001";
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constant SPI_REG_AUTO_CFG : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "010";
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constant SPI_REG_INVALID : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "111";
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-- Control register
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signal ctrl_reg : std_ulogic_vector(15 downto 0) := (others => '0');
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alias ctrl_reset : std_ulogic is ctrl_reg(0);
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alias ctrl_cs : std_ulogic is ctrl_reg(1);
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alias ctrl_rsrv1 : std_ulogic is ctrl_reg(2);
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alias ctrl_rsrv2 : std_ulogic is ctrl_reg(3);
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alias ctrl_div : std_ulogic_vector(7 downto 0) is ctrl_reg(15 downto 8);
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-- Auto mode config register
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signal auto_cfg_reg : std_ulogic_vector(29 downto 0) := (others => '0');
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alias auto_cfg_cmd : std_ulogic_vector(7 downto 0) is auto_cfg_reg(7 downto 0);
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alias auto_cfg_dummies : std_ulogic_vector(2 downto 0) is auto_cfg_reg(10 downto 8);
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alias auto_cfg_mode : std_ulogic_vector(1 downto 0) is auto_cfg_reg(12 downto 11);
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alias auto_cfg_addr4 : std_ulogic is auto_cfg_reg(13);
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alias auto_cfg_rsrv1 : std_ulogic is auto_cfg_reg(14);
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alias auto_cfg_rsrv2 : std_ulogic is auto_cfg_reg(15);
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alias auto_cfg_div : std_ulogic_vector(7 downto 0) is auto_cfg_reg(23 downto 16);
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alias auto_cfg_cstout : std_ulogic_vector(5 downto 0) is auto_cfg_reg(29 downto 24);
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-- Constants below match top 2 bits of rxtx "mode"
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constant SPI_AUTO_CFG_MODE_SINGLE : std_ulogic_vector(1 downto 0) := "00";
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constant SPI_AUTO_CFG_MODE_DUAL : std_ulogic_vector(1 downto 0) := "10";
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constant SPI_AUTO_CFG_MODE_QUAD : std_ulogic_vector(1 downto 0) := "11";
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-- Signals to rxtx
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signal cmd_valid : std_ulogic;
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signal cmd_clk_div : natural range 0 to 255;
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signal cmd_mode : std_ulogic_vector(2 downto 0);
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signal cmd_ready : std_ulogic;
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signal d_clks : std_ulogic_vector(2 downto 0);
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signal d_rx : std_ulogic_vector(7 downto 0);
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signal d_tx : std_ulogic_vector(7 downto 0);
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signal d_ack : std_ulogic;
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signal bus_idle : std_ulogic;
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-- Latch to track that we have a pending read
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signal pending_read : std_ulogic;
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-- Wishbone latches
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signal wb_req : wb_io_master_out;
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signal wb_stash : wb_io_master_out;
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signal wb_rsp : wb_io_slave_out;
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-- Wishbone decode
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signal wb_valid : std_ulogic;
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signal wb_reg_valid : std_ulogic;
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signal wb_reg_dat_v : std_ulogic;
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signal wb_map_valid : std_ulogic;
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signal wb_reg : std_ulogic_vector(SPI_REG_BITS-1 downto 0);
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-- Auto mode clock counts XXX FIXME: Look at reasonable values based
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-- on system clock maybe ? Or make them programmable.
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constant CS_DELAY_ASSERT : integer := 1; -- CS low to cmd
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constant CS_DELAY_RECOVERY : integer := 10; -- CS high to CS low
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constant DEFAULT_CS_TIMEOUT : integer := 32;
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-- Automatic mode state
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type auto_state_t is (AUTO_BOOT, AUTO_IDLE, AUTO_CS_ON, AUTO_CMD,
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AUTO_ADR0, AUTO_ADR1, AUTO_ADR2, AUTO_ADR3,
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AUTO_DUMMY,
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AUTO_DAT0, AUTO_DAT1, AUTO_DAT2, AUTO_DAT3,
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AUTO_DAT0_DATA, AUTO_DAT1_DATA, AUTO_DAT2_DATA, AUTO_DAT3_DATA,
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AUTO_SEND_ACK, AUTO_WAIT_REQ, AUTO_RECOVERY);
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-- Automatic mode signals
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signal auto_cs : std_ulogic;
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signal auto_cmd_valid : std_ulogic;
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signal auto_cmd_mode : std_ulogic_vector(2 downto 0);
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signal auto_d_txd : std_ulogic_vector(7 downto 0);
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signal auto_d_clks : std_ulogic_vector(2 downto 0);
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signal auto_data_next : std_ulogic_vector(wb_out.dat'left downto 0);
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signal auto_cnt_next : integer range 0 to 63;
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signal auto_ack : std_ulogic;
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signal auto_next : auto_state_t;
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signal auto_lad_next : std_ulogic_vector(31 downto 0);
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signal auto_latch_adr : std_ulogic;
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-- Automatic mode latches
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signal auto_data : std_ulogic_vector(wb_out.dat'left downto 0) := (others => '0');
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signal auto_cnt : integer range 0 to 63 := 0;
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signal auto_state : auto_state_t := AUTO_BOOT;
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signal auto_last_addr : std_ulogic_vector(31 downto 0);
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begin
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-- Instanciate low level shifter
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spi_rxtx: entity work.spi_rxtx
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generic map (
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DATA_LINES => DATA_LINES
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)
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port map(
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rst => rst,
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clk => clk,
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clk_div_i => cmd_clk_div,
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cmd_valid_i => cmd_valid,
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cmd_ready_o => cmd_ready,
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cmd_mode_i => cmd_mode,
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cmd_clks_i => d_clks,
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cmd_txd_i => d_tx,
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d_rxd_o => d_rx,
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d_ack_o => d_ack,
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bus_idle_o => bus_idle,
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sck => sck,
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sdat_o => sdat_o,
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sdat_oe => sdat_oe,
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sdat_i => sdat_i
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);
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-- Valid wb command
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wb_valid <= wb_req.stb and wb_req.cyc;
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wb_reg_valid <= wb_valid and wb_sel_reg;
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wb_map_valid <= wb_valid and wb_sel_map;
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-- Register decode. For map accesses, make it look like "invalid"
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wb_reg <= wb_req.adr(SPI_REG_BITS+1 downto 2) when wb_reg_valid else SPI_REG_INVALID;
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-- Shortcut because we test that a lot: data register access
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wb_reg_dat_v <= '1' when wb_reg = SPI_REG_DATA else '0';
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-- Wishbone request -> SPI request
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wb_request_sync: process(clk)
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begin
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if rising_edge(clk) then
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-- We need to latch whether a read is in progress to block
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-- a subsequent store, otherwise the acks will collide.
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--
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-- We are heavy handed and force a wait for an idle bus if
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-- a store is behind a load. Shouldn't happen with flashes
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-- in practice.
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--
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if cmd_valid = '1' and cmd_ready = '1' then
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pending_read <= not wb_req.we;
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elsif bus_idle = '1' then
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pending_read <= '0';
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end if;
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end if;
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end process;
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wb_request_comb: process(all)
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begin
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if ctrl_cs = '1' then
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-- Data register access (see wb_request_sync)
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cmd_valid <= wb_reg_dat_v and not (pending_read and wb_req.we);
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-- Clock divider from control reg
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cmd_clk_div <= to_integer(unsigned(ctrl_div));
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-- Mode based on sel
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if wb_req.sel = "0010" then
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-- dual mode
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cmd_mode <= "10" & wb_req.we;
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d_clks <= "011";
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elsif wb_req.sel = "0100" then
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-- quad mode
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cmd_mode <= "11" & wb_req.we;
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d_clks <= "001";
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else
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-- single bit
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cmd_mode <= "01" & wb_req.we;
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d_clks <= "111";
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end if;
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d_tx <= wb_req.dat(7 downto 0);
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cs_n <= not ctrl_cs;
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else
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cmd_valid <= auto_cmd_valid;
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cmd_mode <= auto_cmd_mode;
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cmd_clk_div <= to_integer(unsigned(auto_cfg_div));
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d_tx <= auto_d_txd;
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d_clks <= auto_d_clks;
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cs_n <= not auto_cs;
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end if;
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end process;
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-- Generate wishbone responses
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--
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-- Note: wb_out and wb_in should only appear in this synchronous process
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--
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-- Everything else should work on wb_req and wb_rsp
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wb_response_sync: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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wb_out.ack <= '0';
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wb_out.stall <= '0';
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wb_stash.cyc <= '0';
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wb_stash.stb <= '0';
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wb_stash.sel <= (others => '0');
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wb_stash.we <= '0';
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else
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-- Latch wb responses as well for 1 cycle. Stall is updated
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-- below
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wb_out <= wb_rsp;
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-- Implement a stash buffer. If we are stalled and stash is
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-- free, fill it up. This will generate a WB stall on the
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-- next cycle.
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if wb_rsp.stall = '1' and wb_out.stall = '0' and
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wb_in.cyc = '1' and wb_in.stb = '1' then
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wb_stash <= wb_in;
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wb_out.stall <= '1';
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end if;
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-- We aren't stalled, see what we can do
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if wb_rsp.stall = '0' then
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if wb_out.stall = '1' then
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-- Something in stash ! use it and clear stash
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wb_req <= wb_stash;
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wb_out.stall <= '0';
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else
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-- Nothing in stash, grab request from WB
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if wb_in.cyc = '1' then
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wb_req <= wb_in;
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else
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wb_req.cyc <= wb_in.cyc;
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wb_req.stb <= wb_in.stb;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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wb_response_comb: process(all)
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begin
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-- Defaults
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wb_rsp.ack <= '0';
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wb_rsp.dat <= x"00" & d_rx & d_rx & d_rx;
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wb_rsp.stall <= '0';
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-- Depending on the access type...
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if wb_map_valid = '1' then
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-- Memory map access
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wb_rsp.stall <= not auto_ack; -- XXX FIXME: Allow pipelining
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wb_rsp.ack <= auto_ack;
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wb_rsp.dat <= auto_data;
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elsif ctrl_cs = '1' and wb_reg = SPI_REG_DATA then
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-- Data register in manual mode
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--
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-- Stall stores if there's a pending read to avoid
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-- acks colliding. Otherwise accept all accesses
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-- immediately if rxtx is ready.
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--
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-- Note: This must match the logic setting cmd_valid
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-- in wb_request_comb.
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--
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-- We also ack stores immediately when accepted. Loads
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-- are handled separately further down.
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--
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if wb_req.we = '1' and pending_read = '1' then
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wb_rsp.stall <= '1';
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else
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wb_rsp.ack <= wb_req.we and cmd_ready;
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wb_rsp.stall <= not cmd_ready;
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end if;
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-- Note: loads acks are handled elsewhere
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elsif wb_reg_valid = '1' then
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-- Normal register access
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--
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-- Normally single cycle but ensure any auto-mode or manual
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-- operation is complete first
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--
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if auto_state = AUTO_IDLE and bus_idle = '1' then
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wb_rsp.ack <= '1';
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wb_rsp.stall <= '0';
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case wb_reg is
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when SPI_REG_CTRL =>
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wb_rsp.dat <= (ctrl_reg'range => ctrl_reg, others => '0');
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when SPI_REG_AUTO_CFG =>
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wb_rsp.dat <= (auto_cfg_reg'range => auto_cfg_reg, others => '0');
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when others => null;
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end case;
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else
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wb_rsp.stall <= '1';
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end if;
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end if;
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-- For loads in manual mode, we've accepted the command early
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-- so none of the above connditions might be true. We thus need
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-- to send the ack whenever we are getting it from rxtx.
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--
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-- This shouldn't collide with any of the above acks because we hold
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-- normal register accesses and stores when there is a pending
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-- load or the bus is busy.
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--
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if ctrl_cs = '1' and d_ack = '1' then
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assert pending_read = '1' report "d_ack without pending read !" severity failure;
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wb_rsp.ack <= '1';
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end if;
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end process;
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-- Automatic mode state machine
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auto_sync: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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auto_last_addr <= (others => '0');
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auto_state <= AUTO_BOOT;
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else
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auto_state <= auto_next;
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auto_cnt <= auto_cnt_next;
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auto_data <= auto_data_next;
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if auto_latch_adr = '1' then
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auto_last_addr <= auto_lad_next;
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end if;
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end if;
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end if;
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end process;
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auto_comb: process(all)
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variable addr : std_ulogic_vector(31 downto 0);
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variable req_is_next : boolean;
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function mode_to_clks(mode: std_ulogic_vector(1 downto 0)) return std_ulogic_vector is
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begin
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if mode = SPI_AUTO_CFG_MODE_QUAD then
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return "001";
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elsif mode = SPI_AUTO_CFG_MODE_DUAL then
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return "011";
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else
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return "111";
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end if;
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end function;
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begin
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-- Default outputs
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auto_ack <= '0';
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auto_cs <= '0';
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auto_cmd_valid <= '0';
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auto_d_txd <= x"00";
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auto_cmd_mode <= "001";
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auto_d_clks <= "111";
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auto_latch_adr <= '0';
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-- Default next state
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auto_next <= auto_state;
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auto_cnt_next <= auto_cnt;
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auto_data_next <= auto_data;
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-- Convert wishbone address into a flash address. We mask
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-- off the 4 top address bits to get rid of the "f" there.
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addr := "00" & wb_req.adr(29 downto 2) & "00";
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-- Calculate the next address for store & compare later
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auto_lad_next <= std_ulogic_vector(unsigned(addr) + 4);
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-- Match incoming request address with next address
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req_is_next := addr = auto_last_addr;
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-- XXX TODO:
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-- - Support < 32-bit accesses
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-- Reset
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if rst = '1' or ctrl_reset = '1' then
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auto_cs <= '0';
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auto_cnt_next <= 0;
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auto_next <= AUTO_BOOT;
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else
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-- Run counter
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if auto_cnt /= 0 then
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auto_cnt_next <= auto_cnt - 1;
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end if;
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-- Automatic CS is set whenever state isn't IDLE or RECOVERY or BOOT
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if auto_state /= AUTO_IDLE and
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auto_state /= AUTO_RECOVERY and
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auto_state /= AUTO_BOOT then
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auto_cs <= '1';
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end if;
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-- State machine
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case auto_state is
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when AUTO_BOOT =>
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if BOOT_CLOCKS then
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auto_cmd_valid <= '1';
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if cmd_ready = '1' then
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auto_next <= AUTO_IDLE;
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end if;
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else
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auto_next <= AUTO_IDLE;
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end if;
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when AUTO_IDLE =>
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-- Access to the memory map only when manual CS isn't set
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if wb_map_valid = '1' and ctrl_cs = '0' then
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-- Ignore writes, we don't support them yet
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if wb_req.we = '1' then
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auto_ack <= '1';
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else
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-- Start machine with CS assertion delay
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auto_next <= AUTO_CS_ON;
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auto_cnt_next <= CS_DELAY_ASSERT;
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end if;
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end if;
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when AUTO_CS_ON =>
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if auto_cnt = 0 then
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-- CS asserted long enough, send command
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auto_next <= AUTO_CMD;
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end if;
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when AUTO_CMD =>
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auto_d_txd <= auto_cfg_cmd;
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auto_cmd_valid <= '1';
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if cmd_ready = '1' then
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if auto_cfg_addr4 = '1' then
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auto_next <= AUTO_ADR3;
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else
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auto_next <= AUTO_ADR2;
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end if;
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end if;
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when AUTO_ADR3 =>
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auto_d_txd <= addr(31 downto 24);
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auto_cmd_valid <= '1';
|
|
if cmd_ready = '1' then
|
|
auto_next <= AUTO_ADR2;
|
|
end if;
|
|
when AUTO_ADR2 =>
|
|
auto_d_txd <= addr(23 downto 16);
|
|
auto_cmd_valid <= '1';
|
|
if cmd_ready = '1' then
|
|
auto_next <= AUTO_ADR1;
|
|
end if;
|
|
when AUTO_ADR1 =>
|
|
auto_d_txd <= addr(15 downto 8);
|
|
auto_cmd_valid <= '1';
|
|
if cmd_ready = '1' then
|
|
auto_next <= AUTO_ADR0;
|
|
end if;
|
|
when AUTO_ADR0 =>
|
|
auto_d_txd <= addr(7 downto 0);
|
|
auto_cmd_valid <= '1';
|
|
if cmd_ready = '1' then
|
|
if auto_cfg_dummies = "000" then
|
|
auto_next <= AUTO_DAT0;
|
|
else
|
|
auto_next <= AUTO_DUMMY;
|
|
end if;
|
|
end if;
|
|
when AUTO_DUMMY =>
|
|
auto_cmd_valid <= '1';
|
|
auto_d_clks <= auto_cfg_dummies;
|
|
if cmd_ready = '1' then
|
|
auto_next <= AUTO_DAT0;
|
|
end if;
|
|
when AUTO_DAT0 =>
|
|
auto_cmd_valid <= '1';
|
|
auto_cmd_mode <= auto_cfg_mode & "0";
|
|
auto_d_clks <= mode_to_clks(auto_cfg_mode);
|
|
if cmd_ready = '1' then
|
|
auto_next <= AUTO_DAT0_DATA;
|
|
end if;
|
|
when AUTO_DAT0_DATA =>
|
|
if d_ack = '1' then
|
|
auto_data_next(7 downto 0) <= d_rx;
|
|
auto_next <= AUTO_DAT1;
|
|
end if;
|
|
when AUTO_DAT1 =>
|
|
auto_cmd_valid <= '1';
|
|
auto_cmd_mode <= auto_cfg_mode & "0";
|
|
auto_d_clks <= mode_to_clks(auto_cfg_mode);
|
|
if cmd_ready = '1' then
|
|
auto_next <= AUTO_DAT1_DATA;
|
|
end if;
|
|
when AUTO_DAT1_DATA =>
|
|
if d_ack = '1' then
|
|
auto_data_next(15 downto 8) <= d_rx;
|
|
auto_next <= AUTO_DAT2;
|
|
end if;
|
|
when AUTO_DAT2 =>
|
|
auto_cmd_valid <= '1';
|
|
auto_cmd_mode <= auto_cfg_mode & "0";
|
|
auto_d_clks <= mode_to_clks(auto_cfg_mode);
|
|
if cmd_ready = '1' then
|
|
auto_next <= AUTO_DAT2_DATA;
|
|
end if;
|
|
when AUTO_DAT2_DATA =>
|
|
if d_ack = '1' then
|
|
auto_data_next(23 downto 16) <= d_rx;
|
|
auto_next <= AUTO_DAT3;
|
|
end if;
|
|
when AUTO_DAT3 =>
|
|
auto_cmd_valid <= '1';
|
|
auto_cmd_mode <= auto_cfg_mode & "0";
|
|
auto_d_clks <= mode_to_clks(auto_cfg_mode);
|
|
if cmd_ready = '1' then
|
|
auto_next <= AUTO_DAT3_DATA;
|
|
end if;
|
|
when AUTO_DAT3_DATA =>
|
|
if d_ack = '1' then
|
|
auto_data_next(31 downto 24) <= d_rx;
|
|
auto_next <= AUTO_SEND_ACK;
|
|
auto_latch_adr <= '1';
|
|
end if;
|
|
when AUTO_SEND_ACK =>
|
|
auto_ack <= '1';
|
|
auto_cnt_next <= to_integer(unsigned(auto_cfg_cstout));
|
|
auto_next <= AUTO_WAIT_REQ;
|
|
when AUTO_WAIT_REQ =>
|
|
-- Incoming bus request we can take ? Otherwise do we need
|
|
-- to cancel the wait ?
|
|
if wb_map_valid = '1' and req_is_next and wb_req.we = '0' then
|
|
auto_next <= AUTO_DAT0;
|
|
elsif wb_map_valid = '1' or wb_reg_valid = '1' or auto_cnt = 0 then
|
|
-- This means we can drop the CS right on the next clock.
|
|
-- We make the assumption here that the two cycles min
|
|
-- spent in AUTO_SEND_ACK and AUTO_WAIT_REQ are long enough
|
|
-- to deassert CS. If that doesn't hold true in the future,
|
|
-- add another state.
|
|
auto_cnt_next <= CS_DELAY_RECOVERY;
|
|
auto_next <= AUTO_RECOVERY;
|
|
end if;
|
|
when AUTO_RECOVERY =>
|
|
if auto_cnt = 0 then
|
|
auto_next <= AUTO_IDLE;
|
|
end if;
|
|
end case;
|
|
end if;
|
|
end process;
|
|
|
|
-- Register write sync machine
|
|
reg_write: process(clk)
|
|
function reg_wr(r : in std_ulogic_vector;
|
|
w : in wb_io_master_out) return std_ulogic_vector is
|
|
variable b : natural range 0 to 31;
|
|
variable t : std_ulogic_vector(r'range);
|
|
begin
|
|
t := r;
|
|
for i in r'range loop
|
|
if w.sel(i/8) = '1' then
|
|
t(i) := w.dat(i);
|
|
end if;
|
|
end loop;
|
|
return t;
|
|
end function;
|
|
begin
|
|
if rising_edge(clk) then
|
|
-- Reset auto-clear
|
|
if rst = '1' or ctrl_reset = '1' then
|
|
ctrl_reset <= '0';
|
|
ctrl_cs <= '0';
|
|
ctrl_rsrv1 <= '0';
|
|
ctrl_rsrv2 <= '0';
|
|
ctrl_div <= std_ulogic_vector(to_unsigned(DEF_CLK_DIV, 8));
|
|
if DEF_QUAD_READ then
|
|
auto_cfg_cmd <= x"6b";
|
|
auto_cfg_dummies <= "111";
|
|
auto_cfg_mode <= SPI_AUTO_CFG_MODE_QUAD;
|
|
else
|
|
auto_cfg_cmd <= x"03";
|
|
auto_cfg_dummies <= "000";
|
|
auto_cfg_mode <= SPI_AUTO_CFG_MODE_SINGLE;
|
|
end if;
|
|
auto_cfg_addr4 <= '0';
|
|
auto_cfg_rsrv1 <= '0';
|
|
auto_cfg_rsrv2 <= '0';
|
|
auto_cfg_div <= std_ulogic_vector(to_unsigned(DEF_CLK_DIV, 8));
|
|
auto_cfg_cstout <= std_ulogic_vector(to_unsigned(DEFAULT_CS_TIMEOUT, 6));
|
|
end if;
|
|
|
|
if wb_reg_valid = '1' and wb_req.we = '1' and auto_state = AUTO_IDLE and bus_idle = '1' then
|
|
if wb_reg = SPI_REG_CTRL then
|
|
ctrl_reg <= reg_wr(ctrl_reg, wb_req);
|
|
end if;
|
|
if wb_reg = SPI_REG_AUTO_CFG then
|
|
auto_cfg_reg <= reg_wr(auto_cfg_reg, wb_req);
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
end architecture;
|
|
|