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fpu-init
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divider-init
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log2ceil-issue
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boxarty-20211011
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microwatt/litedram/gen-src
History
Benjamin Herrenschmidt dbb137437c acorn: Add support for the Acorn CLE 215+ 
This is a NiteFury based PCIe M2 form-factor board originally
used for mining. It contains a speed grade 2 Artix 7 200T,
1GB of DDR3 and 32MB of flash.

The serial port is routed to pin 2 (RX) and 3 (TX) of the P2
connector (pin 1 is GND).

Note: Only 16MB of flash is currently usable until code is added
to configure the flash controller to use 4-bytes address commands
on that part.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
sdram_init litedram: Update generator to work with latest LiteX 4 years ago
acorn-cle-215.yml acorn: Add support for the Acorn CLE 215+ 4 years ago
arty.yml litedram: Remove old "VexRiscV" based initializations 5 years ago
dram-init-mem.vhdl litedram: Update generator to work with latest LiteX 4 years ago
generate.py acorn: Add support for the Acorn CLE 215+ 4 years ago
genesys2.yml litedram: Add generator for Genesys2 4 years ago
nexys-video.yml litedram: Remove old "VexRiscV" based initializations 5 years ago
no-init-mem.vhdl litedram: Split the init memory from the main wrapper 5 years ago
sim.yml litedram: Remove old "VexRiscV" based initializations 5 years ago