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6cdb8ca9f5
clk_gen_bypass needed updating after the addition of CLK_INPUT_HZ and CLK_OUTPUT_HZ. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> |
5 years ago | |
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.. | ||
LICENSE | ||
arty_a7.xdc | 5 years ago | |
clk_gen_bypass.vhd | 5 years ago | |
clk_gen_mcmm.vhd | 5 years ago | |
clk_gen_plle2.vhd | 5 years ago | |
cmod_a7-35.xdc | 5 years ago | |
firmware.hex | ||
hello_world.hex | ||
mw_soc_memory.vhdl | 5 years ago | |
nexys-video.xdc | ||
nexys_a7.xdc | ||
pp_fifo.vhd | 5 years ago | |
pp_soc_uart.vhd | ||
pp_utilities.vhd | ||
soc_reset.vhdl | ||
soc_reset_tb.vhdl | ||
toplevel.vhdl | 5 years ago |