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Paul Mackerras
f06ffcf9b7
This adds a GPIO controller which provides 32 bits of I/O. The registers are modelled on the set used by the gpio-ftgpio010.c driver in the Linux kernel. Currently there is no interrupt capability implemented, though an interrupt line from the GPIO subsystem to the XICS has been connected. For the Arty A7 board, GPIO lines 0 to 13 are connected to the pins labelled IO0 to IO13 on the "shield" connector, GPIO lines 14 to 29 connect to IO26 to IO41, GPIO line 30 connects to the pin labelled A (aka IO42), and GPIO line 31 is connected to LED 7. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
4 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| acorn-cle-215.xdc | 4 years ago | |
| arty_a7.xdc | 4 years ago | |
| clk_gen_bypass.vhd | ||
| clk_gen_ecp5.vhd | 5 years ago | |
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | 4 years ago | |
| cmod_a7-35.xdc | 5 years ago | |
| firmware.hex | ||
| fpga-random.vhdl | 4 years ago | |
| fpga-random.xdc | 4 years ago | |
| genesys2.xdc | 4 years ago | |
| hello_world.hex | 5 years ago | |
| main_bram.vhdl | 5 years ago | |
| nexys-video.xdc | 5 years ago | |
| nexys_a7.xdc | 5 years ago | |
| pp_fifo.vhd | 5 years ago | |
| pp_soc_uart.vhd | 5 years ago | |
| pp_utilities.vhd | ||
| soc_reset.vhdl | 5 years ago | |
| soc_reset_tb.vhdl | 5 years ago | |
| top-acorn-cle-215.vhdl | 4 years ago | |
| top-arty.vhdl | 4 years ago | |
| top-generic.vhdl | 4 years ago | |
| top-genesys2.vhdl | 4 years ago | |
| top-nexys-video.vhdl | 4 years ago | |