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77 lines
2.4 KiB
VHDL
77 lines
2.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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entity clock_generator is
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generic (
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clk_period_hz : positive := 12000000);
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port (
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ext_clk : in std_logic;
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pll_rst_in : in std_logic;
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pll_clk_out : out std_logic;
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pll_locked_out : out std_logic);
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end entity clock_generator;
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architecture rtl of clock_generator is
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signal clkfb : std_ulogic;
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type pll_settings_t is record
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clkin_period : real range 10.000 to 800.0;
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clkfbout_mult : real range 2.0 to 64.0;
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clkout_divide : real range 1.0 to 128.0;
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divclk_divide : integer range 1 to 106;
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end record;
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function gen_pll_settings (
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constant freq_hz : positive)
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return pll_settings_t is
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begin
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if freq_hz = 100000000 then
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return (clkin_period => 10.0,
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clkfbout_mult => 16.0,
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clkout_divide => 32.0,
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divclk_divide => 1);
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elsif freq_hz = 12000000 then
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return (clkin_period => 83.33,
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clkfbout_mult => 50.0,
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clkout_divide => 12.0,
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divclk_divide => 1);
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else
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report "Unsupported input frequency" severity failure;
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end if;
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end function gen_pll_settings;
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constant pll_settings : pll_settings_t := gen_pll_settings(clk_period_hz);
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begin
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pll : MMCME2_BASE
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generic map (
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BANDWIDTH => "OPTIMIZED",
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CLKFBOUT_MULT_F => pll_settings.clkfbout_mult,
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CLKIN1_PERIOD => pll_settings.clkin_period,
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CLKOUT0_DIVIDE_F => pll_settings.clkout_divide,
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DIVCLK_DIVIDE => pll_settings.divclk_divide,
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STARTUP_WAIT => FALSE)
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port map (
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CLKFBOUT => clkfb,
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CLKFBOUTB => open,
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CLKOUT0 => pll_clk_out,
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CLKOUT0B => open,
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CLKOUT1 => open,
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CLKOUT1B => open,
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CLKOUT2 => open,
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CLKOUT2B => open,
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CLKOUT3 => open,
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CLKOUT3B => open,
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CLKOUT4 => open,
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CLKOUT5 => open,
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CLKOUT6 => open,
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LOCKED => pll_locked_out,
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CLKFBIN => clkfb,
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CLKIN1 => ext_clk,
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PWRDWN => '0',
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RST => pll_rst_in
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);
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end architecture rtl;
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