Fix issue #57, Add new aux vector entries for cache size and shape.

Signed-off-by: Bill Schmidt <wschmidt@linux.vnet.ibm.com>

specification/ch_4.xml

@@ -600,7 +600,16 @@ AT_SYSINFO_EHDR    33                    /* In many architectures, the kernel
                                             AT_SYSINFO_EHDR is the address of the
                                             VDSO header that is used by the
                                             dynamic linker to resolve function 
-                                         symbols with the VDSO. */</programlisting>
+                                            symbols with the VDSO. */
+AT_L1I_CACHESIZE      40                    /* Cache sizes and geometries. */
+AT_L1I_CACHEGEOMETRY  41
+AT_L1D_CACHESIZE      42
+AT_L1D_CACHEGEOMETRY  43
+AT_L2_CACHESIZE       44
+AT_L2_CACHEGEOMETRY   45
+AT_L3_CACHESIZE       46
+AT_L3_CACHEGEOMETRY   47
+	</programlisting>
         <para>AT_NULL</para>
         <para>The auxiliary vector has no fixed length; instead an entry of this
         type denotes the end of the vector. The corresponding value of a_un is
@@ -710,6 +719,31 @@ PPC_FEATURE2_HAS_IEEE128  0x00400000 /* VSX IEEE Binary Float 128-bit */</progra
         defined or predictable order. Further, the system may allocate memory
         after the null auxiliary vector entry and before the beginning of the
         information block.</para>
+	<para>AT_L1I_CACHESIZE</para>
+	<para>The size of the level-1 instruction cache, in bytes.</para>
+	<para>AT_L1I_CACHEGEOMETRY</para>
+	<para>The geometry of the level-1 instruction cache.  The low-order
+	sixteen bits contain the cache associativity as a value N, where
+	N = 1 represents a direct-mapped cache, N = 0xffff represents a
+	fully associative cache, and any other N represents an N-way
+	set-associative cache.  The next higher-order sixteen bits contain
+	the size of the cache line in bytes.  Note that the cache line
+	size is not necessarily the same as the cache block size.</para>
+	<para>AT_L1D_CACHESIZE</para>
+	<para>The size of the level-1 data cache, in bytes.</para>
+	<para>AT_L1D_CACHEGEOMETRY</para>
+	<para>The geometry of the level-1 data cache, defined in the same
+	manner as for AT_L1I_CACHEGEOMETRY.</para>
+	<para>AT_L2_CACHESIZE</para>
+	<para>The size of the level-2 cache, in bytes.</para>
+	<para>AT_L2_CACHEGEOMETRY</para>
+	<para>The geometry of the level-2 cache, defined in the same
+	manner as for AT_L1I_CACHEGEOMETRY.</para>
+	<para>AT_L3_CACHESIZE</para>
+	<para>The size of the level-3 cache, in bytes.</para>
+	<para>AT_L3_CACHEGEOMETRY</para>
+	<para>The geometry of the level-3 cache, defined in the same
+	manner as for AT_L1I_CACHEGEOMETRY.</para>
       </section>
     </section>
   </section>