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Avoid misleading uses of r12; add new PPC_FEATURE2_ bits.

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Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>
master
Bill Schmidt 5 years ago
parent 6984303ef0
commit ee46fb7bb5
4 changed files with 47 additions and 35 deletions
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16
specification/bk_main.xml
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@ -37,7 +37,7 @@
</author>
<copyright>
<!-- TODO: Keep second year accurate for latest publish -->
<year>2014-2018</year>
<year>2014-2019</year>
<holder>OpenPOWER Foundation</holder>
</copyright>
<copyright>
@ -57,7 +57,7 @@
<holder>Freescale Semiconductor, Inc</holder>
</copyright>
<!-- TODO: Set the correct document releaseinfo -->
<releaseinfo>Revision 1.5h draft</releaseinfo>
<releaseinfo>Revision 1.5i draft</releaseinfo>
<productname>OpenPOWER</productname>
<pubdate/>

@ -94,7 +94,17 @@
<revhistory>
<!-- TODO: Set the initial version information and clear any old information out -->
<revision>
<date>2018-12-20</date>
<date>2019-04-16</date>
<revdescription>
<itemizedlist spacing="compact">
<listitem>
<para>Revision 1.5i: Changes from compiler workshop.</para>
</listitem>
</itemizedlist>
</revdescription>
</revision>
<revision>
<date>2019-02-01</date>
<revdescription>
<itemizedlist spacing="compact">
<listitem>

44
specification/ch_2.xml
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@ -6645,8 +6645,8 @@ s6 - 72 (stored)</programlisting>
instructions:</para>
</listitem>
</itemizedlist>
<programlisting>lis r16, symbol@ha
ld r12, symbol@l(r16)
<programlisting revisionflag="changed">lis r16, symbol@hba
ld r10, symbol@l(r16)

lis r16, symbol2@ha
addi r16, r16, symbol2@l
@ -6658,8 +6658,8 @@ lvx v1, r0, r16</programlisting>
<xref linkend="dbdoclet.50655241_66700" />.)</para>
</listitem>
</itemizedlist>
<programlisting>&lt;load TOC base to r2&gt;
ld r12, symbol@toc(r2)
<programlisting revisionflag="changed">&lt;load TOC base to r2&gt;
ld r10, symbol@toc(r2)

li r16, symbol2@toc
lvx v1, r2, r16</programlisting>
@ -6669,13 +6669,13 @@ lvx v1, r2, r16</programlisting>
addressing:</para>
</listitem>
</itemizedlist>
<programlisting>&lt;load TOC base to r2&gt;
<programlisting revisionflag="changed">&lt;load TOC base to r2&gt;

ld r12, symbol@got(r2)
ld r12, 0(r12)
ld r10, symbol@got(r2)
ld r10, 0(r10)

ld r12, symbol2@got(r2)
lvx v1, 0, r12</programlisting>
ld r10, symbol2@got(r2)
lvx v1, 0, r10</programlisting>
<itemizedlist>
<listitem>
<para revisionflag="added">
@ -6683,7 +6683,7 @@ lvx v1, 0, r12</programlisting>
</para>
</listitem>
</itemizedlist>
<programlisting revisionflag="added">pld r12, symbol@pcrel
<programlisting revisionflag="added">pld r10, symbol@pcrel

plxv v1, symbol@pcrel</programlisting>
<para>In the OpenPOWER ELF V2 ABI, position-dependent code built with
@ -6769,9 +6769,9 @@ plxv v1, symbol@pcrel</programlisting>
relative addressing (for private data).</para>
</listitem>
</itemizedlist>
<programlisting>&lt;load TOC base to r2&gt;
<programlisting revisionflag="changed">&lt;load TOC base to r2&gt;

ld r12, symbol@toc(r2)
ld r10, symbol@toc(r2)

li r16, symbol2@toc
lvx v1, r2, r16</programlisting>
@ -6782,21 +6782,21 @@ lvx v1, r2, r16</programlisting>
sections):</para>
</listitem>
</itemizedlist>
<programlisting>&lt;load TOC base to r2&gt;
<programlisting revisionflag="changed">&lt;load TOC base to r2&gt;

ld r12, symbol@got(r2)
ld r10, symbol@got(r2)

ld r12, 0(r12)
ld r10, 0(r10)

ld r12 symbol2@got(r2)
lvx v1, 0, r12</programlisting>
ld r10, symbol2@got(r2)
lvx v1, 0, r10</programlisting>
<itemizedlist>
<listitem>
<para revisionflag="added">By using PC-relative addressing (for
private data).</para>
</listitem>
</itemizedlist>
<programlisting revisionflag="added">pld r12, symbol@pcrel
<programlisting revisionflag="added">pld r10, symbol@pcrel

plxv v1, symbol@pcrel</programlisting>
<itemizedlist>
@ -6806,11 +6806,11 @@ plxv v1, symbol@pcrel</programlisting>
</para>
</listitem>
</itemizedlist>
<programlisting revisionflag="added">pld r12, symbol@got@pcrel
ld r12, 0(r12)
<programlisting revisionflag="added">pld r10, symbol@got@pcrel
ld r10, 0(r10)

pld r12, symbol@got@pcrel
lvx v1, 0, r12</programlisting>
pld r10, symbol@got@pcrel
lvx v1, 0, r10</programlisting>
<para revisionflag="added">
A compiler may generate a PC-relative addressing sequence to access
static or restricted-visibility data, but must generate a PC-relative

18
specification/ch_3.xml
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@ -5350,15 +5350,15 @@ target:
and replace the reference with direct PC-relative addressing.
For example:
</para>
<programlisting>pld r12, symbol@got@pcrel
lvx v1, 0, r12</programlisting>
<programlisting>pld r10, symbol@got@pcrel
lvx v1, 0, r10</programlisting>
<para>The previous sequence may be replaced by:</para>
<programlisting>plxv v1, symbol@pcrel
nop</programlisting>
<para>
However, this optimization is not universally safe, since it
changes the value of r12 following the data reference. The
compiler or programmer must ensure that the value of r12 is not
changes the value of r10 following the data reference. The
compiler or programmer must ensure that the value of r10 is not
subsequently used, and communicate a request for this optimization
by placing an R_PPC64_PCREL_OPT relocation on the first instruction
in the sequence. The compiler or programmer must further ensure that
@ -5375,19 +5375,19 @@ nop</programlisting>
of these instructions, but may instead generate a short sequence
that can be optimized by a linker. For example:
</para>
<programlisting>paddi r12,symbol@pcrel
pmlxvx v1,r10,r12,VRM,MC,P,0</programlisting>
<programlisting>paddi r10,symbol@pcrel
pmlxvx v1,r9,r10,VRM,MC,P,0</programlisting>
<para>The previous sequence may be replaced by:</para>
<programlisting>dnop
pmlxv v1,symbol@pcrel(r10),VRM,MC,P,1</programlisting>
pmlxv v1,symbol@pcrel(r9),VRM,MC,P,1</programlisting>
<para>
when the linker determines that the offset from the current
instruction address to symbol's address will fit in 28 bits.
</para>
<para>
Again, this optimization is not universally safe, since it changes
the value of r12 following the data reference. The compiler or
programmer must ensure that the value of r12 is not subsequently
the value of r10 following the data reference. The compiler or
programmer must ensure that the value of r10 is not subsequently
used, and communicate a request for this optimization by placing
an R_PPC64_PCREL_OPT relocation on the first instruction in the
sequence. The compiler or programmer must further ensure that the

4
specification/ch_4.xml
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@ -716,7 +716,9 @@ PPC_FEATURE2_ARCH_3_00 0x00800000 /* ISA 3.0 */
PPC_FEATURE2_HAS_IEEE128 0x00400000 /* VSX IEEE Binary Float 128-bit */
PPC_FEATURE2_DARN 0x00200000 /* darn instruction */
PPC_FEATURE2_SCV 0x00100000 /* scv syscall */
PPC_FEATURE2_HTM_NO_SUSPEND 0x00080000 /* TM without suspended state */</programlisting>
PPC_FEATURE2_HTM_NO_SUSPEND 0x00080000 /* TM without suspended state */
PPC_FEATURE2_ARCH_3_1 0x00040000 /* ISA 3.1 */
PPC_FEATURE2_MMA 0x00020000 /* Matrix Multiply Accumulate */</programlisting>
<para>When a process starts to execute, its stack holds the arguments,
environment, and auxiliary vector received from the exec call. The system
makes no guarantees about the relative arrangement of argument strings,

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