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7
Intrinsics_Reference/bk_main.xml
Unescape Escape View File

@ -54,7 +54,7 @@
<holder>OpenPOWER Foundation</holder> <holder>OpenPOWER Foundation</holder>
</copyright> </copyright>
<!-- TODO: Set the correct document releaseinfo --> <!-- TODO: Set the correct document releaseinfo -->
<releaseinfo>Revision 2.0.0_prd</releaseinfo> <releaseinfo>Revision 2.0.0</releaseinfo>
<productname>OpenPOWER</productname> <productname>OpenPOWER</productname>
<pubdate/> <pubdate/>


@ -88,11 +88,11 @@
<revhistory> <revhistory>
<!-- TODO: Set the initial version information and clear any old information out --> <!-- TODO: Set the initial version information and clear any old information out -->
<revision> <revision>
<date>2021-09-08</date> <date>2020-10-05</date>
<revdescription> <revdescription>
<itemizedlist spacing="compact"> <itemizedlist spacing="compact">
<listitem> <listitem>
<para>Version 2.0.0_prd public review draft</para> <para>Version 2.0_pre pre-review draft</para>
</listitem> </listitem>
</itemizedlist> </itemizedlist>
</revdescription> </revdescription>
@ -121,7 +121,6 @@
<xi:include href="ch_techniques.xml"/> <xi:include href="ch_techniques.xml"/>
<xi:include href="ch_vec_reference.xml"/> <xi:include href="ch_vec_reference.xml"/>
<!-- xi:include href="ch_scal_reference.xml"/ --> <!-- xi:include href="ch_scal_reference.xml"/ -->
<xi:include href="ch_mma_reference.xml"/>
<xi:include href="ch_isa_intrin_xref.xml"/> <xi:include href="ch_isa_intrin_xref.xml"/>
<!-- xi:include href="app_a.xml"/ --> <!-- xi:include href="app_a.xml"/ -->



298
Intrinsics_Reference/ch_biendian.xml
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@ -151,8 +151,8 @@ vector unsigned __int128 x = { (((unsigned __int128)0x1020304050607080) &lt;&lt;
it. it.
</para> </para>
<para> <para>
For the Fortran language, <phrase revisionflag="changed"><xref For the Fortran language, <xref
linkend="VIPR.biendian.fortrantypes" /></phrase> gives a correspondence linkend="VIPR.biendian.fortran-types" /> gives a correspondence
between Fortran and C/C++ language types. between Fortran and C/C++ language types.
</para> </para>
<para> <para>
@ -787,6 +787,10 @@ a[3] = c;</programlisting>
thus are not "endian-sensitive." A complete list of thus are not "endian-sensitive." A complete list of
endian-sensitive built-in functions can be found in <xref endian-sensitive built-in functions can be found in <xref
linkend="VIPR.biendian.sensitive" />. linkend="VIPR.biendian.sensitive" />.
</para>
<para revisionflag="added">
Be sure to update this table for any new endian-sensitive
built-ins added for P10.
</para> </para>
<table frame="all" pgwide="1" xml:id="VIPR.biendian.sensitive"> <table frame="all" pgwide="1" xml:id="VIPR.biendian.sensitive">
<title>Endian-Sensitive Built-In Functions</title> <title>Endian-Sensitive Built-In Functions</title>
@ -800,16 +804,10 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_bperm" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_bperm" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_mergeh" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_inserth"
xrefstyle="select:title nopage"/></code>
</para>
</entry> </entry>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_signedo" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_signextll"
xrefstyle="select:title nopage"/></code>
</para>
</entry> </entry>
</row> </row>
<row> <row>
@ -817,24 +815,7 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_cipher_be" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_cipher_be" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_mergel" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_insertl"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_signextq"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_cipherlast_be" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_mergee" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_sld" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_sld" xrefstyle="select:title nopage"/></code></para>
@ -842,30 +823,10 @@ a[3] = c;</programlisting>
</row> </row>
<row> <row>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_cipherlast_be" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_clr_first"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_mergeh" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_sldb" xrefstyle="select:title
nopage"/></code>
</para>
</entry>
</row>
<row>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_clr_last"
xrefstyle="select:title nopage"/></code>
</para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_mergel" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_mergeo" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_sldw" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_sldw" xrefstyle="select:title nopage"/></code></para>
@ -876,7 +837,7 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_doublee" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_doublee" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_mergeo" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_mfvscr" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_sll" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_sll" xrefstyle="select:title nopage"/></code></para>
@ -887,7 +848,7 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_doubleh" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_doubleh" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_mfvscr" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_mule" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_slo" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_slo" xrefstyle="select:title nopage"/></code></para>
@ -898,7 +859,7 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_doublel" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_doublel" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_mule" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_mulo" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_slv" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_slv" xrefstyle="select:title nopage"/></code></para>
@ -909,7 +870,7 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_doubleo" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_doubleo" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_mulo" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_ncipher_be" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_splat" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_splat" xrefstyle="select:title nopage"/></code></para>
@ -920,13 +881,10 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_extract" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_extract" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_ncipher_be" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_ncipherlast_be" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_srl" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_splati_ins"
xrefstyle="select:title nopage"/></code>
</para>
</entry> </entry>
</row> </row>
<row> <row>
@ -934,13 +892,10 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_extract_fp32_from_shorth" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_extract_fp32_from_shorth" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_ncipherlast_be" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_pack" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_sro" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_srdb" xrefstyle="select:title
nopage"/></code>
</para>
</entry> </entry>
</row> </row>
<row> <row>
@ -948,10 +903,10 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_extract_fp32_from_shortl" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_extract_fp32_from_shortl" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_pack" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_pack_to_short_fp32" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_srl" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_srv" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
</row> </row>
<row> <row>
@ -959,234 +914,122 @@ a[3] = c;</programlisting>
<para><code><xref linkend="vec_extract4b" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_extract4b" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_pack_to_short_fp32" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_packpx" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_sro" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_sum2s" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
</row> </row>
<row> <row>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_first_match_index" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_extracth"
xrefstyle="select:title nopage"/></code>
</para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_packpx" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_packs" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_srv" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_sums" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
</row> </row>
<row> <row>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_first_match_or_eos_index" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_extractl"
xrefstyle="select:title nopage"/></code>
</para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_packs" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_packsu" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_unpackh" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_stril"
xrefstyle="select:title nopage"/></code>
</para>
</entry> </entry>
</row> </row>
<row> <row>
<entry> <entry>
<para><code><xref linkend="vec_first_match_index" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_first_mismatch_index" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_packsu" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_perm" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_unpackl" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_stril_p"
xrefstyle="select:title nopage"/></code>
</para>
</entry> </entry>
</row> </row>
<row> <row>
<entry> <entry>
<para><code><xref linkend="vec_first_match_or_eos_index" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_first_mismatch_or_eos_index" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_perm" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_permxor" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_unsigned2" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_strir"
xrefstyle="select:title nopage"/></code>
</para>
</entry> </entry>
</row> </row>
<row> <row>
<entry> <entry>
<para><code><xref linkend="vec_first_mismatch_index" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_float2" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_pmsum_be" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_permx" </entry>
xrefstyle="select:title nopage"/></code> <entry>
</para> <para><code><xref linkend="vec_unsignede" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_strir_p"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
</row> </row>
<row> <row>
<entry> <entry>
<para><code><xref linkend="vec_first_mismatch_or_eos_index" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_floate" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_permxor" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_reve" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_unsignedo" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry>
<para><code><xref linkend="vec_sum2s" xrefstyle="select:title nopage"/></code></para>
</entry>
</row> </row>
<row> <row>
<entry> <entry>
<para><code><xref linkend="vec_float2" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_floato" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_pmsum_be" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_sbox_be" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_xl" xrefstyle="select:title nopage"/></code> (ISA 2.07 only)</para>
</entry> </entry>
<entry>
<para><code><xref linkend="vec_sums" xrefstyle="select:title nopage"/></code></para>
</entry>
</row> </row>
<row> <row>
<entry> <entry>
<para><code><xref linkend="vec_floate" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_insert" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_shasigma_be" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_replace_elt"
xrefstyle="select:title nopage"/></code>
</para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_unpackh" <para><code><xref linkend="vec_xl_be" xrefstyle="select:title nopage"/></code></para>
xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
</row> </row>
<row> <row>
<entry>
<para><code><xref linkend="vec_floato" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_replace_unaligned"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry> <entry>
<para><code><xref linkend="vec_unpackl" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_insert4b" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
</row>
<row>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_genbm"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_reve" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry> <entry>
<para><code><xref linkend="vec_unsigned2" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_signed2" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
</row>
<row>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_gendm"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_sbox_be" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry> <entry>
<para><code><xref linkend="vec_unsignede" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_xst" xrefstyle="select:title nopage"/></code> (ISA 2.07 only)</para>
</entry> </entry>
</row> </row>
<row> <row>
<entry> <entry>
<para revisionflag="added"> <para><code><xref linkend="vec_mergee" xrefstyle="select:title nopage"/></code></para>
<code><xref linkend="vec_genhm" </entry>
xrefstyle="select:title nopage"/></code> <entry>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_shasigma_be" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_unsignedo" xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
<row>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_genpcvm"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_signed2" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_xl" xrefstyle="select:title nopage"/></code> (ISA 2.07 only)</para>
</entry>
</row>
<row>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_genwm"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_signede" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_signede" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
<entry> <entry>
<para><code><xref linkend="vec_xl_be" xrefstyle="select:title nopage"/></code></para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_insert" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_signedo" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para><code><xref linkend="vec_xst" xrefstyle="select:title nopage"/></code> (ISA 2.07 only)</para>
</entry>
</row>
<row>
<entry>
<para><code><xref linkend="vec_insert4b" xrefstyle="select:title nopage"/></code></para>
</entry>
<entry>
<para revisionflag="added">
<code><xref linkend="vec_signexti"
xrefstyle="select:title nopage"/></code>
</para>
</entry>
<entry>
<para><code><xref linkend="vec_xst_be" xrefstyle="select:title nopage"/></code></para> <para><code><xref linkend="vec_xst_be" xrefstyle="select:title nopage"/></code></para>
</entry> </entry>
</row> </row>
</tbody> </tbody>
</tgroup> </tgroup>
</table> </table>
@ -1340,14 +1183,13 @@ a[3] = c;</programlisting>
introduced serious compiler complexity without much utility. introduced serious compiler complexity without much utility.
Thus this support (previously controlled by switches Thus this support (previously controlled by switches
<code>-maltivec=be</code> and/or <code>-qaltivec=be</code>) is <code>-maltivec=be</code> and/or <code>-qaltivec=be</code>) is
now deprecated. Current versions of the <phrase now deprecated. Current versions of the GCC and Clang
revisionflag="changed">GCC, Clang, and Open XL</phrase> open-source compilers do not implement this support.
compilers do not implement this support.
</para> </para>
</section> </section>
</section> </section>


<section revisionflag="deleted"> <section>
<title>Language-Specific Vector Support for Other <title>Language-Specific Vector Support for Other
Languages</title> Languages</title>
<section> <section>

79
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@ -23,17 +23,13 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
<section> <section>
<title>A Brief History</title> <title>A Brief History</title>
<para> <para>
The history of vector programming on <phrase The history of vector programming on Power processors begins
revisionflag="changed"><trademark
class="registered">Power</trademark></phrase> processors begins
with the AIM (Apple, IBM, Motorola) alliance in the 1990s. The with the AIM (Apple, IBM, Motorola) alliance in the 1990s. The
AIM partners developed the Power Vector Media Extension (VMX) to AIM partners developed the Power Vector Media Extension (VMX) to
accelerate multimedia applications, particularly image accelerate multimedia applications, particularly image
processing. VMX is the name still used by IBM for this processing. VMX is the name still used by IBM for this
instruction set. Freescale (formerly Motorola) used the instruction set. Freescale (formerly Motorola) used the
trademark <phrase revisionflag="changed"><trademark trademark "AltiVec," while Apple at one time called it "Velocity
class="trade">AltiVec</trademark>,</phrase> while Apple at one
time called it "Velocity
Engine." While VMX remains the most official name, the term Engine." While VMX remains the most official name, the term
AltiVec is still in common use today. Freescale's AltiVec AltiVec is still in common use today. Freescale's AltiVec
Technology Programming Interface Manual (the "AltiVec PIM") is Technology Programming Interface Manual (the "AltiVec PIM") is
@ -72,14 +68,11 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
also included AltiVec support, and was used in the Apple also included AltiVec support, and was used in the Apple
PowerMac G5. IBM initially omitted support for VMX from its PowerMac G5. IBM initially omitted support for VMX from its
server-class computers, but added support for it in the POWER6 server-class computers, but added support for it in the POWER6
<phrase revisionflag="added">processor-based</phrase> server server family.
family.
</para> </para>
<para> <para>
IBM extended VMX by introducing the Vector-Scalar Extension IBM extended VMX by introducing the Vector-Scalar Extension
(VSX) for the <phrase revisionflag="changed"><trademark (VSX) for the POWER7 family of processors. VSX adds sixty-four
class="registered">POWER7</trademark></phrase> family of
processors. VSX adds sixty-four
128-bit vector-scalar registers (VSRs); however, to optimize the amount 128-bit vector-scalar registers (VSRs); however, to optimize the amount
of per-process register state, the registers overlap with the of per-process register state, the registers overlap with the
VRs and the scalar floating-point registers (FPRs) (see <xref VRs and the scalar floating-point registers (FPRs) (see <xref
@ -87,18 +80,13 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
the data types representable by the VRs, and can also be treated the data types representable by the VRs, and can also be treated
as containing two 64-bit integers or two 64-bit double-precision as containing two 64-bit integers or two 64-bit double-precision
floating-point values. However, ISA support for two 64-bit floating-point values. However, ISA support for two 64-bit
integers in VSRs was limited until Version 2.07 (<phrase integers in VSRs was limited until Version 2.07 (POWER8) of the
revisionflag="changed"><trademark
class="registered">POWER8</trademark></phrase>) of the
Power ISA, and only the VRs are supported for these Power ISA, and only the VRs are supported for these
instructions. instructions.
</para> </para>
<para> <para>
Both the VMX and VSX instruction sets have been expanded for the Both the VMX and VSX instruction sets have been expanded for the
<phrase revisionflag="changed">POWER8, <trademark POWER8 and POWER9 processor families. Starting with POWER8,
class="registered">POWER9</trademark>, and <trademark
class="registered">Power10</trademark></phrase> processor
families. Starting with POWER8,
a VSR can now contain a single 128-bit integer; and starting a VSR can now contain a single 128-bit integer; and starting
with POWER9, a VSR can contain a single 128-bit IEEE floating-point with POWER9, a VSR can contain a single 128-bit IEEE floating-point
value. Again, the ISA currently only supports 128-bit value. Again, the ISA currently only supports 128-bit
@ -109,16 +97,17 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
the Power SIMD (single-instruction, multiple-data) the Power SIMD (single-instruction, multiple-data)
instructions. instructions.
</para> </para>
<para revisionflag="added">
Write an introductory paragraph about the MMA facility and the
ACC registers.
</para>
<section> <section>
<title>Little-Endian Linux</title> <title>Little-Endian Linux</title>
<para> <para>
The Power architecture has supported operation in either The Power architecture has supported operation in either
big-endian (BE) or little-endian (LE) mode from the big-endian (BE) or little-endian (LE) mode from the
beginning. However, IBM's Power servers were only shipped beginning. However, IBM's Power servers were only shipped
with big-endian operating systems (<phrase with big-endian operating systems (AIX, Linux, i5/OS) prior to
revisionflag="changed"><trademark
class="registered">AIX</trademark>, IBM i, <trademark
class="registered">Linux</trademark></phrase>) prior to
the introduction of POWER8. With POWER8, IBM began the introduction of POWER8. With POWER8, IBM began
supporting little-endian Linux distributions for the first supporting little-endian Linux distributions for the first
time, and introduced a new application binary interface (the time, and introduced a new application binary interface (the
@ -150,9 +139,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
<section xml:id="VIPR.intro.unified"> <section xml:id="VIPR.intro.unified">
<title>The Unified Vector Register Set</title> <title>The Unified Vector Register Set</title>
<para> <para>
In <phrase revisionflag="changed"><trademark In OpenPOWER-compliant processors, floating-point and vector
class="trade">OpenPOWER</trademark>-compliant</phrase>
processors, floating-point and vector
operations are implemented using a unified vector-scalar model. operations are implemented using a unified vector-scalar model.
As shown in <xref linkend="FPR-VSR" /> and <xref As shown in <xref linkend="FPR-VSR" /> and <xref
linkend="VR-VSR" />, there are 64 vector-scalar registers; each linkend="VR-VSR" />, there are 64 vector-scalar registers; each
@ -218,15 +205,11 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
</listitem> </listitem>
<listitem> <listitem>
<para> <para>
<emphasis role="underline">The XL <phrase <emphasis role="underline">The XL compilers</emphasis>. For
revisionflag="added">and Open XL</phrase> XL compilers provided with the Linux Community Edition, you
compilers</emphasis>. For XL <phrase can provide feedback to the XL compiler team via email
revisionflag="added">and Open XL</phrase> compilers provided
with the Linux Community Edition, you can provide feedback
to the XL compiler team via email
(<email>compinfo@cn.ibm.com</email>); for other editions of (<email>compinfo@cn.ibm.com</email>); for other editions of
XL <phrase revisionflag="added">and Open XL</phrase> XL compilers, please open a <link
compilers, please open a <link
xlink:href="https://www.ibm.com/mysupport/s/">Case</link>. xlink:href="https://www.ibm.com/mysupport/s/">Case</link>.
</para> </para>
</listitem> </listitem>
@ -308,7 +291,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
</listitem> </listitem>
<listitem revisionflag="added"> <listitem revisionflag="added">
<para> <para>
<emphasis>Power10 Processor User's Manual.</emphasis> <emphasis>POWER10 Processor User's Manual.</emphasis>
<emphasis> <emphasis>
<link <link
xlink:href="https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k">Not xlink:href="https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k">Not
@ -356,37 +339,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
</emphasis> </emphasis>
</para> </para>
</listitem> </listitem>
<listitem revisionflag="added">
<para>
<emphasis>The GNU C Library Project.</emphasis>
<emphasis>
<link xlink:href="https://www.gnu.org/software/libc">https://www.gnu.org/software/libc</link>
</emphasis>
</para>
</listitem>
<listitem revisionflag="added">
<para>
<emphasis>Matrix-Multiply Assist Best Practices Guide.</emphasis>
<emphasis>
<link xlink:href="http://www.redbooks.ibm.com/redpapers/pdfs/redp5612.pdf">https://www.redbooks.ibm.com/redpapers/pdfs/redp5612.pdf</link>
</emphasis>
</para>
</listitem>
</itemizedlist> </itemizedlist>
</section> </section>


<section xml:id="VIPR.intro.marks" revisionflag="added">
<title>Trademarks</title>
<para>
AIX, POWER7, POWER8, POWER9, and Power10 are trademarks or
registered trademarks of International Business Machines
Corporation. Linux is a registered trademark of Linus
Torvalds. Intel is a registered trademark of Intel Corporation
or its subsidiaries. AltiVec is a trademark of Freescale
Semiconductor, Inc.
</para>
</section>

<section xml:id="VIPR.intro.conf"> <section xml:id="VIPR.intro.conf">
<title>Conformance to this Specification</title> <title>Conformance to this Specification</title>
<orderedlist> <orderedlist>

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36
Intrinsics_Reference/ch_techniques.xml
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@ -113,10 +113,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques">
references. (<code>restrict</code> can be used only in C references. (<code>restrict</code> can be used only in C
when compiling for the C99 standard or later. when compiling for the C99 standard or later.
<code>__restrict__</code> is a language extension, available <code>__restrict__</code> is a language extension, available
in GCC, Clang, and the XL <phrase revisionflag="added">and in GCC, Clang, and the XL compilers, that can be used
Open XL</phrase> compilers, that can be used without without restriction for both C and C++. See your compiler's
restriction for both C and C++. See your compiler's user user manual for details.)
manual for details.)
</para> </para>
<para> <para>
Suppose you have a function that takes two pointer Suppose you have a function that takes two pointer
@ -143,9 +142,8 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques">
</para> </para>
<para> <para>
This reference provides intrinsics that are guaranteed to be This reference provides intrinsics that are guaranteed to be
portable across compliant compilers. In particular, the <phrase portable across compliant compilers. In particular, both the
revisionflag="changed">GCC, Clang, and Open XL</phrase> GCC and Clang compilers for Power implement the intrinsics in
compilers for Power implement the intrinsics in
this manual. The compilers may each implement many more this manual. The compilers may each implement many more
intrinsics, but the ones in this manual are the only ones intrinsics, but the ones in this manual are the only ones
guaranteed to be portable. So if you are using an interface not guaranteed to be portable. So if you are using an interface not
@ -206,15 +204,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques">
responsible for following the calling conventions established by responsible for following the calling conventions established by
the ABI (see <xref linkend="VIPR.intro.links" />). Again, it is the ABI (see <xref linkend="VIPR.intro.links" />). Again, it is
best to look at examples. One place to find well-written best to look at examples. One place to find well-written
<code>.S</code> files is in the <phrase <code>.S</code> files is in the GLIBC project. You can also
revisionflag="changed">GNU C Library project (see <xref
linkend="VIPR.intro.links" />).</phrase> You can also
study the assembly output from your favorite compiler, which can study the assembly output from your favorite compiler, which can
be obtained with the <code>-S</code> or similar option, or by be obtained with the <code>-S</code> or similar option, or by
using the <emphasis role="bold">objdump</emphasis> utility: using the <emphasis role="bold">objdump</emphasis> utility.
</para>
<para revisionflag="added">
<programlisting> objdump -dr &lt;binary or object file&gt;</programlisting>
</para> </para>
</section> </section>


@ -226,12 +219,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques">
<section> <section>
<title>x86 Vector Portability Headers</title> <title>x86 Vector Portability Headers</title>
<para> <para>
Recent versions of the <phrase revisionflag="changed">GCC, Recent versions of the GCC and Clang open-source compilers
Clang, and Open XL</phrase> compilers
for Power provide "drop-in" portability headers for portions for Power provide "drop-in" portability headers for portions
of the <phrase revisionflag="changed"><trademark of the Intel Architecture Instruction Set Extensions (see <xref
class="registered">Intel</trademark></phrase> Architecture
Instruction Set Extensions (see <xref
linkend="VIPR.intro.links" />). These headers mirror the APIs linkend="VIPR.intro.links" />). These headers mirror the APIs
of Intel headers having the same names. As of this writing, of Intel headers having the same names. As of this writing,
support is provided for the MMX and SSE layers, up through support is provided for the MMX and SSE layers, up through
@ -253,18 +243,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques">
<para> <para>
Access to the portability APIs occurs automatically when Access to the portability APIs occurs automatically when
including one of the corresponding Intel header files, such as including one of the corresponding Intel header files, such as
<code>&lt;mmintrin.h&gt;</code>. <phrase <code>&lt;mmintrin.h&gt;</code>.
revisionflag="added">To enable the portability headers, you
must compile with
<code>-DNO_WARN_X86_INTRINSICS</code>.</phrase>
</para> </para>
</section> </section>
<section xml:id="VIPR.techniques.pveclib"> <section xml:id="VIPR.techniques.pveclib">
<title>The Power Vector Library (pveclib)</title> <title>The Power Vector Library (pveclib)</title>
<para>The Power Vector Library, also known as <para>The Power Vector Library, also known as
<code>pveclib</code>, is a separate project available from <code>pveclib</code>, is a separate project available from
<phrase revisionflag="changed">GitHub</phrase> (see <xref github (see <xref linkend="VIPR.intro.links" />). The
linkend="VIPR.intro.links" />). The
<code>pveclib</code> project builds on top of the intrinsics <code>pveclib</code> project builds on top of the intrinsics
described in this manual to provide higher-level vector described in this manual to provide higher-level vector
interfaces that are highly portable. The goals of the project interfaces that are highly portable. The goals of the project

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3
README.md
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@ -37,7 +37,8 @@ This can be accomplished with the following steps:
The project which controls the look and feel of the document is the The project which controls the look and feel of the document is the
[Docs-Maven-Plugin project](https://github.com/OpenPOWERFoundation/Docs-Maven-Plugin), an [Docs-Maven-Plugin project](https://github.com/OpenPOWERFoundation/Docs-Maven-Plugin), an
OpenPOWER Foundation private project on GitHub. To obtain access to the Maven Plugin project, OpenPOWER Foundation private project on GitHub. To obtain access to the Maven Plugin project,
contact TSC Chair of the OpenPOWER Foundation \([tsc-chair@openpowerfoundation.org](mailto://tsc-chair@openpowerfoundation.org)\) or contact Jeff Scheel \([scheel@us.ibm.com](mailto://scheel@us.ibm.com)\) or
Jeff Brown \([jeffdb@us.ibm.com](mailto://jeffdb@us.ibm.com)\).


## License ## License
This project is licensed under the Apache V2 license. More information This project is licensed under the Apache V2 license. More information

4
pvipr-errata-1.0/bk_main.xml
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@ -82,11 +82,11 @@
<revhistory> <revhistory>
<!-- TODO: Set the initial version information and clear any old information out --> <!-- TODO: Set the initial version information and clear any old information out -->
<revision> <revision>
<date>2021-06-09</date> <date>2021-04-07</date>
<revdescription> <revdescription>
<itemizedlist spacing="compact"> <itemizedlist spacing="compact">
<listitem> <listitem>
<para>Revision 1.0</para> <para>Initial draft</para>
</listitem> </listitem>
</itemizedlist> </itemizedlist>
</revdescription> </revdescription>

8
pvipr-errata-1.0/pom.xml
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@ -112,9 +112,9 @@
other Foundation members or the public other Foundation members or the public


The appropriate starting security for a new document is "workgroupConfidential". --> The appropriate starting security for a new document is "workgroupConfidential". -->
<!-- security>workgroupConfidential</security --> <security>workgroupConfidential</security>
<!-- security>foundationConfidential</security --> <!-- security>foundationConfidential</security -->
<security>public</security> <!-- security>public</security -->


<!-- TODO: Set the appropriate work flow status for the document. For documents <!-- TODO: Set the appropriate work flow status for the document. For documents
which are not "published" this will affect the document title page which are not "published" this will affect the document title page
@ -129,9 +129,9 @@
review = this document is presently being reviewed review = this document is presently being reviewed


The appropriate starting security for a new document is "draft". --> The appropriate starting security for a new document is "draft". -->
<!-- documentStatus>draft</documentStatus --> <documentStatus>draft</documentStatus>
<!-- documentStatus>review</documentStatus --> <!-- documentStatus>review</documentStatus -->
<documentStatus>published</documentStatus> <!-- documentStatus>published</documentStatus -->
</configuration> </configuration>
</execution> </execution>
</executions> </executions>

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