add all specifications

* add/sanitize all specification documents
* add/sanitize all version of a specification
* move to single vesioned documents
* rename pages to be generic names
* update template single layout to include tags and better layout

Signed-off-by: Toshaan Bharvani <toshaan@vantosh.com>

content/specifications/64bitelfabi.md

@@ -1,11 +1,16 @@
 ---
-title: 64-bit ELF v2 ABI Specification for OpenPOWER Architecture
+title: 64-bit ELF ABI Specification for OpenPOWER Architecture
+group: systemsoftware
 publicreview: false
+aliases:
+  - "64bitelfv2abi/"
+  - "64bitelfv2/"
 tags:
   - specifications
   - systemsoftware
   - abi
-group: systemsoftware
+  - toolchain
+  - compiler
 date: 2021-03-15
 draft: false
 ---
@@ -13,7 +18,7 @@ draft: false
 The ABI (application binary interface) specification provides the definitions for the machine interface and
 inter-object interfaces for the little-endian POWER architecture.  
 
-This specification defines the OpenPOWER ELF v2 ABI which is derived from and represents the first major update to the Power ABI
+This specification defines the OpenPOWER ELF ABI which is derived from and represents the first major update to the Power ABI
 since the original release of the IBM® RS/6000® ABI.
 It was developed to make extensive use of new functions available in OpenPOWER-compliant processors.
 It expects an OpenPOWER-compliant processor to implement at least Power ISA v2.07B with all OpenPOWER Architecture instruction categories
@@ -22,7 +27,7 @@ as well as OpenPOWER-defined implementation characteristics for some implementat
 The Executable and Linking Format (ELF) defines a linking interface for executables and shared objects in two parts :
 the first part is the generic System V ABI, the second part is a processor-specific supplement.
 This document, the OpenPOWER ABI for Linux Supplement for the Power Architecture 64-bit ELF V2 ABI,
-is the OpenPOWER-compliant processor-specific supplement for use with ELF V2 on 64-bit IBM Power Architecture® systems.
+is the OpenPOWER-compliant processor-specific supplement for use with ELF on 64-bit IBM Power Architecture® systems.
 This is not a complete System V ABI supplement because it does not define any library interfaces.
 This document establishes both big-endian and little-endian application binary interfaces.
 OpenPOWER-compliant processors in the 64-bit Power Architecture can execute in either big-endian or little-endian mode.

content/specifications/advancedacceleratoradapter.md

@@ -0,0 +1,35 @@
+---
+title: Advanced Accelerator Adapter Electro-Mechanical Specification
+group: accelerator
+publicreview: false
+tags:
+  - specification
+  - accelerator
+  - power9
+  - 25gbps
+  - 25gio
+  - capi30
+  - opencapi
+date: 2018-01-17
+draft: false
+---
+
+The Advanced Accelerator Adapter Electro-Mechanical Specification defines an electro-mechanical specification for
+advanced accelerator adapters within the OpenPOWER eco-system supported by IBM® POWER9™.
+POWER9 modules present a 25Gbps interface organized into groups of 8 bit-lanes.
+Innovation within the community is encouraged for systems that support accelerated computing and
+the accelerator adapters needed to make heterogeneous / accelerated computing solutions available to the market.  
+
+This specification defines two accelerator approaches.
+The first approach is a mezzanine card attached to the system planar via two connectors.
+This approach is defined in Part I: Mezzanine Adapter Card.  
+
+The second approach is via cable and is defined in Cabled Interface Extension.
+While the accelerator card form factor is not defined in this specification Part II : Cabled Interface Extension assumes a PCIe® card for illustration.  
+
+The electrical characteristics of the 25Gbps channel are defined in Part III: 25 Gbit/sec Electrical Channel.  
+
+This document is a Standard Track, Workgroup Specification work product owned by the 25G IO Interoperability Workgroup and
+handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.
+It was created using the Document Development Guide version 1.1.0.
+Comments, questions, etc. can be submitted to the public mailing list for this document at <25giomode-p9_25gbps_phy@mailinglist.openpowerfoundation.org>.

content/specifications/caia.md

@@ -0,0 +1,22 @@
+---
+title: Coherent Accelerator Interface Architecture
+group: hardwarearchitecture
+reviewdraft: false
+aliases:
+  - "coherentacceleratorinterfacearchitecture/"
+  - "caia1/"
+  - "caia2/"
+tags:
+  - specification
+  - caia
+  - capi
+  - power8
+  - power9
+date: 2016-03-15
+draft: false
+---
+
+This document defines the Coherent Accelerator Interface Architecture (CAIA) for the IBM® POWER® systems.
+The information contained in this document allows various CAIA-compliant accelerator implementations
+to meet the needs of a wide variety of systems and applications.
+Compatibility with the CAIA allows applications and system software to migrate from one implementation to another with minor changes.

content/specifications/fsi.md

@@ -0,0 +1,28 @@
+---
+title: Field Replaceable Unit Service Interface Specification
+group: hardwarearchitecture
+publicreview: false
+aliases:
+  - "openfsi/"
+  - "openfieldserviceinterface/"
+  - "fieldserviceinterface/"
+tags:
+  - specification
+  - fsi
+  - fru
+  - openfsi
+  - hardware
+date: 2016-10-13
+draft: false
+---
+
+This document describes a Field Replaceable Unit (FRU) Support Interface (FSI) suited
+to service all chips in a computer system via a common serial interface.
+Key features are ease of use, easy scalability, robustness, and support for virtualization and
+the tunneling of interrupts and DMA control signals across the interface.
+FSI is superior to similar industry standard interfaces in these and many other features including speed, distance, data protection, and address range.  
+
+FSI is a point to point two wire interface operating in half duplex mode,
+which is capable of supporting distances of up to 4 meters at up to 166 MHz bus frequency.
+All operations are fully CRC checked to allow error recovery.
+With its versatile architecture, the FSI is suited for a wide range of applications from service access to in-system test.  

content/specifications/ioda.md

@@ -0,0 +1,20 @@
+---
+title: IO Design Architecture (IODA) Specification
+group: hardwarearchitecture
+publicreview: false
+tsth: false
+tags:
+  - specification
+  - hardware
+  - reference
+  - pcie
+  - phb
+  - ioda
+  - power8
+  - power9
+date: 2016-03-15
+draft: false
+---
+
+The purpose of the OpenPOWER I/O Design Architecture (IODA) specification is to describe the chip architecture for key aspects of
+PCIe® based host bridge (PHB) designs for IBM® POWER systems.

content/specifications/isa.md

@@ -0,0 +1,33 @@
+---
+title: "Instruction Set Architecture"
+group: isa
+publicreview: false
+aliases:
+  - "powerisa/"
+  - "power31/"
+  - "powerisa31/"
+  - "power30/"
+  - "powerisa30/"
+  - "power207/"
+  - "powerisa207/"
+tags:
+  - instructionsetarchitecture
+  - isa
+  - powerisa
+  - cores
+  - power8
+  - power9
+  - power10
+date: 2021-08-30
+draft: false
+---
+
+The Power Instruction Set Architecture (ISA) Version is a specification that describes the architecture used for the IBM POWER processor.  
+It defines the instructions the processors execute.  
+It is comprised of three books and a set of appendices.  
+- Book I
+  - Power ISA User Instruction Set Architecture, covers the base instruction set and related facilities available to the application programmer.
+- Book II
+  - Power ISA Virtual Environment Architecture, defines the storage model and related instructions and facilities available to the application programmer.
+- Book III
+  - Power ISA Operating Environment Architecture, defines the supervisor instructions and related facilities.

content/specifications/linuxonpower.md

@@ -0,0 +1,17 @@
+---
+
+
+---
+
+The purpose of this document is to detail a stable platform architecture to be used by platforms defined by the POWER ISA Specification.  
+
+This architecture specification provides a comprehensive computer system platform-to-software interface definition,
+combined with minimum system requirements, that enables the development of and software porting to
+a range of compatible industry-standard computer systems from workstations through servers.
+These systems are based on the requirements defined in the Power Instruction Set Architecture (ISA).
+The definition supports the development of both uni-processor and multi-processor system implementations.  
+
+This document is a Standard Track, Work Group Specification work product owned by the System Software Workgroup and
+handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.
+It was created using the Master Template Guide version 1.0.0.
+Comments, questions, etc. can be submitted to the public mailing list for this document at syssw-linux_architecture_ref@mailinglist.openpowerfoundation.org.

content/specifications/memorybus.md

@@ -0,0 +1,27 @@
+---
+title: Memory Bus Specification
+group: memory
+publicreview: false
+alias:
+  - "openpowermemorybus/"
+  - "opmb/"
+tags:
+  - hardware
+  - memory
+  - memorybus
+date: 2021-05-26
+draft: false
+---
+
+The OpenPOWER Memory Bus (OPMB) Specification defines the OpenPOWER Memory Bus Architecture.
+The architecture and specification are used to develop Memory Function Units (MFU) and
+to integration of those MFUs into the OpenPOWER system structure.
+An MFU is a logic block developed by a member of the OpenPOWER eco-system to attach special purpose memory technology and
+function processing for data stored in the memory technology.
+An example of MFU might be a database function accelerator which attaches dense flash memory technology.
+
+This figure illustrates the concept.
+{{< image src="specifications/opmb-mbd.png" width="750" height="750" >}}
+
+Comments regarding the specification content and suggestions for updates may be submitted to the following mailing list:
+<memwg-opmb@mailinglist.openpowerfoundation.org>

content/specifications/ocpa.md

@@ -0,0 +1,16 @@
+---
+title: OpenCAPI POWER Platform Architecture Guide
+group: systemsoftware
+publicreview: false
+tags:
+  - opencapi
+  - firmware
+  - operatingsystem
+date: 2019-01-18
+draft: false
+---
+
+The OpenCAPI POWER Platform Architecture (OCPA) defines an accelerator interface structure for
+coherently attaching accelerators to the IBM Power Systems™ using an OpenCAPI Physical Link.
+The intent is to allow implementation of a wide range of accelerators to optimally address many different market segments.
+The target audience is firmware and operating system developers.

content/specifications/powerisa207.md

@@ -2,7 +2,7 @@
 title: "POWER Instruction Set Architecture 2.07"
 publicreview: false
 date: 2022-01-01
-draft: false
+draft: true
 ---
 
 The Power Instruction Set Architecture (ISA) Version 2.07B is a specification that describes the architecture used

content/specifications/powerisa30.md

@@ -2,7 +2,7 @@
 title: "POWER Instruction Set Architecture 3.0"
 publicreview: false
 date: 2021-08-30
-draft: false
+draft: true
 ---
 
 The Power Instruction Set Architecture (ISA) Version 3.0 is a specification that describes the architecture used for the IBM POWER9 processor.  

content/specifications/powerisa31.md

@@ -1,7 +1,7 @@
 ---
 title: "POWER Instruction Set Architecture 3.1"
 date: 2021-08-30
-draft: false
+draft: true
 ---
 
 The Power Instruction Set Architecture (ISA) Version 3.1 is a specification that describes the architecture used for the IBM POWER10 processor.  

content/specifications/pslafuinterface.md

@@ -0,0 +1,40 @@
+---
+title: PSL / AFU Interface Specification
+group: accelerator
+publicreview: false
+tags:
+  - powerservicelayer
+  - psl
+  - acceleratorfunctionalunit
+  - afu
+  - accelerator
+  - capi1
+  - capi2
+  - pcie4
+  - power8
+  - power9
+date: 2016-03-15
+draft: false
+---
+
+A CAPI based accelerator interfaces to the POWER system through a logic unit called the Power Service Layer (PSL).
+The Accelerator Function Unit (AFU) contains the logic that implements the unique acceleration function.  
+
+The POWER Service Layer to Accelerator Functional Unit (PSL / AFU) interface communicates to the acceleration logic running on the FPGA.
+Through this interface, the PSL offers services to the AFU.
+The services offered are cache-line oriented and allow the AFU to make buffering versus throughput trade-offs.  
+
+The interface to the AFU is composed of six independent interfaces :
+- AFU Command Interface is the interface through which the AFU sends service requests to the PSL.
+- AFU Buffer Interface is the interface through which the PSL moves data to and from the AFU.
+- PSL Response Interface is the interface through which the PSL reports status about service requests.
+- AFU MMIO Interface is the interface through which software reads and writes can access registers within the AFU.
+- AFU Control Interface allows the PSL job management functions to control the state of the AFU.
+- AFU DMA Interface allows the AFU to send native PCIe Writes and Reads and to receive Read Completion data.
+
+Together these interfaces allow software to control the AFU state and allow the AFU to access data in the system.  
+
+This document is a Standard Track, Work Group Specification work product owned by the Accelerator Workgroup and
+handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.
+It was created using the Master Template Guide version 1.0.0.
+Comments, questions, etc. can be submitted to the public mailing list for this document at <aclwg-afu_psl@mailinglist.openpowerfoundation.org>.

content/specifications/pviprcompliance.md

@@ -1,27 +0,0 @@
----
-title: "PVIPR Compliance Specification"
-tags:
-  - pvipr
-date: 2021-03-22
-draft: false
----
-
-This document provides requirements for a compiler to demonstrate compliance with the Power Vector Intrinsics Programming Reference, version 1.0.  
-
-This document is a Standard Track, Workgroup Specification work product owned by the Compliance Workgroup
-and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.
-Comments, questions, etc. can be submitted to the public mailing list for the parent specification at
-<openpower-pvipr-thts@mailinglist.openpowerfoundation.org>.  
-
-The input to this specification is the following specification which describes the vector intrinsics expected to be provided
-by compilers targeting PowerISA 2.07 and 3.0B or later, as implemented on POWER8 and POWER9 systems.  
-
-Power Vector Intrinsics Programming Reference (PVIPR) which is published on the resource catalog:
-https://openpowerfoundation.org/?resource_lib=power-vector-intrinsic-programming-reference
-
-The PVIPR document is organized into the following chapters:
-1. Introduction to Vector Programming on Power
-2. The Power Bi-Endian Vector Programming Model
-3. Vector Programming Techniques
-4. Vector Intrinsic Reference
-5. Instruction/Intrinsic Cross-Reference

content/specifications/vectorintrinsicportingguide.md

@@ -0,0 +1,22 @@
+---
+title: Vector Intrinsics Porting Guide
+group: systemsoftware
+publicreview: false
+tags:
+  - software
+  - vectorintrinsics
+  - vector
+  - vmx
+  - vsx
+  - altivec
+  - optimization
+date: 2018-01-08
+draft:
+---
+
+The goal of this project is to provide functional equivalents of the Intel MMX, SSE, and AVX intrinsic functions,
+that are commonly used in Linux applications, and make them (or equivalents) available for the PowerPC64LE platform.  
+
+This document is a Work Group Note work product owned by the System Software Workgroup and
+handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.
+Comments, questions, etc. can be submitted to the public mailing list for this document at <syssw-programming-guides@mailinglist.openpowerfoundation.org>.

content/specifications/vectorintrinsicprogrammingreference.md

@@ -1,7 +1,15 @@
 ---
-title: "Power Vector Intrinsics Programming Reference Specification"
+title: "Vector Intrinsics Programming Reference Specification"
+group: systemsoftware
+reviewdraft: false
+aliases:
+  - "powervectorintrinsicsprogrammingreference/"
+  - "pvipr/"
 tags:
+  - specification
+  - software
   - pvipr
+  - vectorintrinsics
 date: 2021-03-24
 draft: false
 ---

data/specifications/64bitelfabi.yaml

@@ -1,23 +1,23 @@
 versions:
-  - number: "1.0"
+  - number: "2.1.0"
     date: "2014-07-21"
     description: "Initial release."
     download: "https://files.openpower.foundation/s/XqEfC9EKNWzgneb"
-  - number: "1.1"
+  - number: "2.1.1"
     date: "2015-07-16"
     description: "Incorporate errata."
     download: "https://files.openpower.foundation/s/aybzqzEpN5AGfXG"
-  - number: "1.2"
+  - number: "2.1.2"
     date: "2016-06-13"
     description: "POWER8 errata"
-  - number: "1.3"
+  - number: "2.1.3"
     date: "2016-06-13"
     description: "POWER9 errata"
-  - number: "1.4"
+  - number: "2.1.4"
     date: "2017-01-13"
     description: "Conversion from FrameMaker to DocBook, minor corrections."
     download: "https://files.openpower.foundation/s/aqwWeS3qmoaDyos"
-  - number: "1.5"
+  - number: "2.1.5"
     date: "2020-12-01"
     description: "POWER10 support"
     download: "https://files.openpower.foundation/s/cfA2oFPXbbZwEBK"

data/specifications/advancedacceleratoradapter.yaml

@@ -0,0 +1,32 @@
+versions:
+  - number: 0.1
+    date: 2017-03-13
+    description: Creation of electo-mechanical consolidated specification
+  - number: 0.2
+    date: 2017-04-27
+    description: Review updates from Dan Dreps & Jeff Brown
+  - number: 0.3
+    date: 2017-06-27
+    description:  Added part on cable extender version
+  - number: 0.4
+    date: 2017-07-20
+    description: Updates from workgroup review
+  - number: 0.5
+    date: 2017-08-01
+    description: Updates from workgroup review
+  - number: 0.6
+    date: 2017-08-02
+    description: Updates to table 5.1 about ILD, ILDB, and "moving average smoothing"
+  - number: 0.7
+    date: 2017-08-08
+    description: Added section on Conformance, additional minor edits, removed Section 6.2 Mezzanine Net Model
+  - number: 0.8
+    date: 2017-08-17
+    description: public review draft
+  - number: 0.9
+    date: 2017-10-19
+    description: Modified mezzanine card section 2.1,2., and 2.3 to reflect a reference design and connector PN
+  - number: 1.0
+    date: 2017-11-08
+    description: workgroup specification
+    download: https://files.openpower.foundation/s/xSQPe6ypoakKQdq

data/specifications/caia.yaml

@@ -0,0 +1,27 @@
+versions:
+  - number: 0.1
+    date: 2014-12-09
+    description: intital release
+  - number: 0.2
+    date: 2015-08-15
+    description: changes from wg review
+  - number: 0.3
+    date: 2015-10-07
+    description: conversion to docbook from framemaker
+  - number: 0.9
+    date: 2015-10-26
+    description: public review draft
+  - number: 1.0
+    date: 2016-01-13
+    description: workgroup specification
+    download: https://files.openpower.foundation/s/kpYmfrSREq8wFXR
+  - number: 1.1
+    date: 2017-06-15
+    description: conversion from framemaker
+  - number: 1.2
+    date: 2018-07-02
+    description: internal review
+  - number: 1.9
+    date: 2020-03-23
+    description: public review
+    download: https://files.openpower.foundation/s/EMFd9nPCx8N8tPr

data/specifications/fsi.yaml

@@ -0,0 +1,17 @@
+versions:
+  - number: 0.1
+    date: 2015-09-01
+    description: creation based on IBM FSI spec contib
+  - number: 0.2
+    date: 2015-09-02
+    description: comment correction as per review
+  - number: 0.3
+    date: 2016-05-05
+    description: public review draft
+  - number: 0.4
+    date: 2016-08-16
+    description: correction chapter 1 added definition & chapter 4 typo
+  - number: 1.0.0
+    date: 2016-12-12
+    description: workgroup specification
+    download: 

data/specifications/ioda.yaml

@@ -0,0 +1,15 @@
+versions:
+  - number: 2.0.7
+    date: 2015-04-23
+    description: Creation based on IBM IODA2 Specification
+  - number: 2.0.8
+    date: 2015-08-21
+    description:  Clean-up of typo/conversion errors
+  - number: 2.0.9
+    date: 2015-10-01
+    description: Clean-up of typo/conversion errors
+  - number: 2.1.0
+    date: 2016-01-13
+    description: Clean-up legal wording and added foundation info appendix
+    download: https://files.openpower.foundation/s/BcARpp9gFMXwqrL
+#  - number: 3.0

data/specifications/linuxonpower.yaml

@@ -0,0 +1,29 @@
+versions:
+  - number: "1.1"
+    date: 2016-03-24
+    download: https://files.openpower.foundation/s/LmdoZDGkJqp679y
+  - number: "2.1"
+    date: 2016-05-04
+    description: conversion from IBM document
+  - number: "2.2"
+    date: 2016-10-11
+    description: include latest PAPR ACR 2.8
+  - number: "2.3"
+    date: 2018-07-30
+    description: preparation for wg review
+  - number: "2.4"
+    date: 2019-01-08
+    description: update from wg review
+  - number: "2.5"
+    date: 2020-04-06
+    description: include latest PARP ACR 2.9
+  - number: "2.6"
+    date: 2020-04-20
+    description: update formatting
+  - number: "2.7"
+    date: 2020-06-11
+    description: public review
+  - number: "2.9"
+    date: 2020-08-12
+    description: workgroup note
+    download: https://files.openpower.foundation/s/ZmtZyCGiJ2oJHim

data/specifications/memorybus.yaml

@@ -0,0 +1,27 @@
+versions:
+  - number: 0.40
+    date: 2017-10-05
+  - number: 0.41
+    date: 2020-05-21
+  - number: 0.42
+    date: 2020-06-04
+  - number: 0.43
+    date: 2020-07-30
+  - number: 0.50
+    date: 2020-08-30
+  - number: 0.51
+    date: 2020-08-30
+  - number: 0.52
+    date: 2020-09-10
+  - number: 0.53
+    date: 2020-09-10
+  - number: 0.90
+    date: 2020-10-08
+  - number: 0.91
+    date: 2020-10-11
+  - number: 0.92
+    date: 2021-02-01
+  - number: 0.93
+    date: 2021-04-08
+  - number: 1.93
+    date: 2021-04-26

data/specifications/ocpa.yaml

@@ -0,0 +1,17 @@
+versions:
+  - number: "2.6"
+    date: 2018-01-15
+    description: conversion from framemaker
+  - number: "2.7"
+    date: 2018-04-09
+    description: minor editing for first draft
+  - number: "2.8"
+    date: 2018-07-02
+    description: more editing
+  - number: "2.9"
+    date: 2018-07-26
+    description: public review draft
+  - number: "3.0"
+    date: 2019-01-18
+    description: workgroup note
+    download: https://files.openpower.foundation/s/DwnMymtj9BRQQ2y

data/specifications/powerisa.yaml

@@ -0,0 +1,21 @@
+versions:
+  - number: "2.07"
+    date: "2013-05-03"
+    download: ""
+    description: "Initial release."
+  - number: "2.07b"
+    date: "2017-03-28"
+    description: "Update specification."
+    download: "https://ibm.ent.box.com/s/jd5w15gz301s5b5dt375mshpq9c3lh4u"
+  - number: "3.0b"
+    date: "2017-03-29"
+    download: "https://ibm.ent.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv"
+    description: "Initial release."
+  - number: "3.0c"
+    date: "2020-05-01"
+    download: "https://files.openpower.foundation/s/XXFoRATEzSFtdG8"
+    description: "Incorporate errata."
+  - number: "3.1"
+    date: "2020-05-02"
+    download: "https://files.openpower.foundation/s/bo728kgiWfgMHAr"
+    description: "Initial release."

data/specifications/pslafuinterface.yaml

@@ -0,0 +1,25 @@
+versions:
+  - number: 0.1.0
+    date: 2015-04-14
+    description: IBM CAPI documentation conversion
+  - number: 1.0.0
+    date: 2015-10-20
+    description: workgroup specification
+    download: https://files.openpower.foundation/s/drQqcZEcBfLEYcf
+  - number: 1.0.1
+    date: 2016-09-13
+    description: clarification data alignment, parity, partial cacheline
+    download: https://files.openpower.foundation/s/yLreYMysGbZiYiT
+  - number: 1.1
+    date: 2016-05-18
+    description: conversion from IBM internal documentation
+  - number: 1.2
+    date: 2016-08-02
+    description: updates for v2
+  - number: 1.3
+    description: Fixes to CAS Operand Alignment on Buffer Interface
+    date: 2017-01-16
+  - number: 2.0
+    date: 2017-07-20
+    description: workgroup specification
+    download: https://files.openpower.foundation/s/SxLFti5e4a5gBTb

data/specifications/vectorintrinsicportingguide.yaml

@@ -0,0 +1,14 @@
+versions:
+  - number: "0.1"
+    date: 2017-07-26
+    description: initial draft from Steve Munroe
+  - number: "0.2"
+    date: 2017-09-14
+    description: Miscellaneous correction for spelling, grammar and punctuation
+  - number: "0.3"
+    date: 2017-10-30
+    description: Updates to describe issues associated with larger vector sizes and proposed solutions
+  - number: "1.0"
+    date: 2018-03-14
+    description: Minor updates for Published version
+    download: https://files.openpower.foundation/s/7FSEcPrjPH3xmp3

data/specifications/vectorintrinsicprogrammingreference.yaml

@@ -0,0 +1,5 @@
+versions:
+  - number: 1.0.0
+    date: 2020-08-11
+    description:
+    download: https://files.openpower.foundation/s/9nRDmJgfjM8MpR7

themes/openpowerfoundation/layouts/specifications/single.html

@@ -2,6 +2,7 @@
 {{ partial "navbar.html" . }}
 {{ $filename := .File.BaseFileName }}
 {{ $datafile := index $.Site.Data.specifications $filename }}
+{{ $compliancefile := printf "%s/%s" "compliance" $filename }}
 <main id="main" class="specifications-single">
 <section id="page" class="section-bg">
 <div class="row">
@@ -18,22 +19,20 @@
 			<span class="changetime-wrapper"><span class="changetime">{{ .date }}</span></span>
 		{{ end }}
 	{{ end }}
-	{{ if .Param "group" }}
-		{{ $group := printf "%s/%s" "groups" (.Param "group") }}
-		{{ with $.Site.GetPage $group }}
-			Owned by : {{ .Title }}
-		{{ end }}
-	{{ end }}
 	</div>
 	<div class="col-lg-3"></div>
 </div>
 {{ if .Param "publicreview" }}
-<div class="row">
+	{{ $reviewenddate := .Date.AddDate 0 0 30 }}
-	<div class="col-lg-3"></div>
+	{{ if lt now $reviewenddate }}
-	<div class="col-lg-6">
+		<div class="row">
-	</div>
+			<div class="col-lg-3"></div>
-	<div class="col-lg-3"></div>
+			<div class="col-lg-6">
-</div>
+				<b>The Public Review for this document completes at close-of-business on {{ $reviewenddate.Format "Monday 2 January 2006" }}.</b>
+			</div>
+			<div class="col-lg-3"></div>
+		</div>
+	{{ end }}
 {{ end }}
 <div class="row">
 	<div class="col-lg-3"></div>
@@ -41,6 +40,15 @@
 		<p>{{ .Content }}</p>
 	</div>
 	<div class="col-lg-3">
+	{{ if .Param "group" }}
+		{{ $group := printf "%s/%s" "groups" (.Param "group") }}
+		{{ with $.Site.GetPage $group }}
+			Owned by : <a href="{{ .Permalink }}">{{ .Title }}</a><br>
+		{{ end }}
+	{{ end }}
+	{{ with $.Site.GetPage $compliancefile }}
+		Compliance : <a href="{{ .Permalink }}">Test Suite &amp; Harness</a>
+	{{ end }}
 	{{ if $datafile.versions }}
 		<ul class="changelogtimeline">
 		{{ range sort $datafile.versions "date" "desc" }}
@@ -62,17 +70,38 @@
 	</div>
 </div>
 {{ if .Params.tags }}
+{{ $tags := .Params.tags }}
 <div class="row">
 	<div class="col-lg-3"></div>
 	<div class="col-lg-6 text-center">
-	{{ range .Params.tags }}
+		{{ if not (eq (len $.Site.Taxonomies.tags) 0) }}
-		{{ . }}
+			{{ $fontUnit := "rem" }}
-	{{ end }}
+			{{ $largestFontSize := 3.5 }}
+			{{ $smallestFontSize := 0.5 }}
+			{{ $fontSpread := sub $largestFontSize $smallestFontSize }}
+			{{ $max := add (len (index $.Site.Taxonomies.tags.ByCount 0).Pages) 1 }}
+			{{ $min := len (index $.Site.Taxonomies.tags.ByCount.Reverse 0).Pages }}
+			{{ $spread := sub $max $min }}
+			{{ $fontStep := div $fontSpread $spread }}
+			{{ range $name, $taxonomy := $.Site.Taxonomies.tags }}
+				{{ $currentTagCount := len $taxonomy.Pages }}
+				{{ $currentFontSize := (add $smallestFontSize (mul (sub $currentTagCount $min) $fontStep) ) }}
+				{{ $count := len $taxonomy.Pages }}
+				{{ $weigth := div (sub (math.Log $count) (math.Log $min)) (sub (math.Log $max) (math.Log $min)) }}
+				{{ $currentFontSize := (add $smallestFontSize (mul (sub $largestFontSize $smallestFontSize) $weigth) ) }}
+				{{ range $tags }}
+					{{ if eq $name . }}
+						&nbsp;
+						<span style="font-size: {{ $currentFontSize }}{{ $fontUnit }}">{{ $name }}</span>
+						&nbsp;
+				{{ end }}
+			{{ end }}
+		{{ end }}
 	</div>
 	<div class="col-lg-3"></div>
+{{ end }}
 </div>
 {{ end }}
 </section>
 </main>
-
 {{ partial "footer.html" . }}