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---
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title: "Introducing IBM® POWER10 Functional Simulator"
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date: "2020-10-02"
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categories:
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- "blogs"
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tags:
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- "openpower"
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- "ibm"
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- "featured"
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- "openpower-summit"
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- "openpower-foundation"
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- "hardware"
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- "linux"
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- "ibm-power"
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- "power10"
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- "functional-simulator"
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---
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By [Brad Thomasson](https://www.linkedin.com/in/bradford-thomasson-9b89044/), Cognitive Software Engineer, IBM
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After announcing the newest [IBM POWER10 processor at the Hot Chips 2020 in August](https://newsroom.ibm.com/2020-08-17-IBM-Reveals-Next-Generation-IBM-POWER10-Processor), our IBM Cognitive Systems Simulation team is now proud to present the [IBM POWER10 Functional Simulator](https://www14.software.ibm.com/webapp/set2/sas/f/pwrfs/pwr10/home.html).
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This publicly available simulation environment is designed to educate developers, facilitate porting of existing Linux applications to the POWER10 architecture, and enable new ones to be created.
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\[caption id="attachment\_7638" align="aligncenter" width="1024"\] _A close-up of the first commercialized 7nm processor, the IBM POWER10. Photo credit: Connie Zhou for IBM_\[/caption\]
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This simulator provides enough POWER10 processor complex functionality to allow the entire software stack to execute. This includes loading, booting and running a little endian Linux environment.
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Note that while the IBM POWER10 Functional Simulator serves as a full instruction set simulator for the POWER10 processor, it may not model all aspects of the IBM Power Systems POWER10 hardware and thus may not exactly reflect the behavior of the POWER10 hardware.
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Features/support available in the simulator include:
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- POWER10 hardware reference model
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- Full instruction set simulator for Power ISA as implemented in POWER10
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- Models complex SMP effects
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- Architectural modeled areas:
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- Functional behavior of all units (Load/Store, FXU, FPU, DFP, VMX, VSX, etc.)
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- Exceptions and Interrupt handling
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- Address translation, both Paravirtualized HPT and two level Radix Tree
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- Memory and basic translation cache modeling (SLBs, TLBs, ERATs)
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- Instruction Prefix Support
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- VSX Matrix-Multiply Assist (MMA) Instructions for AI
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- Reduced-Precision instructions to accelerate matrix multiplication
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- Copy-Paste Facility
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- New AIL/HAIL programmability feature for Linux/Hybrid cloud
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- Linux and Hypervisor development and debug platform
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- TCL command-line interface provides:
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- Custom user initialization scripts
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- Processor state control for debug: Step, Run, Cycle run-to, Stop, etc.
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- Register and Memory R/W interaction
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Our team is very open to feedback and questions. For all technical inquiries and suggestions, please reach out to our Cognitive Systems Simulation team through the [Customer Connect Support Channel](https://login.ibm.com/oidc/sps/auth?Target=https%3A%2F%2Flogin.ibm.com%2Foidc%2Fendpoint%2Fdefault%2Fauthorize%3FqsId%3D2d9cf726-59b4-4d0e-b4f0-f04c029876d7%26client_id%3DMzUxMDEwNzQtZTU2Ny00&client_id=MzUxMDEwNzQtZTU2Ny00) or consider joining the [OpenPOWER Foundation Slack workspace](https://join.slack.com/t/openpowerfoundation/shared_invite/zt-9l4fabj6-C55eMvBqAPTbzlDS1b7bzQ).
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