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# a2o tb-node
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SIM_BUILD ?= build_node
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SIM ?= icarus
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# icarus
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VERILOG_ROOT = ../../verilog
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#NODE = a2node
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# a2node_verilator has some test, etc. inputs tied in rtl
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# also has l/s credits set to 1 in defines
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NODE = $(VERILOG_ROOT)/a2node_verilator
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COMPILE_ARGS = -I$(NODE) -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work -y$(NODE)
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# other options
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# rtl
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TOPLEVEL_LANG = verilog
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# top-level to enable trace, etc.
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VERILOG_SOURCES = ./cocotb_icarus_node.v
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TOPLEVEL = cocotb_icarus_node
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# python test
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MODULE = tb_node
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TESTCASE = tb_node
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# cocotb make rules
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include $(shell cocotb-config --makefiles)/Makefile.sim
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build: clean sim fst
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run: sim fst
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vcd: sim
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fst:
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vcd2fst a2onode.vcd a2onode.fst
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rm a2onode.vcd
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