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Makefile

2 years ago
# a2o tb-node
SIM_BUILD ?= build_node
SIM ?= icarus
# icarus
VERILOG_ROOT = ../../verilog
2 years ago
#NODE = a2node
# a2node_verilator has some test, etc. inputs tied in rtl
# also has l/s credits set to 1 in defines
2 years ago
NODE = $(VERILOG_ROOT)/a2node_verilator
COMPILE_ARGS = -I$(NODE) -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work -y$(NODE)
2 years ago
# other options
# rtl
TOPLEVEL_LANG = verilog
# top-level to enable trace, etc.
VERILOG_SOURCES = ./cocotb_icarus_node.v
TOPLEVEL = cocotb_icarus_node
# python test
MODULE = tb_node
TESTCASE = tb_node
2 years ago
# cocotb make rules
include $(shell cocotb-config --makefiles)/Makefile.sim
build: clean sim fst
run: sim fst
vcd: sim
fst:
vcd2fst a2onode.vcd a2onode.fst
rm a2onode.vcd