pd
openpowerwtf 2 years ago
parent 4177984080
commit 3893e0253d

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# A2O # A2O


# Current Status

* for now, /rel is the original and /dev has updates:

* compiles with verilator, iverilog, yosys
* runs original simple boot code up to test invocation with cocotb (A2L2 interface partially implemented in Python)

## To Do

* continue with cocotb testing
* add A2Node bridge to WB, and Litex wrapper
* experiment with parameters to create smaller version(s) for dOpenLane

# Original Release

## The Project ## The Project
This is the release of the A2O POWER processor core RTL and associated FPGA implementation (using ADM-PCIE-9V3 FPGA). This is the release of the A2O POWER processor core RTL and associated FPGA implementation (using ADM-PCIE-9V3 FPGA).



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dev/.gitignore vendored

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*.pdf

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# Testing RTL with new environments

##

* RTL

* updated source to remove a bunch of Verilator warnings
* updated source for compatibility with Icaraus -g2012
* changed the GPR/FPR macro to remove need for clk4x on FPGA; was ugly and not working with either simulator

* Verilator

* can IFETCH some ops in ST and SMT2 mode
* can't get cocotb to build with Verilator (very long compile times)

* Icarus (w/cocotb)

* executing boot code until test call with python A2L2 interface

* Yosys

* finishes compile


## Next To Do

* create A2L2 cpp model that can be used by Verilator and cocotb (Cython wrapper)
* create simple A2L2-WB RTL for easily connecting to Litex, etc.
* create Litex core wrapper
* OpenLane experiments with blackbox arrays and yosys/abc/sta
* create FPGA version of GPR/FPR (4R4W) using (4)4R1W banks and valid table
* parse vcd/fst and serve browser code for custom trace screens (handle spec/arch mapped facilities, arrays, etc.)

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# verilator
**/obj_dir*/
# cooc/icarus
coco_icarus
**/sim_build*/
# gtkwave
*.vcd
*.fst
# python
**/__pycache__/
*.py[cod]

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# A2L2 Interface

import cocotb
from cocotb.triggers import Timer, RisingEdge
from cocotb.binary import BinaryValue
from cocotb.handle import Force
from cocotb.handle import Release

from dotmap import DotMap
import itertools

# ------------------------------------------------------------------------------------------------
# Classes

'''
Data return timings from spec:

* Reload Data Coming
Indicates that reload data is coming in three cycles. This signal is required for L2 designs that return data in consecutive cycles, but can be
tied to a logic 0 for designs that return data in every other cycle. For L2 designs that return data in consecutive cycles, this signal should be
asserted three cycles ahead of the first of two paired data beats. If more than two data beats will be presented consecutively, this signal should be
asserted once for the first set of two (paired) data beats and once for the second set of two (paired) data beats. Each assertion
should be three cycles ahead of the first beat of the paired set of data beats. This signal allows the A2 core to insert an issue bubble for the second
reload data beat to avoid flushing the processor pipe. This signal is not required to be asserted as described above for DITC return data.
For non-cacheable (I=1) reloads of one or two beats, this signal should be asserted three cycles ahead of the first (and possibly only) data beat transfer.

* Reload Data Valid
Indicates that reload data is coming in two cycles. This signal qualifies the other reload interface signals sent in this cycle: reld_ditc, reld_core_tag, reld_crit_qw, and reld_qw.
If reld_data_vld is not active, then the qualified signals should be ignored.

* Reload Direct Inter-Thread Communication
Indicates that the reload data is associated with a DITC transfer instead of a standard load-ttype reload. This signal is qualified by reld_data_vld and determines the
interpretation of the reld_core_tag bus. DITC reload data transfers are always 64-Byte transfers that follow the same consecutive cycle or every-other-cycle behavior
as standard load-ttype reloads for the attached L2.

**i believe this means ditc can use either 1of2/2of2 or 1of2/-/-/2of2 pattern, but never requires data_coming (probs because pipe considerations not important for ditc)**

======
Cycles:

* d-3 (reld_data_coming)
Loads:
1. I=1: assert 3 cycs ahead of first transfer (two transfers only if 32B allowed)
2. I=0 data every other cycle: not asserted
3. I=0 data consecutive cycles: assert 3 cycs ahead of the 1of2 paired beats; if more than 2 beats are consecutive, assert 3 cycs ahead of each paired beat
DITC:
1. assertion not required **(or used by core?)**

* d-2 (reld_data_vld and qualified signals)
Loads:
1. assert 2 cycs ahead of data
DITC:
1. assert 2 cycs ahead of data and also assert reld_ditc

Cacheable Return Modes:
1. no back-to-back: coming=0
2. all back-to-back: coming=1/0/1
3. interleaved back-to-back: coming=1/0/0/0/1
4. mixed: legal cases for subxfers (?) **i think the 'mixed' aren't valid - xucr0[52] selects b2b mode**
* 1 1 1 1 (no b2b)
* 1 2 1 (mixed)
* 1 1 2 (mixed)
* 2 1 1 (mixed)
* 2 2 (full b2b)
5. between subxfers a delay or other transaction can be inserted

?? xucr0[52] definition selects b2b but also says crit first; i guess this means crit first is allowed, but not required?? a2l2 spec says it is not required to send crit first

'''
class A2L2Trans(DotMap):
'''A2L2 Transaction'''
nextID = itertools.count()
def __init__(self, sim, tid, tt, tag=None, addr=None, length=0, wimg=0, cycD=None, be=None, data=None):
super().__init__()
self.sim = sim
self.id = next(A2L2Trans.nextID)
self.tid = tid
self.tt = tt
self.tag = tag
self.addr = addr
self.len = length
self.wimg = wimg
self.xfers = 1
self.xferNum = 0
self.xferCrit = 1
self.beatNum = 1
if cycD is not None:
self.cycC = cycD - 3
self.cycV = cycD - 2
self.cycD = cycD
self.be = f'{int(be, 16):032b}' if be is not None else None
self.data = data
self.done = False

self.ieq1 = wimg & 0x4 == 0x4

self.load = tt == 0x00 or tt == 0x08 or tt == 0x22 or tt == 0x09 or tt == 0x0B # IF, LD, DITC, LARX, LARX_HINT
self.store = tt == 0x20 or tt == 0x29 # ST, STCX

if self.load:
self.addr = self.addr & 0xFFFFFFF0
elif self.store:
self.addr = self.addr & 0xFFFFFFE0
if self.be == None or self.data == None:
raise Exception('A2L2Trans: store must have BE and data')
else:
self.len = 0
self.storeStart = None
for i in range(len(self.be)):
if self.be[i] == '1':
if self.storeStart is None:
self.storeStart = i
self.len += 1
elif self.storeStart is not None:
break
else:
raise Exception(f'A2L2Trans: unsupported ttype={tt}')

self.ditc = tt == 0x22

if self.ieq1:
if tt == 0x00 or tt == 0x08: # IF, LD
if len == 7:
self.xfers = 2
elif tt == 0x22: # DITC
self.xfers = 4
else:
if self.load:
self.xfers = 4
self.xferCrit = ((self.addr & 0x30) >> 4) + 1
self.addr = self.addr & 0xFFFFFFC0

def readXfer(self):
# read() returns this qw crit-first if cacheable!
w0 = self.sim.mem.read(self.addr)
w1 = self.sim.mem.read(self.addr+4)
w2 = self.sim.mem.read(self.addr+8)
w3 = self.sim.mem.read(self.addr+12)
beatNum = self.beatNum
if self.beatNum < self.xfers:
self.beatNum += 1
self.cycD += 1
self.addr += 16 #wtf this is wrong - going to need to schedule the pattern when the trans is created!!!!!!!!!!!!!!!!!!!!!!!!
return w0,w1,w2,w3,beatNum

def doStore(self):
addr = ((self.addr + self.storeStart) >> 2) << 2
dataStart = self.storeStart*2
if self.len == 1:
word = self.sim.mem.read(addr)
byte = self.addr & 0x3
if byte == 0:
mask = 0xFFFFFF00
elif byte == 1:
mask = 0xFFFF00FF
elif byte == 2:
mask = 0xFF00FFFF
else:
mask = 0x00FFFFFF
word = (word & mask) | (int(self.data[dataStart:dataStart+2], 16) << (byte*2))
self.sim.mem.write(addr, word)

elif self.len == 2:
word = self.sim.mem.read(addr)
hw = (self.addr & 0x2) >> 1
if hw == 0:
mask = 0xFFFF0000
else:
mask = 0x0000FFFF
word = (word & mask) | (int(self.data[dataStart:dataStart+4], 16) << (hw*4))
self.sim.mem.write(addr, word)

elif self.len == 4:
self.sim.mem.write(addr, int(self.data[dataStart:dataStart+8], 16))

elif self.len == 8:
self.sim.mem.write(addr, int(self.data[dataStart:dataStart+16], 16))
self.sim.mem.write(addr+4, int(self.data[dataStart+16:dataStart+32], 16))

elif self.len == 16:
self.sim.mem.write(addr, int(self.data[0:8], 16))
self.sim.mem.write(addr+4, int(self.data[8:16], 16))
self.sim.mem.write(addr+8, int(self.data[16:24], 16))
self.sim.mem.write(addr+12, int(self.data[24:32], 16))

elif self.len == 32:
self.sim.mem.write(addr, int(self.data[0:8], 16))
self.sim.mem.write(addr+4, int(self.data[8:16], 16))
self.sim.mem.write(addr+8, int(self.data[16:24], 16))
self.sim.mem.write(addr+12, int(self.data[24:32], 16))
self.sim.mem.write(addr+16, int(self.data[32:40], 16))
self.sim.mem.write(addr+20, int(self.data[40:48], 16))
self.sim.mem.write(addr+24, int(self.data[48:56], 16))
self.sim.mem.write(addr+28, int(self.data[56:64], 16))

else:
raise Exception(f'A2L2Trans: unsupported store len={self.len}')


# ------------------------------------------------------------------------------------------------
# Functions

def hex(n, pad=0):
if pad:
return f'000000000000000000000000{n.value.hex()[2:].upper()}'[-pad:]
else:
return n.value.hex()[2:].upper()

# ------------------------------------------------------------------------------------------------
# Tasks

async def A2L2Driver(dut, sim):
"""A2L2 node interface"""

transTypes = {
'00': 'IFETCH',
'08': 'LOAD',
'20': 'STORE'
}

ok = True
readPending = []
countReads = 0
mem = {}
sim.msg('A2L2 Driver: started.')

dut.an_ac_flh2l2_gate.value = 0

while ok and not sim.done:

await RisingEdge(dut.clk_1x)

dut.an_ac_req_ld_pop.value = 0
dut.an_ac_req_st_pop.value = 0
dut.an_ac_req_st_gather.value = 0

dut.an_ac_reld_data_coming.value = 0
dut.an_ac_reld_data_vld.value = 0
dut.an_ac_reld_ecc_err.value = 0
dut.an_ac_reld_ecc_err_ue.value = 0
dut.an_ac_reld_ditc.value = 0
dut.an_ac_reld_l1_dump.value = 0
dut.an_ac_req_spare_ctrl_a1.value = 0

if sim.threads == 1:
dut.an_ac_reservation_vld.value = 0
dut.an_ac_stcx_complete.value = 0
dut.an_ac_stcx_pass.value = 0
else:
for i in range(sim.threads):
dut.an_ac_reservation_vld[i].value = 0
dut.an_ac_stcx_complete[i].value = 0
dut.an_ac_stcx_pass[i].value = 0

dut.an_ac_sync_ack.value = 0
dut.an_ac_icbi_ack.value = 0
dut.an_ac_back_inv.value = 0

# bummer IndexError: Slice indexing is not supported
#dut.an_ac_reld_data[0:31].value = 0x48000000
#dut.an_ac_reld_data[32:63].value = 0x48000000
#dut.an_ac_reld_data[64:95].value = 0x48000000
#dut.an_ac_reld_data[96:127].value = 0x48000000
# bummer TypeError: Unsupported type for value assignment: <class 'str'> ('48000000480000004800000048000000')
#dut.an_ac_reld_data.value = '48000000480000004800000048000000'
#v = 0x48000000
# bummer TypeError: Unsupported type for value assignment: <class 'str'> ('01001000000000000000000000000000010010000000000000000000000000000100100000000000000000000000000001001000000000000000000000000000')
#dut.an_ac_reld_data.value = f'{v:0>32b}{v:0>32b}{v:0>32b}{v:0>32b}'
# otay!
#v1 = cocotb.binary.BinaryValue()
#v1.assign(f'{v:0>32b}{v:0>32b}{v:0>32b}{v:0>32b}')
#dut.an_ac_reld_data.value = v1.value

if dut.ac_an_req.value: # should first check ac_an_req_pwr_token prev cyc

tt = hex(dut.ac_an_req_ttype, 2)
transType = transTypes[tt]
tid = hex(dut.ac_an_req_thread)
ra = hex(dut.ac_an_req_ra, 8)
tag = hex(dut.ac_an_req_ld_core_tag, 2)
lenEnc = hex(dut.ac_an_req_ld_xfr_len)
le = 'LE ' if dut.ac_an_req_endian.value else ''
wimg_w = dut.ac_an_req_wimg_w.value
wimg_i = dut.ac_an_req_wimg_i.value
wimg_m = dut.ac_an_req_wimg_m.value
wimg_g = dut.ac_an_req_wimg_g.value
wimg = 0
if wimg_w:
wimg += 8
if wimg_i:
wimg += 4
if wimg_m:
wimg += 2
if wimg_g:
wimg += 1

if transType == 'IFETCH' or transType == 'LOAD':
# when allowing out-of-order, schedule reld once added
if len(readPending) == 0:
reldCyc = sim.cycle + 6 # const for now
else:
reldCyc = readPending[-1].cycD + 4 # worst-case const for now
trans = A2L2Trans(sim, tid, int(tt, 16), int(tag, 16), int(ra, 16), int(lenEnc, 16), wimg, reldCyc)
readPending.append(trans)
sim.msg(f'T{tid} {transType} {ra} tag={tag} len={trans.len} {le}WIMG:{wimg:X} reld data:{trans.cycD}')
elif transType == 'STORE':
# should verify st_data_pwr_token prev cycle
be = hex(dut.ac_an_st_byte_enbl, 8)
data = hex(dut.ac_an_st_data, 64)
trans = A2L2Trans(sim, tid, int(tt, 16), int(tag, 16), int(ra, 16), int(lenEnc, 16), wimg, None, be=be, data=data)
sim.msg(f'T{tid} {transType} {ra} tag={tag} len={trans.len} be={be} data={data} {le}WIMG:{wimg:X}')
trans.doStore()
#assert False, 'got a store'

# data early indicator (d-3)
dut.an_ac_reld_data_coming.value = 0
for i in range(len(readPending)):
trans = readPending[i]
if trans.cycC == sim.cycle:
dut.an_ac_reld_data_coming.value = 1
if trans.xferNum == 0 and trans.xfers == 4: # 4 beats b2b - need diff scheduling for all modes
trans.cycC += 2

# data valid indicator (d-2)
dut.an_ac_reld_data_vld.value = 0
dut.an_ac_reld_core_tag.value = 0x1F
dut.an_ac_reld_ditc.value = 1
dut.an_ac_reld_qw.value = 3
dut.an_ac_reld_crit_qw.value = 1

for i in range(len(readPending)):
trans = readPending[i]
if trans.cycV == sim.cycle:
trans.xferNum += 1
dut.an_ac_reld_data_vld.value = 1
dut.an_ac_reld_core_tag.value = trans.tag
dut.an_ac_reld_ditc.value = 1 if trans.ditc else 0
dut.an_ac_reld_qw.value = trans.xferNum - 1
dut.an_ac_reld_crit_qw.value = 1 if trans.xferNum == trans.xferCrit else 0
if trans.xferNum < 4 and trans.xfers == 4:
trans.cycV += 1

# data beat
if len(readPending) > 0 and readPending[0].cycD == sim.cycle: # ordered

trans = readPending[0]
w0,w1,w2,w3,beatNum = trans.readXfer()

v1 = cocotb.binary.BinaryValue()
v1.assign(f'{w0:0>32b}{w1:0>32b}{w2:0>32b}{w3:0>32b}')
dut.an_ac_reld_data.value = v1.value

sim.msg(f'RELD tag={trans.tag:02X} {w0:08X}{w1:08X}{w2:08X}{w3:08X} {beatNum}of{trans.xfers}{" crit" if beatNum == trans.xferCrit else ""}')

if beatNum == trans.xfers:
trans.done = True
countReads += 1 #wtf do this in monitor
if len(readPending) == 1:
readPending = []
else:
readPending = readPending[1:]
dut.an_ac_req_ld_pop.value = 1 #wtf can randomize, etc.


# A2L2 Checker
# check protocol, etc.
async def A2L2Checker(dut, sim):
"""A2L2 interface checker """

me = 'A2L2 Checker'
ok = True
sim.msg(f'{me}: started.')

while ok:
await RisingEdge(dut.clk_1x)


# A2L2 Monitor
# count transactions, etc.
# fail on bad addresses
async def A2L2Monitor(dut, sim):
"""A2L2 interface monitor"""

me = 'A2L2 Monitor'
ok = True
start = len(sim.config.a2l2.badAddr) > 0
sim.msg(f'{me}: started.')

while start and ok:

await RisingEdge(dut.clk_1x)

if dut.ac_an_req.value: # should first check ac_an_req_pwr_token prev cyc

tt = hex(dut.ac_an_req_ttype, 2)
if tt == '00': #wtf someone should make this a enum/class
ra = dut.ac_an_req_ra.value.integer
for i in range(len(sim.config.a2l2.badAddr)):
blk = sim.config.a2l2.badAddr[i]
if 'I' in blk[2].upper():
blkStart = int(blk[0], 16)
blkEnd = int(blk[1], 16)
if ra >= blkStart and ra <= blkEnd:
ok = False
assert False, (f'{me}: Bad IFetch @={ra:08X}') #wtf want this to end back in main code for summary

class A2L2:
driver = A2L2Driver
checker = A2L2Checker
monitor = A2L2Monitor

def __init__(self):
pass

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# a2o tb
# make -f Makefile.icarus build # rebuild and sim and fst
# make -f Makefile.icarus run # sim and fst
# make -f Makefile.icarus # sim

#COCOTB_LOG_LEVEL=DEBUG
#GPI_EXTRA=vpi

#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM

#SIM_BUILD ?= build
SIM ?= icarus

# options
#COCOTB_HDL_TIMEUNIT ?= 1ns
#COCOTB_HDL_TIMEPRECISION ?= 1ps
#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM

# icarus
#
# includes are needed for *.vh
# unisims is for FPGA RAMs
# coco forces -g2012 for some reason, and appends it after COMPILE_ARGS below! issue #781

VERILOG_ROOT = ../../verilog

COMPILE_ARGS = -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work

# other options

# rtl
TOPLEVEL_LANG = verilog
# top-level to enable trace, etc.
VERILOG_SOURCES = ./cocotb_icarus.v
TOPLEVEL = cocotb_icarus

# python test
MODULE = tb

# cocotb make rules
include $(shell cocotb-config --makefiles)/Makefile.sim

build: clean sim fst

run: sim fst

fst:
vcd2fst wtf-coco.vcd wtf-coco.fst
rm wtf-coco.vcd

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# a2o smt2 tb
# make -f Makefile.icarus build # rebuild and sim and fst
# make -f Makefile.icarus run # sim and fst
# make -f Makefile.icarus # sim

SIM_BUILD ?= build_smt2
SIM ?= icarus

# options
#COCOTB_HDL_TIMEUNIT ?= 1ns
#COCOTB_HDL_TIMEPRECISION ?= 1ps
#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM

# icarus
#
# includes are needed for *.vh
# unisims is for FPGA RAMs
# coco forces -g2012 for some reason, and appends it after COMPILE_ARGS below! issue #781

VERILOG_ROOT = ../../verilog

COMPILE_ARGS = -I$(VERILOG_ROOT)/smt2 -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work

# other options

# rtl
TOPLEVEL_LANG = verilog
# top-level to enable trace, etc.
VERILOG_SOURCES = ./cocotb_icarus.v
TOPLEVEL = cocotb_icarus

# python test
MODULE = tb

# cocotb make rules
include $(shell cocotb-config --makefiles)/Makefile.sim

build: clean sim fst

run: sim fst

fst:
vcd2fst wtf-coco.vcd wtf-coco.fst
rm wtf-coco.vcd

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# a2o tb
# make -f Makefile.icarus build # rebuild and sim and fst
# make -f Makefile.icarus run # sim and fst
# make -f Makefile.icarus # sim

#COCOTB_LOG_LEVEL=DEBUG
#GPI_EXTRA=vpi

#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM

SIM_BUILD ?= build_sweetpea
SIM ?= icarus

# options
#COCOTB_HDL_TIMEUNIT ?= 1ns
#COCOTB_HDL_TIMEPRECISION ?= 1ps
#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM

# icarus

VERILOG_ROOT = ../../verilog

COMPILE_ARGS = -I$(VERILOG_ROOT)/sweetpea -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work

# other options

# rtl
TOPLEVEL_LANG = verilog
# top-level to enable trace, etc.
VERILOG_SOURCES = ./cocotb_icarus.v
TOPLEVEL = cocotb_icarus

# python test
MODULE = tb

# cocotb make rules
include $(shell cocotb-config --makefiles)/Makefile.sim

build: clean sim fst

run: sim fst

fst:
vcd2fst wtf-coco.vcd wtf-coco.fst
rm wtf-coco.vcd

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# a2o tb

SIM_BUILD ?= sim_build_verilator
SIM ?= verilator

# set precision
#COCOTB_HDL_TIMEPRECISION ?= 1ns

# verilator
COMPILE_ARGS = --error-limit 1 --language 1364-2001 -Wno-fatal -Wno-LITENDIAN -Iverilog/work -Iverilog/trilib -Iverilog/unisims

# coverage
#EXTRA_ARGS += --coverage
# tracing
EXTRA_ARGS += --trace

# rtl
TOPLEVEL_LANG = verilog
VERILOG_SOURCES += verilog/trilib_clk1x/*.v
VERILOG_SOURCES += verilog/trilib/*.v
VERILOG_SOURCES += verilog/work/*.v

# rtl top
TOPLEVEL = c

# python test
MODULE = tbv

# cocotb make rules
include $(shell cocotb-config --makefiles)/Makefile.sim

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# OP Environment

import cocotb
from cocotb.triggers import Timer
from cocotb.handle import Force
from cocotb.handle import Release

from dotmap import DotMap

# ------------------------------------------------------------------------------------------------
# Classes

class Sim(DotMap):

def msg(self, m):
self.dut._log.info(f'[{self.cycle:08d}] {m}') #wtf do multiline if /n in m

def __init__(self, dut, cfg=None):
super().__init__()
self.dut = dut
# defaults
self.memFiles = ['../mem/boot_ieq1.bin.hex'] #wtf cmdline parm
self.threads = None
self.resetCycle = 10
self.hbCycles = 100
self.clk2x = True
self.clk4x = False
self.resetAddr = 0xFFFFFFFC
self.resetOp = 0x48000002
self.maxCycles = 1500
self.memFiles = None
self.config = DotMap()
self.config.core = DotMap({
'creditsLd': None,
'creditsSt': None,
'creditsLdStSingle': False
})
self.config.a2l2 = DotMap({
'badAddr': [('E0','E0', 'IRW')]
})
# json
if cfg is not None:
pass

# runtime
self.cycle = 0
self.ok = True
self.fail = None
self.done = False

if self.threads is None:
try:
v = dut.an_ac_pm_thread_stop[1].value
self.threads = 2
except:
self.threads = 1
self.msg(f'Set threads={self.threads}.')

class TransQ(DotMap):
def __init__(self):
super().__init__()

class Memory(DotMap):

def __init__(self, sim, default=0, logStores=True):
super().__init__()
self.sim = sim
self.data = {}
self.le = False
self.default = default # default word data for unloaded
self.logStores = logStores

def loadFile(self, filename, format='ascii', addr=0, le=0):
# format # binary, ascii, ascii w/addr
# le: reverse bytes
try:
if format == 'ascii':
with open(filename, 'r') as f:
lines = f.readlines()
for line in lines:
self.data[addr] = int(line, 16) # key is int
addr += 4
elif format == 'binary':
pass
elif format == 'addrdata':
pass
except Exception as e:
self.sim.msg(f'Error reading {filename}:\n{e}')
raise IOError

# word-aligned byte address
def read(self, addr):
try:
addr = addr + 0
except:
addr = int(addr, 16)
if addr in self.data:
return self.data[addr]
else:
return self.default

# word-aligned byte address + data
def write(self, addr, data):
try:
addr = addr + 0
except:
addr = int(addr, 16)
try:
data = data + 0
except:
data = int(data, 16)
if self.logStores:
if addr not in self.data:
self.sim.msg(f'Mem Update: @{addr:08X} XXXXXXXX->{data:08X}')
else:
self.sim.msg(f'Mem Update: @{addr:08X} {self.data[addr]:08X}->{data:08X}')
self.data[addr] = data

@ -0,0 +1,913 @@
1 # © IBM Corp. 2020
2 # Licensed under and subject to the terms of the CC-BY 4.0
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
4 # Additional rights, including the right to physically implement a softcore
5 # that is compliant with the required sections of the Power ISA
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
7 # This README will be updated with additional information when OpenPOWER's
8 # license is available.
9
10 # boot kernel
11 # set up translations
12 # set up timer facilities
13 # set up threads
14 # call user code
15 # process user rc
16
17 # todo:
18 # 1. skip_printf_init flag should be threaded
19
20 .include "defines.s"
1 # © IBM Corp. 2020
2 # Licensed under and subject to the terms of the CC-BY 4.0
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
4 # Additional rights, including the right to physically implement a softcore
5 # that is compliant with the required sections of the Power ISA
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
7 # This README will be updated with additional information when OpenPOWER's
8 # license is available.
9
10 #-----------------------------------------
11 # Defines
12 #-----------------------------------------
13
14 # Regs
15
16 .set r0, 0
17 .set r1, 1
18 .set r2, 2
19 .set r3, 3
20 .set r4, 4
21 .set r5, 5
22 .set r6, 6
23 .set r7, 7
24 .set r8, 8
25 .set r9, 9
26 .set r10,10
27 .set r11,11
28 .set r12,12
29 .set r13,13
30 .set r14,14
31 .set r15,15
32 .set r16,16
33 .set r17,17
34 .set r18,18
35 .set r19,19
36 .set r20,20
37 .set r21,21
38 .set r22,22
39 .set r23,23
40 .set r24,24
41 .set r25,25
42 .set r26,26
43 .set r27,27
44 .set r28,28
45 .set r29,29
46 .set r30,30
47 .set r31,31
48
49 .set f0, 0
50 .set f1, 1
51 .set f2, 2
52 .set f3, 3
53 .set f4, 4
54 .set f5, 5
55 .set f6, 6
56 .set f7, 7
57 .set f8, 8
58 .set f9, 9
59 .set f10,10
60 .set f11,11
61 .set f12,12
62 .set f13,13
63 .set f14,14
64 .set f15,15
65 .set f16,16
66 .set f17,17
67 .set f18,18
68 .set f19,19
69 .set f20,20
70 .set f21,21
71 .set f22,22
72 .set f23,23
73 .set f24,24
74 .set f25,25
75 .set f26,26
76 .set f27,27
77 .set f28,28
78 .set f29,29
79 .set f30,30
80 .set f31,31
81
82 .set cr0, 0
83 .set cr1, 1
84 .set cr2, 2
85 .set cr3, 3
86 .set cr4, 4
87 .set cr5, 5
88 .set cr6, 6
89 .set cr7, 7
90
91 # SPR numbers
92
93 .set srr0, 26
94 .set srr1, 27
95 .set epcr, 307
96 .set tar, 815
97
98 .set dbsr, 304
99 .set dbcr0, 308
100 .set dbcr1, 309
101 .set dbcr2, 310
102 .set dbcr3, 848
103
104 .set ivpr, 63
105
106 .set iucr0, 1011
107 .set iucr1, 883
108 .set iucr2, 884
109
110 .set iudbg0, 888
111 .set iudbg1, 889
112 .set iudbg2, 890
113 .set iulfsr, 891
114 .set iullcr, 892
115
116 .set mmucr0, 1020
117 .set mmucr1, 1021
118 .set mmucr2, 1022
119 .set mmucr3, 1023
120
121 .set tb, 268
122 .set tbl, 284
123 .set tbh, 285
124
125 .set dec, 22
126 .set udec, 550
127 .set tsr, 336
128 .set tcr, 340
129
130 .set xucr0, 1014
131 .set xucr1, 851
132 .set xucr2, 1016
133 .set xucr3, 852
134 .set xucr4, 853
135
136 .set tens, 438
137 .set tenc, 439
138 .set tensr, 437
139
140 .set pid, 48
141 .set pir, 286
142 .set pvr, 287
143 .set tir, 446
144
21
22 .section .text
23 start:
24
25 int_000:
26 0000 48000400 b boot_start
27
28 # critical input
29 0004 4800001C .align 5
29 60000000
29 60000000
29 60000000
29 60000000
30 int_020:
31 0020 48000000 b .
32
33 # debug
34 0024 4800001C .align 5
34 60000000
34 60000000
34 60000000
34 60000000
35 int_040:
36 0040 48000000 b .
37
38 # dsi
39 0044 4800001C .align 5
39 60000000
39 60000000
39 60000000
39 60000000
40 int_060:
41 0060 48000000 b .
42
43 # isi
44 0064 4800001C .align 5
44 60000000
44 60000000
44 60000000
44 60000000
45 int_080:
46 0080 48000000 b .
47
48 # external
49 0084 4800001C .align 5
49 60000000
49 60000000
49 60000000
49 60000000
50 int_0A0:
51 00a0 48000000 b .
52
53 # alignment
54 00a4 4800001C .align 5
54 60000000
54 60000000
54 60000000
54 60000000
55 int_0C0:
56 00c0 48000000 b .
57
58 # program
59 00c4 4800001C .align 5
59 60000000
59 60000000
59 60000000
59 60000000
60 int_0E0:
61 00e0 48000000 b .
62
63 # fp unavailable
64 00e4 4800001C .align 5
64 60000000
64 60000000
64 60000000
64 60000000
65 int_100:
66 0100 48000000 b .
67
68 # sc
69 0104 4800001C .align 5
69 60000000
69 60000000
69 60000000
69 60000000
70 int_120:
71 0120 48000CE0 b int_120_handler
72
73 # apu unavailable
74 0124 4800001C .align 5
74 60000000
74 60000000
74 60000000
74 60000000
75 int_140:
76 0140 48000000 b .
77
78 # decrementer
79 0144 4800001C .align 5
79 60000000
79 60000000
79 60000000
79 60000000
80 int_160:
81 0160 48000000 b .
82
83 # fit
84 0164 4800001C .align 5
84 60000000
84 60000000
84 60000000
84 60000000
85 int_180:
86 0180 48000000 b .
87
88 # watchdog
89 0184 4800001C .align 5
89 60000000
89 60000000
89 60000000
89 60000000
90 int_1A0:
91 01a0 48000000 b .
92
93 # dtlb
94 01a4 4800001C .align 5
94 60000000
94 60000000
94 60000000
94 60000000
95 int_1C0:
96 01c0 48000000 b .
97
98 # itlb
99 01c4 4800001C .align 5
99 60000000
99 60000000
99 60000000
99 60000000
100 int_1E0:
101 01e0 48000000 b .
102
103 # vector unavailable
104 01e4 4800001C .align 5
104 60000000
104 60000000
104 60000000
104 60000000
105 int_200:
106 0200 48000000 b .
107
108 #
109 0204 4800001C .align 5
109 60000000
109 60000000
109 60000000
109 60000000
110 int_220:
111 0220 48000000 b .
112
113 #
114 0224 4800001C .align 5
114 60000000
114 60000000
114 60000000
114 60000000
115 int_240:
116 0240 48000000 b .
117
118 #
119 0244 4800001C .align 5
119 60000000
119 60000000
119 60000000
119 60000000
120 int_260:
121 0260 48000000 b .
122
123 # doorbell
124 0264 4800001C .align 5
124 60000000
124 60000000
124 60000000
124 60000000
125 int_280:
126 0280 48000000 b .
127
128 # doorbell critical
129 0284 4800001C .align 5
129 60000000
129 60000000
129 60000000
129 60000000
130 int_2A0:
131 02a0 48000000 b .
132
133 # doorbell guest
134 02a4 4800001C .align 5
134 60000000
134 60000000
134 60000000
134 60000000
135 int_2C0:
136 02c0 48000000 b .
137
138 # doorbell guest critical
139 02c4 4800001C .align 5
139 60000000
139 60000000
139 60000000
139 60000000
140 int_2E0:
141 02e0 48000000 b .
142
143 # hvsc
144 02e4 4800001C .align 8
144 60000000
144 60000000
144 60000000
144 60000000
145 int_300:
146 0300 48000A00 b int_300_handler
147
148 # hvpriv
149 0304 4800001C .align 5
149 60000000
149 60000000
149 60000000
149 60000000
150 int_320:
151 0320 48000000 b .
152
153 # lrat
154 0324 4800001C .align 5
154 60000000
154 60000000
154 60000000
154 60000000
155 int_340:
156 0340 48000000 b .
157
158 # -------------------------------------------------------------------------------------------------
159 # initial translation
160 # both erats:
161 # 00000000 1M: (boot)
162 # 10000000 1M: (test)
163
164 0344 480000BC .align 8
164 60000000
164 60000000
164 60000000
164 60000000
165 boot_start:
166
167 0400 7CBE6AA6 mfspr r5,tir # who am i?
168 0404 2C250000 cmpdi r5,0x00 # skip unless T0
169 0408 408200EC bne init_t123
170
171 040c 3C608C00 lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
172 # derat 31 @00000000
173
174 0410 3800001F li r0,0x001F # entry #31
175 0414 38400015 li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
176 0418 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
177 041c 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
178
179 0420 7C7CFBA6 mtspr mmucr0,r3
180 0424 7C4011A6 eratwe r2,r0,2
181 0428 7C8009A6 eratwe r4,r0,1
182 042c 7D0001A6 eratwe r8,r0,0
183 0430 4C00012C isync
184
185 0434 81400A08 lwz r10,CONFIG+S_ERATW2(r0) # load parms for erat settings
186
187 # derat 30 @100000000
188
189 0438 3800001E li r0,0x001E # entry #30
190 043c 3C801000 lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
191 0440 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
192 0444 65081000 oris r8,r8,0x1000
193
194 0448 7D4011A6 eratwe r10,r0,2
195 044c 7C8009A6 eratwe r4,r0,1
196 0450 7D0001A6 eratwe r8,r0,0
197 0454 4C00012C isync
198
199 0458 3C608800 lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
200 # ierat 15 @00000000
201
202 045c 3800000F li r0,0x000F # entry #15
203 0460 3840003F li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
204 0464 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
205 0468 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
206
207 046c 7C7CFBA6 mtspr mmucr0,r3
208 0470 7C4011A6 eratwe r2,r0,2
209 0474 7C8009A6 eratwe r4,r0,1
210 0478 7D0001A6 eratwe r8,r0,0
211 047c 4C00012C isync
212
213 # *** leave the init'd entry 14 for MT access to FFFFFFC0
214 # ierat 13 @10000000
215
216 0480 3800000D li r0,0x000D # entry #13
217 0484 3C801000 lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
218 0488 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
219 048c 65081000 oris r8,r8,0x1000
220
221 0490 7D4011A6 eratwe r10,r0,2
222 0494 7C8009A6 eratwe r4,r0,1
223 0498 7D0001A6 eratwe r8,r0,0
224 049c 4C00012C isync
225
226 # -------------------------------------------------------------------------------------------------
227 # init
228 #
229
230 # T0-only
231 # set up any core facilities, then enable the others if config'd
232 init_t0:
233
234 # switch to 64b
235
236 04a0 81400A00 lwz r10,CONFIG+S_MSR(r0)
237 04a4 7D400124 mtmsr r10
238 04a8 4C00012C isync
239
240 # other init
241
242 04ac 3C200300 lis r1,0x0300 # icm=gicm=1
243 04b0 7C334BA6 mtspr epcr,r1
244
245 # set up timer facs
246
247 04b4 38200000 li r1,0 # clear
248 04b8 7C3603A6 mtspr dec,r1
249 04bc 7C3D43A6 mtspr tbh,r1
250 04c0 7C3C43A6 mtspr tbl,r1
251
252 04c4 3C40FE00 lis r2,0xFE00 # mask: clear enw,wis,wrs,dis,fis,udis
253 04c8 7C5053A6 mtspr tsr,r2
254
255 04cc 7C56FAA6 mfspr r2,xucr0
256 04d0 70420200 andi. r2,r2,0x0200 # set tcs=0
257 04d4 7C56FBA6 mtspr xucr0,r2
258
259 04d8 7C3053A6 mtspr tsr,r1 # clear tsr
260 04dc 7C3453A6 mtspr tcr,r1 # disable all timers
261
262 # set thread configuration
263
264 04e0 80200A04 lwz r1,CONFIG+S_FLAGS(r0)
265 04e4 7021000F andi. r1,r1,0xF
266 04e8 7C366BA6 mtspr tens,r1 # 60:63 = tid 3:0 enabled
267 #not r1,r1
268 #mtspr tenc,r1 # in case T0 is marked disabled
269 04ec 4C00012C isync
270
271 04f0 48000014 b boot_complete
272
273 # except T0
274 # just worry about myself
275
276 init_t123:
277
278 # switch to 64b
279
280 04f4 81400A00 lwz r10,CONFIG+S_MSR(r0)
281 04f8 7D400124 mtmsr r10
282 04fc 4C00012C isync
283
284 0500 48000004 b boot_complete
285
286 # -------------------------------------------------------------------------------------------------
287 boot_complete:
288
289 # set up thread and hop to it
290
291 0504 80200A04 lwz r1,CONFIG+S_FLAGS(r0)
292 0508 74218000 andis. r1,r1,0x8000 # 1=skip initial printf init
293 050c 40820008 bne boot_complete_1
294 0510 480006F1 bl printf_reset # wipe buffer
295
296 boot_complete_1:
297
298 0514 80200A04 lwz r1,CONFIG+S_FLAGS(r0)
299 0518 3C407FFF lis r2,0x7FFF # clear printf flag
300 051c 6042FFFF ori r2,r2,0xFFFF
301 0520 7C211038 and r1,r1,r2
302 0524 90200A04 stw r1,CONFIG+S_FLAGS(r0)
303
304 0528 7CBE6AA6 mfspr r5,tir # who am i?
305 052c 78A53664 sldi r5,r5,6 # 64B offset
306 0530 38A50A80 addi r5,r5,CONFIG+T_CONFIG
307
308 0534 81650000 lwz r11,T_MSR(r5)
309 0538 E9850008 ld r12,T_STACK(r5)
310 053c E9A50010 ld r13,T_ENTRY(r5)
311
312 0540 80200A04 lwz r1,CONFIG+S_FLAGS(r0)
313 0544 70210010 andi. r1,r1,FLAG_EOT_SC
314 0548 4182001C beq eot_blr
315
316 eot_sc:
317
318 054c 80400A0C lwz r2,CONFIG+S_EOT_SC(r0)
319 0550 3C204400 lis r1,0x4400 # 'sc 1'
320 0554 60210012 ori r1,r1,0022
321 0558 F8220000 std r1,0x0(r2)
322 055c 7C2803A6 mtlr r1 # prog will blr to sc
323 0560 48000014 b process_start
324
325 eot_blr:
326
327 0564 48000005 bl 4
328 0568 7C2802A6 mflr r1
329 056c 38210030 addi r1,r1,0x30 # !!!!!!!!!!!!!!! <-- WARNING!
330 0570 7C2803A6 mtlr r1 # prog will blr to exec_complete
331
332 process_start:
333
334 0574 7D7B03A6 mtspr srr1,r11 # msr
335 0578 7DBA03A6 mtspr srr0,r13 # @entry
336 057c 7D816378 mr r1,r12 # @stack
337 0580 7C7E6AA6 mfspr r3,tir # tid - main(tid) if yall want it
338
339 0584 7C4C42A6 mfspr r2,tb
340 0588 F8450030 std r2,T_TIMER_START(r5)
341 058c 4C000064 rfi
342 0590 60000000 nop # !!!!!!!!!!!!!!! pads for lr calc
343 0594 60000000 nop
344 0598 60000000 nop
345
346 # -------------------------------------------------------------------------------------------------
347 exec_complete:
348 # allow blr to here, or it will be entered by sc directly
349
350 # user blr'd here...
351 059c 44000022 sc 1 # hvsc back to sup state
352
353 exec_complete_sup:
354 05a0 7CBE6AA6 mfspr r5,tir # who am i?
355 05a4 78A53664 sldi r5,r5,6 # 64B offset
356 05a8 38A50A80 addi r5,r5,CONFIG+T_CONFIG
357
358 05ac 7C4C42A6 mfspr r2,tb
359 05b0 F8450038 std r2,T_TIMER_END(r5)
360
361 05b4 2C230000 cmpdi r3,0 # check rc
362 05b8 41820148 beq pass
363 05bc 48000044 b fail
364
365 # -------------------------------------------------------------------------------------------------
366 # dead zone
367 05c0 48000040 .align 8
367 60000000
367 60000000
367 60000000
367 60000000
368 fail:
369 0600 48000000 b .
370
371 # -------------------------------------------------------------------------------------------------
372 # happy ending
373 0604 480000FC .align 8
373 60000000
373 60000000
373 60000000
373 60000000
374 pass:
375 0700 48000000 b .
376
377 # -------------------------------------------------------------------------------------------------
378
379 # dec
380 0704 480000FC .align 11
380 60000000
380 60000000
380 60000000
380 60000000
381 int_800:
382 0800 48000000 b .
383
384 # perf
385 0804 4800001C .align 5
385 60000000
385 60000000
385 60000000
385 60000000
386 int_820:
387 0820 48000000 b .
388
389 .set CONFIG,0x0A00
390 # -------------------------------------------------------------------------------------------------
391 # config info
392 0824 480001DC .align 9
392 60000000
392 60000000
392 60000000
392 60000000
393
394 0a00 8002B000 .long 0x8002B000 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
395 0a04 80000001 .long 0x80000001 # flags: skip_printf_init=0 eot_sc=27 thr_en=28:31(T3:T0)
396 0a08 000000BF .long 0x000000BF # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wi
397 0a0c 10000000 .long 0x10000000 # @user eot sc
398
399 # per-thread configs (64B each)
400 0a10 48000070 .align 7
400 60000000
400 60000000
400 60000000
400 60000000
401 0a80 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
402 0a84 00000000 .long 0x00000000 #
403 0a88 00000000 .long 0x00000000 #
404 0a8c 1003FF00 .long 0x1003FF00 # @stack
405 0a90 00000000 .long 0x00000000 #
406 0a94 100004B0 .long 0x100004B0 # @entry
407 0a98 00000000 .long 0
408 0a9c 10030000 .long 0x10030000 # @print_start
409 0aa0 00000000 .long 0
410 0aa4 10031FFF .long 0x10031FFF # @print_end
411 0aa8 00000000 .long 0
412 0aac 10030000 .long 0x10030000 # print ptr
413 0ab0 00000000 .quad 0 # start tb
413 00000000
414 0ab8 00000000 .quad 0 # end tb
414 00000000
415
416 0ac0 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
417 0ac4 00000000 .long 0x00000000 #
418 0ac8 00000000 .long 0x00000000 #
419 0acc 1003DF00 .long 0x1003DF00 # @stack
420 0ad0 00000000 .long 0x00000000 #
421 0ad4 100004B0 .long 0x100004B0 # @entry
422 0ad8 00000000 .long 0
423 0adc 10032000 .long 0x10032000 # @print_start
424 0ae0 00000000 .long 0
425 0ae4 10033FFF .long 0x10033FFF # @print_end
426 0ae8 00000000 .long 0
427 0aec 10032000 .long 0x10032000 # print ptr
428 0af0 00000000 .quad 0 # start tb
428 00000000
429 0af8 00000000 .quad 0 # end tb
429 00000000
430
431 0b00 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
432 0b04 00000000 .long 0x00000000 # flags
433 0b08 00000000 .long 0x00000000 #
434 0b0c 1003BF00 .long 0x1003BF00 # @stack
435 0b10 00000000 .long 0x00000000 #
436 0b14 100004B0 .long 0x100004B0 # @entry
437 0b18 00000000 .long 0
438 0b1c 10034000 .long 0x10034000 # @print_start
439 0b20 00000000 .long 0
440 0b24 10035FFF .long 0x10035FFF # @print_end
441 0b28 00000000 .long 0
442 0b2c 10034000 .long 0x10034000 # print ptr
443 0b30 00000000 .quad 0 # start tb
443 00000000
444 0b38 00000000 .quad 0 # end tb
444 00000000
445
446 0b40 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
447 0b44 00000000 .long 0x00000000 # flags
448 0b48 00000000 .long 0x00000000 #
449 0b4c 10039F00 .long 0x10039F00 # @stack
450 0b50 00000000 .long 0x00000000 #
451 0b54 100004B0 .long 0x100004B0 # @entry
452 0b58 00000000 .long 0
453 0b5c 10036000 .long 0x10036000 # @print_start
454 0b60 00000000 .long 0
455 0b64 10037FFF .long 0x10037FFF # @print_end
456 0b68 00000000 .long 0
457 0b6c 10036000 .long 0x10036000 # print ptr
458 0b70 00000000 .quad 0 # start tb
458 00000000
459 0b78 00000000 .quad 0 # end tb
459 00000000
460
461
462 .set S_MSR,0x00
463 .set S_FLAGS,0x04
464 .set S_ERATW2,0x08
465 .set S_EOT_SC,0x0C
466
467 .set T_CONFIG,0x80
468 .set T_MSR,0x00
469 .set T_FLAGS,0x04
470 .set T_STACK,0x08
471 .set T_ENTRY,0x10
472 .set T_TIMER_START,0x30
473 .set T_TIMER_END,0x38
474 .set T_PRINTSTART, 0x18
475 .set T_PRINTEND, 0x20
476 .set T_PRINTF, 0x28
477 .set FLAG_EOT_SC,0x10
478
479
480 # -------------------------------------------------------------------------------------------------
481 # other stuff
482 0b80 48000080 .align 10
482 60000000
482 60000000
482 60000000
482 60000000
483
484 # clear buffer and reset pointer to start
485 .align 6
486 printf_reset:
487
488 0c00 7CBE6AA6 mfspr r5,tir # who am i?
489 0c04 78A53664 sldi r5,r5,6 # 64B offset
490 0c08 38A50A80 addi r5,r5,CONFIG+T_CONFIG
491
492 0c0c 38C50018 addi r6,r5,T_PRINTSTART
493 0c10 E8E60000 ld r7,0(r6) # buffer start
494 0c14 38C50020 addi r6,r5,T_PRINTEND
495 0c18 E9060000 ld r8,0(r6) # buffer end
496 0c1c 7D074050 sub r8,r8,r7
497 0c20 39080001 addi r8,r8,1 # num bytes
498
499 0c24 7D0903A6 mtctr r8
500 0c28 38C00000 li r6,0
501 0c2c 7CE83B78 mr r8,r7
502 printf_reset_clr:
503 0c30 98C80000 stb r6,0(r8)
504 0c34 39080001 addi r8,r8,1
505 0c38 4200FFF8 bdnz printf_reset_clr
506
507 0c3c 39050028 addi r8,r5,T_PRINTF
508 0c40 F8E80000 std r7,0(r8) # reset ptr
509
510 0c44 4E800020 blr
511
512
513 # hvsc
514 0c48 480000B8 .align 8
514 60000000
514 60000000
514 60000000
514 60000000
515 # go to exec_complete_sup in sup mode
516 int_300_handler:
517
518 0d00 80000A00 lwz r0,CONFIG+S_MSR(r0)
519 0d04 7C000124 mtmsr r0
520 0d08 4C00012C isync
521 0d0c 4BFFF894 b exec_complete_sup
522
523 # sc
524 0d10 480000F0 .align 8
524 60000000
524 60000000
524 60000000
524 60000000
525 # r3 is id, remaining are function-specific
526 # not preserving r0, r3-r9 right now
527 #
528 # 0001 whoami
529 # 0010 tick
530 # 0100 putchar r4=c
531 # 0106 printf_mode *NI*
532 # 0107 printf_rst
533 #
534 int_120_handler:
535
536 0e00 7C0802A6 mflr r0
537
538 0e04 2C230001 cmpdi r3,0x0001
539 0e08 41820038 beq sc_whoami
540 0e0c 2C230010 cmpdi r3,0x0010
541 0e10 41820070 beq sc_tick
542 0e14 2C230100 cmpdi r3,0x100
543 0e18 418200A8 beq sc_putchar
544 0e1c 2C230107 cmpdi r3,0x107
545 0e20 41820120 beq sc_printf_rst
546
547 0e24 3860FFFF li r3,-1
548 0e28 7C0803A6 mtlr r0
549 0e2c 4C000064 rfi
550
551 # thread id
552 0e30 60000000 .align 6
552 60000000
552 60000000
552 60000000
553 sc_whoami:
554 0e40 7C7E6AA6 mfspr r3,tir
555 0e44 4C000064 rfi
556
557 # tb
558 0e48 48000038 .align 6
558 60000000
558 60000000
558 60000000
558 60000000
559 sc_tick:
560 0e80 7C6C42A6 mfspr r3,tb
561 0e84 4C000064 rfi
562
563 # wrap buffer; could add flag to stop when full, or reset
564 0e88 48000038 .align 6
564 60000000
564 60000000
564 60000000
564 60000000
565 sc_putchar:
566
567 0ec0 7CBE6AA6 mfspr r5,tir # who am i?
568 0ec4 78A53664 sldi r5,r5,6 # 64B offset
569 0ec8 38A50A80 addi r5,r5,CONFIG+T_CONFIG
570
571 0ecc 38C50028 addi r6,r5,T_PRINTF
572 0ed0 E8E60000 ld r7,0(r6) # buffer ptr
573 0ed4 98870000 stb r4,0(r7) # store char
574 0ed8 38E70001 addi r7,r7,1
575
576 0edc 39050020 addi r8,r5,T_PRINTEND
577 0ee0 E9080000 ld r8,0(r8) # buffer end
578 0ee4 7C274000 cmpd r7,r8
579 0ee8 38600000 li r3,0 # rc=normal
580 0eec 40810010 ble sc_putchar_ok
581 0ef0 39050018 addi r8,r5,T_PRINTSTART
582 0ef4 E8E80000 ld r7,0(r8) # buffer start
583 0ef8 3860FFFF li r3,-1 # rc=full
584 sc_putchar_ok:
585 0efc F8E60000 std r7,0(r6) # save ptr
586
587 0f00 4C000064 rfi
588
589 # clear buffer and reset pointer to start
590 0f04 4800003C .align 6
590 60000000
590 60000000
590 60000000
590 60000000
591 sc_printf_rst:
592
593 0f40 7C6902A6 mfctr r3
594
595 0f44 4BFFFCBD bl printf_reset
596
597 0f48 7C6903A6 mtctr r3
598 0f4c 7C0803A6 mtlr r0
599 0f50 38600000 li r3,0
600
601 0f54 4C000064 rfi
602

@ -0,0 +1 @@
+timescale+1ns/1ps

@ -0,0 +1,321 @@

`include "tri_a2o.vh"

`timescale 1ns/1ps

// might add some sim-only lines to enable clks, etc.

module cocotb_icarus (

input[0:`NCLK_WIDTH-1] nclk,
input scan_in,
output scan_out,

// Pervasive clock control
input an_ac_rtim_sl_thold_8,
input an_ac_func_sl_thold_8,
input an_ac_func_nsl_thold_8,
input an_ac_ary_nsl_thold_8,
input an_ac_sg_8,
input an_ac_fce_8,
input [0:7] an_ac_abst_scan_in,

// L2 LARX/STCX
input [0:`THREADS-1] an_ac_reservation_vld,
input [0:`THREADS-1] an_ac_stcx_complete,
input [0:`THREADS-1] an_ac_stcx_pass,

// ICBI ACK Interface
input an_ac_icbi_ack,
input [0:1] an_ac_icbi_ack_thread,

// Back invalidate interface
input an_ac_back_inv,
input [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr,
input [0:4] an_ac_back_inv_target, // connect to bit(0)
input an_ac_back_inv_local,
input an_ac_back_inv_lbit,
input an_ac_back_inv_gs,
input an_ac_back_inv_ind,
input [0:7] an_ac_back_inv_lpar_id,
output ac_an_back_inv_reject,
output [0:7] ac_an_lpar_id,

// L2 Reload Inputs
input an_ac_reld_data_vld, // reload data is coming next cycle
input [0:4] an_ac_reld_core_tag, // reload data destinatoin tag (which load queue)
input [0:127] an_ac_reld_data, // Reload Data
input [58:59] an_ac_reld_qw, // quadword address of reload data beat
input an_ac_reld_ecc_err, // Reload Data contains a Correctable ECC error
input an_ac_reld_ecc_err_ue, // Reload Data contains an Uncorrectable ECC error
input an_ac_reld_data_coming,
input an_ac_reld_ditc,
input an_ac_reld_crit_qw,
input an_ac_reld_l1_dump,
input [0:3] an_ac_req_spare_ctrl_a1, // spare control bits from L2

// load/store credit control
input an_ac_flh2l2_gate, // Gate L1 Hit forwarding SPR config bit
input an_ac_req_ld_pop, // credit for a load (L2 can take a load command)
input an_ac_req_st_pop, // credit for a store (L2 can take a store command)
input an_ac_req_st_gather, // credit for a store due to L2 gathering of store commands
input [0:`THREADS-1] an_ac_sync_ack,

//SCOM Satellite
input [0:3] an_ac_scom_sat_id,
input an_ac_scom_dch,
input an_ac_scom_cch,
output ac_an_scom_dch,
output ac_an_scom_cch,

// FIR and Error Signals
output [0:`THREADS-1] ac_an_special_attn,
output [0:2] ac_an_checkstop,
output [0:2] ac_an_local_checkstop,
output [0:2] ac_an_recov_err,
output ac_an_trace_error,
output ac_an_livelock_active,
input an_ac_checkstop,
input [0:`THREADS-1] an_ac_external_mchk,

// Perfmon Event Bus
output [0:4*`THREADS-1] ac_an_event_bus0,
output [0:4*`THREADS-1] ac_an_event_bus1,

// Reset related
input an_ac_reset_1_complete,
input an_ac_reset_2_complete,
input an_ac_reset_3_complete,
input an_ac_reset_wd_complete,

// Power Management
output [0:`THREADS-1] ac_an_pm_thread_running,
input [0:`THREADS-1] an_ac_pm_thread_stop,
input [0:`THREADS-1] an_ac_pm_fetch_halt,
output ac_an_power_managed,
output ac_an_rvwinkle_mode,

// Clock, Test, and LCB Controls
input an_ac_gsd_test_enable_dc,
input an_ac_gsd_test_acmode_dc,
input an_ac_ccflush_dc,
input an_ac_ccenable_dc,
input an_ac_lbist_en_dc,
input an_ac_lbist_ip_dc,
input an_ac_lbist_ac_mode_dc,
input an_ac_scan_diag_dc,
input an_ac_scan_dis_dc_b,

//Thold input to clock control macro
input [0:8] an_ac_scan_type_dc,

// Pervasive
output ac_an_reset_1_request,
output ac_an_reset_2_request,
output ac_an_reset_3_request,
output ac_an_reset_wd_request,
input an_ac_lbist_ary_wrt_thru_dc,
input [0:`THREADS-1] an_ac_sleep_en,
input [0:`THREADS-1] an_ac_ext_interrupt,
input [0:`THREADS-1] an_ac_crit_interrupt,
input [0:`THREADS-1] an_ac_perf_interrupt,
input [0:`THREADS-1] an_ac_hang_pulse,
input an_ac_tb_update_enable,
input an_ac_tb_update_pulse,
input [0:3] an_ac_chipid_dc,
input [0:7] an_ac_coreid,
output [0:`THREADS-1] ac_an_machine_check,
input an_ac_debug_stop,
output [0:`THREADS-1] ac_an_debug_trigger,
input [0:`THREADS-1] an_ac_uncond_dbg_event,
output [0:31] ac_an_debug_bus,
output ac_an_coretrace_first_valid, // coretrace_ctrls[0]
output ac_an_coretrace_valid, // coretrace_ctrls[1]
output [0:1] ac_an_coretrace_type, // coretrace_ctrls[2:3]

// L2 Outputs
output ac_an_req_pwr_token, // power token for command coming next cycle
output ac_an_req, // command request valid
output [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra, // real address for request
output [0:5] ac_an_req_ttype, // command (transaction) type
output [0:2] ac_an_req_thread, // encoded thread ID
output ac_an_req_wimg_w, // write-through
output ac_an_req_wimg_i, // cache-inhibited
output ac_an_req_wimg_m, // memory coherence required
output ac_an_req_wimg_g, // guarded memory
output [0:3] ac_an_req_user_defined, // User Defined Bits
output [0:3] ac_an_req_spare_ctrl_a0, // Spare bits
output [0:4] ac_an_req_ld_core_tag, // load command tag (which load Q)
output [0:2] ac_an_req_ld_xfr_len, // transfer length for non-cacheable load
output [0:31] ac_an_st_byte_enbl, // byte enables for store data
output [0:255] ac_an_st_data, // store data
output ac_an_req_endian, // endian mode (0=big endian, 1=little endian)
output ac_an_st_data_pwr_token // store data power token
);

c c0(
// generic map (
// EXPAND_TYPE => EXPAND_TYPE
// );

.nclk(nclk),
.scan_in(scan_in),
.scan_out(scan_out),

// Pervasive clock control
.an_ac_rtim_sl_thold_8(an_ac_rtim_sl_thold_8),
.an_ac_func_sl_thold_8(an_ac_func_sl_thold_8),
.an_ac_func_nsl_thold_8(an_ac_func_nsl_thold_8),
.an_ac_ary_nsl_thold_8(an_ac_ary_nsl_thold_8),
.an_ac_sg_8(an_ac_sg_8),
.an_ac_fce_8(an_ac_fce_8),
.an_ac_abst_scan_in(an_ac_abst_scan_in),

// L2 STCX complete
.an_ac_stcx_complete(an_ac_stcx_complete),
.an_ac_stcx_pass(an_ac_stcx_pass),

// ICBI ACK Interface
.an_ac_icbi_ack(an_ac_icbi_ack),
.an_ac_icbi_ack_thread(an_ac_icbi_ack_thread),

// Back invalidate interface
.an_ac_back_inv(an_ac_back_inv),
.an_ac_back_inv_addr(an_ac_back_inv_addr),
.an_ac_back_inv_target(an_ac_back_inv_target),
.an_ac_back_inv_local(an_ac_back_inv_local),
.an_ac_back_inv_lbit(an_ac_back_inv_lbit),
.an_ac_back_inv_gs(an_ac_back_inv_gs),
.an_ac_back_inv_ind(an_ac_back_inv_ind),
.an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id),
.ac_an_back_inv_reject(ac_an_back_inv_reject),
.ac_an_lpar_id(ac_an_lpar_id),

// L2 Reload Inputs
.an_ac_reld_data_vld(an_ac_reld_data_vld),
.an_ac_reld_core_tag(an_ac_reld_core_tag),
.an_ac_reld_data(an_ac_reld_data),
.an_ac_reld_qw(an_ac_reld_qw),
.an_ac_reld_ecc_err(an_ac_reld_ecc_err),
.an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue),
.an_ac_reld_data_coming(an_ac_reld_data_coming),
.an_ac_reld_ditc(an_ac_reld_ditc),
.an_ac_reld_crit_qw(an_ac_reld_crit_qw),
.an_ac_reld_l1_dump(an_ac_reld_l1_dump),
.an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1),

// load/store credit control
.an_ac_flh2l2_gate(an_ac_flh2l2_gate),
.an_ac_req_ld_pop(an_ac_req_ld_pop),
.an_ac_req_st_pop(an_ac_req_st_pop),
.an_ac_req_st_gather(an_ac_req_st_gather),
.an_ac_sync_ack(an_ac_sync_ack),
.an_ac_pm_fetch_halt(an_ac_pm_fetch_halt),

//SCOM Satellite
.an_ac_scom_sat_id(an_ac_scom_sat_id),
.an_ac_scom_dch(an_ac_scom_dch),
.an_ac_scom_cch(an_ac_scom_cch),
.ac_an_scom_dch(ac_an_scom_dch),
.ac_an_scom_cch(ac_an_scom_cch),

// FIR and Error Signals
.ac_an_special_attn(ac_an_special_attn),
.ac_an_checkstop(ac_an_checkstop),
.ac_an_local_checkstop(ac_an_local_checkstop),
.ac_an_recov_err(ac_an_recov_err),
.ac_an_trace_error(ac_an_trace_error),
.ac_an_livelock_active(ac_an_livelock_active),
.an_ac_checkstop(an_ac_checkstop),
.an_ac_external_mchk(an_ac_external_mchk),

// Perfmon Event Bus
.ac_an_event_bus0(ac_an_event_bus0),
.ac_an_event_bus1(ac_an_event_bus1),

// Reset related
.an_ac_reset_1_complete(an_ac_reset_1_complete),
.an_ac_reset_2_complete(an_ac_reset_2_complete),
.an_ac_reset_3_complete(an_ac_reset_3_complete),
.an_ac_reset_wd_complete(an_ac_reset_wd_complete),

// Power Management
.ac_an_pm_thread_running(ac_an_pm_thread_running),
.an_ac_pm_thread_stop(an_ac_pm_thread_stop),
.ac_an_power_managed(ac_an_power_managed),
.ac_an_rvwinkle_mode(ac_an_rvwinkle_mode),

// Clock, Test, and LCB Controls
.an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc),
.an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc),
.an_ac_ccflush_dc(an_ac_ccflush_dc),
.an_ac_ccenable_dc(an_ac_ccenable_dc),
.an_ac_lbist_en_dc(an_ac_lbist_en_dc),
.an_ac_lbist_ip_dc(an_ac_lbist_ip_dc),
.an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc),
.an_ac_scan_diag_dc(an_ac_scan_diag_dc),
.an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b),

//Thold input to clock control macro
.an_ac_scan_type_dc(an_ac_scan_type_dc),

// Pervasive
.ac_an_reset_1_request(ac_an_reset_1_request),
.ac_an_reset_2_request(ac_an_reset_2_request),
.ac_an_reset_3_request(ac_an_reset_3_request),
.ac_an_reset_wd_request(ac_an_reset_wd_request),
.an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
.an_ac_reservation_vld(an_ac_reservation_vld),
.an_ac_sleep_en(an_ac_sleep_en),
.an_ac_ext_interrupt(an_ac_ext_interrupt),
.an_ac_crit_interrupt(an_ac_crit_interrupt),
.an_ac_perf_interrupt(an_ac_perf_interrupt),
.an_ac_hang_pulse(an_ac_hang_pulse),
.an_ac_tb_update_enable(an_ac_tb_update_enable),
.an_ac_tb_update_pulse(an_ac_tb_update_pulse),
.an_ac_chipid_dc(an_ac_chipid_dc),
.an_ac_coreid(an_ac_coreid),
.ac_an_machine_check(ac_an_machine_check),
.an_ac_debug_stop(an_ac_debug_stop),
.ac_an_debug_trigger(ac_an_debug_trigger),
.an_ac_uncond_dbg_event(an_ac_uncond_dbg_event),

// L2 Outputs
.ac_an_req_pwr_token(ac_an_req_pwr_token),
.ac_an_req(ac_an_req),
.ac_an_req_ra(ac_an_req_ra),
.ac_an_req_ttype(ac_an_req_ttype),
.ac_an_req_thread(ac_an_req_thread),
.ac_an_req_wimg_w(ac_an_req_wimg_w),
.ac_an_req_wimg_i(ac_an_req_wimg_i),
.ac_an_req_wimg_m(ac_an_req_wimg_m),
.ac_an_req_wimg_g(ac_an_req_wimg_g),
.ac_an_req_user_defined(ac_an_req_user_defined),
.ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0),
.ac_an_req_ld_core_tag(ac_an_req_ld_core_tag),
.ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len),
.ac_an_st_byte_enbl(ac_an_st_byte_enbl),
.ac_an_st_data(ac_an_st_data),
.ac_an_req_endian(ac_an_req_endian),
.ac_an_st_data_pwr_token(ac_an_st_data_pwr_token)
);

initial begin
$dumpfile ("wtf-coco.vcd");
// you can do it by levels and also by module so could prune down
$dumpvars;
// need to explicitly specify arrays for icarus
// guess not: $dumpvars cannot dump a vpiMemory
//$dumpvars(0, c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_data_q);
#1;
end

// see if coco lets me risingedge() these
wire clk_1x, clk_2x, clk_4x, rst;

assign clk_1x = nclk[0];
assign clk_2x = nclk[2];
assign clk_4x = nclk[3];
assign rst = nclk[1];

endmodule

@ -0,0 +1,310 @@
#!/bin/python3

# problems:
# some parse error causes it to ignore filters AND not let you add them (can be caused from gui); changing order
# of traces fixes it - maybe problem with my trans filter?

import sys
import os
import io
from dotmap import DotMap

from vcd.gtkw import *

gtkwFile = 'pyvcd.gtkw'
#fo = io.StringIO(gtkwFile)
fo = open(gtkwFile, 'w')
gtkw = GTKWSave(fo)

base = 'cocotb_icarus.'
topIndicator = '!' #wtf never need this?
vectorNoBits = False
core = 0

# add zero and one signals to top level for use here
zero = 'an_ac_sg_8'

filterPath = '../gtkwave/'
filterNull = filterPath + 'gtkf-nop.py'
filterValid = filterPath + 'gtkf-valid.py'
filterIBuf = filterPath + 'gtkf-ibuf.py'
filterPPC = filterPath + 'gtkf-ppc.py'
filterA2L2 = filterPath + 'gtkf-a2l2.py'
filterR64 = filterPath + 'gtkf-64R.py'

# need to indicate if signal is 'threaded' (vector) to gen diff netlists for diff smt modes


# showVector should maybe be done by Combined that can take specific bits to use
class Signal(DotMap):
def __init__(self, name, alias=None, color=None, highlight=False, rjustify=False, datafmt='bin', extraflags=GTKWFlag(0), translateFile=None, translateProc=None, transactionProc=None, bits=None, showVector=False):
super().__init__()
if name[0] != topIndicator:
name = base + name
else:
name = name[1:]
self.name = name
self.bits = bits
self.alias = alias
self.color = color
self.highlight = highlight
self.rjustify = rjustify
self.datafmt = datafmt
self.extraflags = extraflags
self.translateFile = translateFile
self.translateProc = translateProc
self.transactionProc = transactionProc
self.showVector = showVector

def add(self):
trace = self.name
bits = self.bits
if bits is not None:
if vectorNoBits:
trace = trace.split('[')[0]
if type(bits) is not list:
bits = [bits]
with gtkw.trace_bits(trace, showVector=self.showVector):
for i in range(len(bits)):
# for now - i guess highlight and filters might make sense
#gtkw.trace_bit(bits[i], trace, self.alias, self.color, self.datafmt, self.highlight, self.rjustify, self.extraflags, translate_filter_file=self.translateFile, translate_filter_proc=self.translateProc, transaction_filter_proc=self.transactionProc)
gtkw.trace_bit(bits[i], trace, self.alias, self.color)

else:
gtkw.trace(trace, self.alias, self.color, self.datafmt, self.highlight, self.rjustify, self.extraflags, translate_filter_file=self.translateFile, translate_filter_proc=self.translateProc, transaction_filter_proc=self.transactionProc)

class Combined(DotMap):
def __init__(self, name, traces, color=None, highlight=False, rjustify=False, datafmt='bin', extraflags=GTKWFlag(0), translateFile=None, translateProc=None, transactionProc=None):
super().__init__()
self.name = name
self.traces = traces
self.color = color
self.highlight = highlight
self.rjustify = rjustify
self.datafmt = datafmt
self.extraflags = extraflags
self.translateFile = translateFile
self.translateProc = translateProc
self.transactionProc = transactionProc

def add(self):
trace = []
for t in self.traces:
trace.append(t.name)
gtkw.trace(trace, self.name, self.color, self.datafmt, self.highlight, self.rjustify, self.extraflags, translate_filter_file=self.translateFile, translate_filter_proc=self.translateProc, transaction_filter_proc=self.transactionProc)

class Group(DotMap):
def __init__(self, name, traces, closed=True, highlight=False):
super().__init__()
self.name = name
self.traces = traces
self.closed = closed
self.highlight = highlight

def add(self):
if len(self.traces) > 0:
with gtkw.group(self.name, self.closed, self.highlight):
for j in range(len(self.traces)):
self.traces[j].add()

def addCombined(self, alias, color=None, highlight=False, rjustify=False, datafmt='bin', extraflags=GTKWFlag(0), translateFile=None, translateProc=None, transactionProc=None):
trace = []
for t in self.traces:
trace.append(t.name)
gtkw.trace(trace, alias, color, datafmt, highlight, rjustify, extraflags, translate_filter_file=translateFile, translate_filter_proc=translateProc, transaction_filter_proc=transactionProc)

nodeMisc = Group('Misc', [
Signal(f'nclk[0:5]', alias='reset', bits=1, showVector=False),
Signal(f'nclk[0:5]', alias='clk1x', bits=0, showVector=False),
Signal(f'nclk[0:5]', alias='clk2x', bits=2, showVector=False),
Signal(f'an_ac_pm_thread_stop[0]')
#Signal('ac_an_checkstop[0:2]'),
])
#nodeMisc.add()
# until gtkwave has a tiny nested indicator...
for i in range(len(nodeMisc.traces)):
nodeMisc.traces[i].add()

a2l2Req = Group('A2L2 Req', [
Signal(f'ac_an_req'),
Signal(f'ac_an_req_endian'),
Signal(f'ac_an_req_ld_core_tag[0:4]'),
Signal(f'ac_an_req_ld_xfr_len[0:2]'),
Signal(f'ac_an_req_pwr_token'),
Signal(f'ac_an_req_ra[22:63]'),
Signal(f'ac_an_req_ttype[0:5]'),
Signal(f'ac_an_req_wimg_w'),
Signal(f'ac_an_req_wimg_i'),
Signal(f'ac_an_req_wimg_m'),
Signal(f'ac_an_req_wimg_g')
])

a2l2Rsp = Group('A2L2 Rsp', [
Signal(f'an_ac_reld_data_coming'),
Signal(f'an_ac_reld_data_vld'),
Signal(f'an_ac_reld_qw[58:59]', datafmt='dec', rjustify=True),
Signal(f'an_ac_reld_crit_qw'),
Signal(f'an_ac_reld_data[0:127]', datafmt='hex')
])

a2l2Misc = Group('A2L2 Misc', [
Signal(f'ac_an_req_pwr_token'),
Signal(f'an_ac_req_ld_pop'),
Signal(f'c{core}.lq0.lsq.arb.load_cred_cnt_q[0:4]', datafmt='dec'),
Signal(f'an_ac_req_st_pop'),
Signal(f'an_ac_req_st_gather'),
Signal(f'c{core}.lq0.lsq.arb.store_cred_cnt_q[0:5]', datafmt='dec'),
Signal(f'an_ac_reservation_vld'),
Signal(f'an_ac_stcx_complete'),
Signal(f'an_ac_stcx_pass'),
Signal(f'an_ac_sync_ack'),
Signal(f'an_ac_icbi_ack')
])

ibuf = Group('IBuf', [
Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_valid_q[0:15]', datafmt='hex'),
Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_head_q[0:15]', datafmt='hex')
])
for i in range(16):
ibuf.traces.append(
Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[{i}].q[0:109]',translateProc=filterIBuf)
)

#ibuf2 = Combined(f'IBuf[{i}]',
# [
# (Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_valid_q[0:15]', bits=[{i}]),
# Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[{i}].q[0:109]')) for i in range(16)
# ]
#)


pipe = []

pipe.append(Combined('iu_xu_nia', [
Signal(f'c{core}.iuq0.iu_xu_t0_nia[0:61]'),
Signal(zero), # word-align
Signal(zero)
], datafmt='hex'))

pipe.append(ibuf)
#pipe.append(ibuf2)

for i in range(2):
pipe.append(Signal(f'c{core}.iu_rv_iu6_t0_i{i}_instr[0:31]', datafmt='hex', color=GTKWColor.green, translateProc=filterPPC))

# match cycle with instr
for i in range(2):
pipe.append(Combined(f'iu6_i{i}_itag_dispatched', [
Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_dispatched_d'),
Signal(zero), # pad missing bit 0
Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i{i}_itag[1:6]')
], color=GTKWColor.green, translateProc=filterValid))

#for i in range(2):
# pipe.append(Combined(f'iu6_i{i}_itag', [
# Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_valop_q'),
# Signal(zero), # pad missing bit 0
# Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_itag_q[1:6]')
# ], color=GTKWColor.blue, translateProc=filterValid))

for i in range(2):
pipe.append(Combined(f'iu6_i{i}_itag_dispatched', [
Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_dispatched_q'),
Signal(zero), # pad missing bit 0
Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_itag_q[1:6]')
], color=GTKWColor.green, translateProc=filterValid))

# eventually arrange all by ex
for ex in range(1):
for rv in range(2):
for fx in range(2):
for src in range(1,4):
pipe.append(Combined(f'rv0_fx{fx}_ex{ex}_s{src}', [
Signal(f'c{core}.rv_fx{fx}_ex{ex}_s{src}_v'),
Signal(f'c{core}.rv0.rf_byp.fx{fx}_ex{ex}_s{src}_itag_q[0:6]')
], color=GTKWColor.blue, translateProc=filterValid))

for ex in range(6):
for fx in range(2):
pipe.append(Combined(f'fx{fx}_ex{ex}', [
Signal(f'c{core}.xu0.xu{fx}.dec.ex{ex}_val_q[0]'),
Signal(f'c{core}.xu0.xu{fx}.dec.ex{ex}_itag_q[0:6]')
], color=GTKWColor.blue, translateProc=filterValid))

for ex in range(4):
pipe.append(Combined(f'br_ex{ex}_bta', [
Signal(f'c{core}.xu0.xu0.br.ex{ex}_bta_val_q'),
Signal(f'c{core}.xu0.xu0.br.ex{ex}_pred_bta_q[42:61]'),
Signal(zero), # word-align
Signal(zero)
], color=GTKWColor.blue, translateProc=filterValid))


for i in range(2):
pipe.append(Combined(f'cp2 i{i}_completed_itag', [
Signal(f'c{core}.iu_lq_i{i}_completed'),
Signal(f'c{core}.iu_lq_t0_i{i}_completed_itag[0:6]'),
], color=GTKWColor.green, translateProc=filterValid))

for i in range(2):
pipe.append(Combined(f'cp2 i{i}_completed_ifar', [
Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp2_i{i}_complete_q'),
Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i{i}_ifar[42:61]'),
Signal(zero), # word-align
Signal(zero)
], color=GTKWColor.green, translateProc=filterValid))

# or add more stuff and make transaction
for i in range(2):
pipe.append(Combined(f'cp2 i{i}_completed_itag/ifar', [
Signal(f'c{core}.iu_lq_i{i}_completed'),
Signal(zero), # pad itag
Signal(f'c{core}.iu_lq_t0_i{i}_completed_itag[0:6]'),
Signal(zero), # pad ifar
Signal(zero), # pad
Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i{i}_ifar[42:61]'),
Signal(zero), # word-align
Signal(zero)
], color=GTKWColor.green, translateProc=filterValid))


pipe = Group('Pipe', pipe, closed=False)


threads = 1
sprs = [None] * threads
for i in range(threads):
sprs[i] = Group(f't{i} SPR', [
Signal(f'c{core}.xu0.spr.threads.thread[{i}].xu_spr_tspr.srr0_do[0:64]', datafmt='bin', translateProc=filterR64),
Signal(f'c{core}.xu0.spr.threads.thread[{i}].xu_spr_tspr.srr1_do[0:64]', datafmt='bin', translateProc=filterR64)
], closed=False)

a2l2Req.add()
a2l2Rsp.add()
a2l2Misc.add()

# move this after and it works
#a2l2Req.addCombined('A2L2 Trans (Req)', transactionProc=filterA2L2)

pipe.add()
sprs[0].add()

a2l2Req.addCombined('A2L2 Trans (Req)', transactionProc=filterA2L2)

#for i in range(len(groups)):
# groups[i].add()


#gtkw.comment('Test pyvcd')
#gtkw.savefile(gtkwFile)
#gtkw.zoom_markers()
#gtkw.pos()

gtkw.sst_expanded(True)
gtkw.size(3000, 1500)
gtkw.treeopen(base)
gtkw.signals_width(600)
gtkw.pattern_trace(True)


fo.close()

@ -0,0 +1,255 @@
@800200
-
@28
+{reset} (1)cocotb_icarus.nclk[0:5]
@1001200
-group_end
@800200
-
@28
+{clk1x} (0)cocotb_icarus.nclk[0:5]
@1001200
-group_end
@800200
-
@28
+{clk2x} (2)cocotb_icarus.nclk[0:5]
@1001200
-group_end
@8
cocotb_icarus.an_ac_pm_thread_stop[0]
@c00200
-A2L2 Req
@8
cocotb_icarus.ac_an_req
cocotb_icarus.ac_an_req_endian
cocotb_icarus.ac_an_req_ld_core_tag[0:4]
cocotb_icarus.ac_an_req_ld_xfr_len[0:2]
cocotb_icarus.ac_an_req_pwr_token
cocotb_icarus.ac_an_req_ra[22:63]
cocotb_icarus.ac_an_req_ttype[0:5]
cocotb_icarus.ac_an_req_wimg_w
cocotb_icarus.ac_an_req_wimg_i
cocotb_icarus.ac_an_req_wimg_m
cocotb_icarus.ac_an_req_wimg_g
@1401200
-A2L2 Req
@c00200
-A2L2 Rsp
@8
cocotb_icarus.an_ac_reld_data_coming
cocotb_icarus.an_ac_reld_data_vld
@24
cocotb_icarus.an_ac_reld_qw[58:59]
@8
cocotb_icarus.an_ac_reld_crit_qw
@2
cocotb_icarus.an_ac_reld_data[0:127]
@1401200
-A2L2 Rsp
@c00200
-A2L2 Misc
@8
cocotb_icarus.ac_an_req_pwr_token
cocotb_icarus.an_ac_req_ld_pop
@4
cocotb_icarus.c0.lq0.lsq.arb.load_cred_cnt_q[0:4]
@8
cocotb_icarus.an_ac_req_st_pop
cocotb_icarus.an_ac_req_st_gather
@4
cocotb_icarus.c0.lq0.lsq.arb.store_cred_cnt_q[0:5]
@8
cocotb_icarus.an_ac_reservation_vld
cocotb_icarus.an_ac_stcx_complete
cocotb_icarus.an_ac_stcx_pass
cocotb_icarus.an_ac_sync_ack
cocotb_icarus.an_ac_icbi_ack
@1401200
-A2L2 Misc
@800200
-Pipe
@2
#{iu_xu_nia} (0)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (1)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (2)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (3)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (4)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (5)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (6)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (7)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (8)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (9)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (10)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (11)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (12)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (13)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (14)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (15)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (16)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (17)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (18)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (19)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (20)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (21)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (22)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (23)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (24)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (25)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (26)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (27)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (28)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (29)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (30)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (31)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (32)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (33)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (34)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (35)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (36)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (37)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (38)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (39)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (40)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (41)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (42)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (43)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (44)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (45)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (46)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (47)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (48)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (49)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (50)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (51)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (52)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (53)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (54)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (55)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (56)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (57)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (58)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (59)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (60)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (61)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8
@c00200
-IBuf
@2
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_valid_q[0:15]
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_head_q[0:15]
@4008
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[0].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[1].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[2].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[3].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[4].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[5].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[6].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[7].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[8].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[9].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[10].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[11].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[12].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[13].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[14].q[0:109]
^>1 ../gtkwave/gtkf-ibuf.py
cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[15].q[0:109]
@1401200
-IBuf
@4002
[color] 4
^>2 ../gtkwave/gtkf-ppc.py
cocotb_icarus.c0.iu_rv_iu6_t0_i0_instr[0:31]
[color] 4
^>2 ../gtkwave/gtkf-ppc.py
cocotb_icarus.c0.iu_rv_iu6_t0_i1_instr[0:31]
@4008
[color] 4
^>3 ../gtkwave/gtkf-valid.py
#{iu6_i0_itag_dispatched} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_dispatched_d cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6]
[color] 4
^>3 ../gtkwave/gtkf-valid.py
#{iu6_i1_itag_dispatched} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_dispatched_d cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6]
[color] 4
^>3 ../gtkwave/gtkf-valid.py
#{iu6_i0_itag_dispatched} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_dispatched_q cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6]
[color] 4
^>3 ../gtkwave/gtkf-valid.py
#{iu6_i1_itag_dispatched} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_dispatched_q cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{rv0_fx0_ex0_s1} cocotb_icarus.c0.rv_fx0_ex0_s1_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{rv0_fx0_ex0_s2} cocotb_icarus.c0.rv_fx0_ex0_s2_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{rv0_fx0_ex0_s3} cocotb_icarus.c0.rv_fx0_ex0_s3_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{rv0_fx1_ex0_s1} cocotb_icarus.c0.rv_fx1_ex0_s1_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{rv0_fx1_ex0_s2} cocotb_icarus.c0.rv_fx1_ex0_s2_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{rv0_fx1_ex0_s3} cocotb_icarus.c0.rv_fx1_ex0_s3_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{rv0_fx0_ex0_s1} cocotb_icarus.c0.rv_fx0_ex0_s1_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{rv0_fx0_ex0_s2} cocotb_icarus.c0.rv_fx0_ex0_s2_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{rv0_fx0_ex0_s3} cocotb_icarus.c0.rv_fx0_ex0_s3_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{rv0_fx1_ex0_s1} cocotb_icarus.c0.rv_fx1_ex0_s1_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{rv0_fx1_ex0_s2} cocotb_icarus.c0.rv_fx1_ex0_s2_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{rv0_fx1_ex0_s3} cocotb_icarus.c0.rv_fx1_ex0_s3_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{fx0_ex0} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex0_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{fx1_ex0} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex0_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{fx0_ex1} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex1_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{fx1_ex1} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex1_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{fx0_ex2} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex2_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{fx1_ex2} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex2_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{fx0_ex3} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex3_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{fx1_ex3} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex3_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{fx0_ex4} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex4_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{fx1_ex4} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex4_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{fx0_ex5} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex5_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{fx1_ex5} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex5_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6]
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{br_ex0_bta} cocotb_icarus.c0.xu0.xu0.br.ex0_bta_val_q (0)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (1)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (2)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (3)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (4)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (5)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (6)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (7)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (8)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (9)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (10)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (11)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (12)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (13)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (14)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (15)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (16)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (17)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (18)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (19)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{br_ex1_bta} cocotb_icarus.c0.xu0.xu0.br.ex1_bta_val_q (0)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (1)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (2)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (3)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (4)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (5)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (6)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (7)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (8)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (9)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (10)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (11)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (12)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (13)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (14)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (15)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (16)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (17)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (18)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (19)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{br_ex2_bta} cocotb_icarus.c0.xu0.xu0.br.ex2_bta_val_q (0)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (1)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (2)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (3)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (4)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (5)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (6)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (7)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (8)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (9)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (10)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (11)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (12)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (13)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (14)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (15)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (16)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (17)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (18)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (19)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8
[color] 5
^>3 ../gtkwave/gtkf-valid.py
#{br_ex3_bta} cocotb_icarus.c0.xu0.xu0.br.ex3_bta_val_q (0)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (1)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (2)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (3)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (4)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (5)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (6)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (7)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (8)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (9)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (10)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (11)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (12)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (13)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (14)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (15)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (16)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (17)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (18)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (19)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8
[color] 4
^>3 ../gtkwave/gtkf-valid.py
#{cp2 i0_completed_itag} cocotb_icarus.c0.iu_lq_i0_completed (0)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (1)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (2)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (3)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (4)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (5)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (6)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6]
[color] 4
^>3 ../gtkwave/gtkf-valid.py
#{cp2 i1_completed_itag} cocotb_icarus.c0.iu_lq_i1_completed (0)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (1)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (2)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (3)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (4)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (5)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (6)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6]
[color] 4
^>3 ../gtkwave/gtkf-valid.py
#{cp2 i0_completed_ifar} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp2_i0_complete_q (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (6)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (7)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (8)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (9)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (10)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (11)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (12)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (13)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (14)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (15)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (16)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (17)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (18)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (19)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8
[color] 4
^>3 ../gtkwave/gtkf-valid.py
#{cp2 i1_completed_ifar} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp2_i1_complete_q (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (6)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (7)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (8)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (9)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (10)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (11)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (12)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (13)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (14)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (15)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (16)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (17)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (18)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (19)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8
[color] 4
^>3 ../gtkwave/gtkf-valid.py
#{cp2 i0_completed_itag/ifar} cocotb_icarus.c0.iu_lq_i0_completed cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (1)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (2)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (3)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (4)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (5)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (6)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (6)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (7)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (8)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (9)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (10)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (11)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (12)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (13)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (14)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (15)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (16)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (17)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (18)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (19)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8
[color] 4
^>3 ../gtkwave/gtkf-valid.py
#{cp2 i1_completed_itag/ifar} cocotb_icarus.c0.iu_lq_i1_completed cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (1)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (2)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (3)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (4)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (5)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (6)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (6)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (7)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (8)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (9)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (10)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (11)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (12)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (13)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (14)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (15)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (16)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (17)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (18)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (19)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8
@1000200
-Pipe
@800200
-t0 SPR
@4008
^>4 ../gtkwave/gtkf-64R.py
cocotb_icarus.c0.xu0.spr.threads.thread[0].xu_spr_tspr.srr0_do[0:64]
^>4 ../gtkwave/gtkf-64R.py
cocotb_icarus.c0.xu0.spr.threads.thread[0].xu_spr_tspr.srr1_do[0:64]
@1000200
-t0 SPR
@10000008
^<1 ../gtkwave/gtkf-a2l2.py
#{A2L2 Trans (Req)} cocotb_icarus.ac_an_req cocotb_icarus.ac_an_req_endian (0)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (1)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (2)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (3)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (4)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (0)cocotb_icarus.ac_an_req_ld_xfr_len[0:2] (1)cocotb_icarus.ac_an_req_ld_xfr_len[0:2] (2)cocotb_icarus.ac_an_req_ld_xfr_len[0:2] cocotb_icarus.ac_an_req_pwr_token (0)cocotb_icarus.ac_an_req_ra[22:63] (1)cocotb_icarus.ac_an_req_ra[22:63] (2)cocotb_icarus.ac_an_req_ra[22:63] (3)cocotb_icarus.ac_an_req_ra[22:63] (4)cocotb_icarus.ac_an_req_ra[22:63] (5)cocotb_icarus.ac_an_req_ra[22:63] (6)cocotb_icarus.ac_an_req_ra[22:63] (7)cocotb_icarus.ac_an_req_ra[22:63] (8)cocotb_icarus.ac_an_req_ra[22:63] (9)cocotb_icarus.ac_an_req_ra[22:63] (10)cocotb_icarus.ac_an_req_ra[22:63] (11)cocotb_icarus.ac_an_req_ra[22:63] (12)cocotb_icarus.ac_an_req_ra[22:63] (13)cocotb_icarus.ac_an_req_ra[22:63] (14)cocotb_icarus.ac_an_req_ra[22:63] (15)cocotb_icarus.ac_an_req_ra[22:63] (16)cocotb_icarus.ac_an_req_ra[22:63] (17)cocotb_icarus.ac_an_req_ra[22:63] (18)cocotb_icarus.ac_an_req_ra[22:63] (19)cocotb_icarus.ac_an_req_ra[22:63] (20)cocotb_icarus.ac_an_req_ra[22:63] (21)cocotb_icarus.ac_an_req_ra[22:63] (22)cocotb_icarus.ac_an_req_ra[22:63] (23)cocotb_icarus.ac_an_req_ra[22:63] (24)cocotb_icarus.ac_an_req_ra[22:63] (25)cocotb_icarus.ac_an_req_ra[22:63] (26)cocotb_icarus.ac_an_req_ra[22:63] (27)cocotb_icarus.ac_an_req_ra[22:63] (28)cocotb_icarus.ac_an_req_ra[22:63] (29)cocotb_icarus.ac_an_req_ra[22:63] (30)cocotb_icarus.ac_an_req_ra[22:63] (31)cocotb_icarus.ac_an_req_ra[22:63] (32)cocotb_icarus.ac_an_req_ra[22:63] (33)cocotb_icarus.ac_an_req_ra[22:63] (34)cocotb_icarus.ac_an_req_ra[22:63] (35)cocotb_icarus.ac_an_req_ra[22:63] (36)cocotb_icarus.ac_an_req_ra[22:63] (37)cocotb_icarus.ac_an_req_ra[22:63] (38)cocotb_icarus.ac_an_req_ra[22:63] (39)cocotb_icarus.ac_an_req_ra[22:63] (40)cocotb_icarus.ac_an_req_ra[22:63] (41)cocotb_icarus.ac_an_req_ra[22:63] (0)cocotb_icarus.ac_an_req_ttype[0:5] (1)cocotb_icarus.ac_an_req_ttype[0:5] (2)cocotb_icarus.ac_an_req_ttype[0:5] (3)cocotb_icarus.ac_an_req_ttype[0:5] (4)cocotb_icarus.ac_an_req_ttype[0:5] (5)cocotb_icarus.ac_an_req_ttype[0:5] cocotb_icarus.ac_an_req_wimg_w cocotb_icarus.ac_an_req_wimg_i cocotb_icarus.ac_an_req_wimg_m cocotb_icarus.ac_an_req_wimg_g
[*] Test pyvcd
[sst_expanded] 1
[size] 3000 1500
[treeopen] cocotb_icarus.
[signals_width] 600
[pattern_trace] 1

@ -0,0 +1,8 @@
<testsuites name="results">
<testsuite name="all" package="all">
<property name="random_seed" value="1654605675" />
<testcase name="tb" classname="tb" file="/home/wtf/projects/a2o-opf/dev/sim/coco/tb.py" lineno="232" time="163.92313623428345" sim_time_ns="8177.000001" ratio_time="49.88313540629925">
<failure />
</testcase>
</testsuite>
</testsuites>

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After

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@ -0,0 +1,250 @@
// simple verilator top
/*
doesn't build on 4.106 (at least)
*/

#define TRACING

#include <cstddef>
#include <iostream>
#include <iomanip>

#include "verilated.h"
#include "Vc.h"

#ifdef TRACING
#include "verilated_vcd_c.h"
VerilatedVcdC *t;
#else
unsigned int t = 0;
#endif

/*
#include "uart/uartsim.h"
*/

Vc* m;

vluint64_t main_time = 0; // in units of timeprecision used in verilog or --timescale-override
// what is it? it changed to 941621251 after calling loadmem()

double sc_time_stamp() { // $time in verilog
return main_time;
}

const int resetCycle = 10;
const int threadRunCycle = 200;
const int runCycles = 1000;
const int hbCycles = 500;
const int threads = 1; // needs a more realistic a2l2 data return to work in smt

/*

143 # -------------------------------------------------------------------------------------------------
144 # enable smt2 and branch in different locs (driver returns b +64 if doesnt hit actual ops)
145 # 32b mode until msr[32]=1
146
147 0344 480000BC .align 8
147 60000000
147 60000000
147 60000000
147 60000000
148 boot_start:
149
150 0400 38200003 li r1,0x3
151 0404 7C366BA6 mtspr tens,r1 # 62:63 = tid 1:0 enabled
152 0408 7C3E6AA6 mfspr r1,tir # who am i?
*** appears to need an isync here! cr is not correct w/o it (old r1?)
153 040c 2C010000 cmpwi r1,0x00
154 0410 38202000 li r1,0x2000 # change to use 660 so stay in page 0
155 0414 41820008 beq t0
156 t1:
157 0418 5421103A slwi r1,r1,2 # change to addi so stay in page 0
158 t0:
160 041c 7C2903A6 mtctr r1
161 0420 4E800420 bctr # off to neverneverland


162 041c 7C2FCBA6 mtspr tar,r1
163 0420 4E800460 bctar 0x14,0,0

4C00012C isync


*/

int mem[1024]; // 4B*1K

void loadmem(void) {
int adr;
mem[0x0000/4] = 0x48000400;
adr = 0x400/4;

mem[adr++] = threads == 1 ? 0x38200001 : 0x38200003;
mem[adr++] = 0x7C366BA6;
mem[adr++] = 0x7C366BA6;
mem[adr++] = 0x7C3E6AA6;
mem[adr++] = 0x4C00012C;
mem[adr++] = 0x2C010000;
mem[adr++] = 0x38200660;
mem[adr++] = 0x41820008;
mem[adr++] = 0x38210100;
mem[adr++] = 0x7C2903A6;
mem[adr++] = 0x4E800420;

}

// nclk = (clk,reset,clk2x,clk4x,-,-)

int main(int argc, char **argv) {
using namespace std;

loadmem();

cout << setfill('0');

Verilated::commandArgs(argc, argv);
m = new Vc;

#ifdef TRACING
Verilated::traceEverOn(true);
t = new VerilatedVcdC;
m->trace(t, 99);
t->open("wtf.vcd");
cout << "Tracing enabled." << endl;
#endif

bool resetDone = false;
unsigned int threadStop = 0x3;

unsigned int tick = 0;
unsigned int cycle = 1;
unsigned int readPending = 0;
unsigned int readAddr = 0;
unsigned int readTag = 0;
unsigned int readTID = 0;
unsigned int countReads = 0;

m->nclk = 0x3C; // run 2x,4x = 1x
cout << setw(8) << cycle << "Resetting..." << endl;

m->an_ac_pm_thread_stop = threadStop;
cout << setw(8) << cycle << "Thread stop=" << threadStop << endl;

// can skip 4x with new gpr array
// 1x=4/4 2x=2/2 4x=1/1
// 1 1 1 7
// 1 1 0 6
// 1 0 1 5
// 1 0 0 4
// 0 1 1 3
// 0 1 0 2
// 0 0 1 1
// 0 0 0 0
// (insert reset)
//const int clocks[8] = {11, 0, 11, 0, 11, 0, 11, 0}; // 2x,4x == 1x
const int clocks[8] = {11, 10, 9, 8, 3, 2, 1, 0}; // 1x, 2x, 4x
const int ticks1x = 8;

while (!Verilated::gotFinish()) {

if (!resetDone && (cycle > resetCycle)) {
m->nclk &= 0x2F;
cout << setw(8) << cycle << "Releasing reset." << endl;
resetDone = true;
}

if (threadStop && (cycle > threadRunCycle)) {
threadStop = 0x0;
m->an_ac_pm_thread_stop = threadStop;
cout << setw(8) << cycle << "Thread stop=" << threadStop << endl;
}

m->nclk = (m->nclk & 0x10) | (clocks[tick % 8] << 2);
tick++;
m->eval();

// bus is 1x clock
if ((tick % ticks1x) == 0) {

if (readPending == cycle) { // i=1

m->an_ac_reld_data_vld = 1;
m->an_ac_reld_core_tag = readTag;
m->an_ac_reld_qw = 0;
m->an_ac_reld_crit_qw = 1;

if (readAddr == 0xFFFFFFF0) {

m->an_ac_reld_data[3]= 0x00000000; // 0
m->an_ac_reld_data[2]= 0x00000000; // 4
m->an_ac_reld_data[1]= 0x00000000; // 8
m->an_ac_reld_data[0]= 0x48000002; // C

} else if (readAddr < 0x0500) {

m->an_ac_reld_data[3]= mem[readAddr/4+0];
m->an_ac_reld_data[2]= mem[readAddr/4+1];
m->an_ac_reld_data[1]= mem[readAddr/4+2];
m->an_ac_reld_data[0]= mem[readAddr/4+3];

} else {

m->an_ac_reld_data[3]= 0x48000040;
m->an_ac_reld_data[2]= 0x00000000;
m->an_ac_reld_data[1]= 0x00000000;
m->an_ac_reld_data[0]= 0x00000000;

}
readPending = 0;
countReads++;
cout << setw(8) << cycle << " an_ac_rsp: data="<< hex << uppercase << setw(8) << m->an_ac_reld_data[3]
<< hex << uppercase << setw(8) << m->an_ac_reld_data[2]
<< hex << uppercase << setw(8) << m->an_ac_reld_data[1]
<< hex << uppercase << setw(8) << m->an_ac_reld_data[0]
<< dec << nouppercase << endl;
} else {
m->an_ac_reld_data_vld = 0;
}

m->an_ac_req_ld_pop = 0;
if (!readPending && m->ac_an_req) {
readAddr = m->ac_an_req_ra;
readTag = m->ac_an_req_ld_core_tag;
readTID = m->ac_an_req_thread;
readPending = cycle + 3;
cout << setw(8) << cycle << " ac_an_req: T" << readTID << " ra=" << hex << uppercase << setw(8) << readAddr << dec << nouppercase << endl;
m->an_ac_req_ld_pop = 1;
}

}

// finish clock stuff
if ((tick % ticks1x) == 0) {
cycle++;
if ((cycle % hbCycles) == 0) {
cout << setw(8) << cycle << " ...tick..." << endl;
}
}
#ifdef TRACING
t->dump(tick);
t->flush();
#endif

// check for fails

// hit limit
if (cycle > runCycles) {
break;
}

}

#ifdef TRACING
t->close();
#endif
m->final();

exit(EXIT_SUCCESS);

}

@ -0,0 +1,307 @@
# a2o test tb

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
from cocotb.triggers import FallingEdge
from cocotb.handle import Force
from cocotb.handle import Release

import itertools
from dotmap import DotMap

from OPEnv import *
from A2L2 import *

# ------------------------------------------------------------------------------------------------
# Tasks

# get rid of z on anything that will be sampled here
# is there a func to get all inputs?
async def init(dut, sim):
"""Initialize inputs. """

dut.nclk.value = 0
dut.scan_in.value = 0
dut.an_ac_scan_type_dc.value = 0x0
dut.an_ac_chipid_dc.value = 0x0
dut.an_ac_coreid.value = 0x0
dut.an_ac_scom_sat_id.value = 0x0

dut.an_ac_lbist_ary_wrt_thru_dc.value = 0
dut.an_ac_gsd_test_enable_dc.value = 0
dut.an_ac_gsd_test_acmode_dc.value = 0
dut.an_ac_ccflush_dc.value = 0
dut.an_ac_ccenable_dc.value = 0
dut.an_ac_lbist_en_dc.value = 0
dut.an_ac_lbist_ip_dc.value = 0
dut.an_ac_lbist_ac_mode_dc.value = 0
dut.an_ac_scan_diag_dc.value = 0
dut.an_ac_scan_dis_dc_b.value = 0

dut.an_ac_rtim_sl_thold_8.value = 0
dut.an_ac_func_sl_thold_8.value = 0
dut.an_ac_func_nsl_thold_8.value = 0
dut.an_ac_ary_nsl_thold_8.value = 0
dut.an_ac_sg_8.value = 0
dut.an_ac_fce_8.value = 0
dut.an_ac_abst_scan_in.value = 0

dut.an_ac_checkstop.value = 0

dut.an_ac_reset_1_complete.value = 0
dut.an_ac_reset_2_complete.value = 0
dut.an_ac_reset_3_complete.value = 0
dut.an_ac_reset_wd_complete.value = 0

dut.an_ac_pm_fetch_halt.value = 0
dut.an_ac_debug_stop.value = 0

dut.an_ac_tb_update_enable.value = 1
dut.an_ac_tb_update_pulse.value = 0 # tb clock if xucr0[tcs]=1 (must be <1/2 proc clk; tb pulse is 2x this clock)

# why is coco turning [0] into non-vector??? or is that gpi/vpi/icarus/???
if sim.threads == 1:
dut.an_ac_pm_thread_stop.value = 0x1
dut.an_ac_external_mchk.value = 0
dut.an_ac_sleep_en.value = 0
dut.an_ac_ext_interrupt.value = 0
dut.an_ac_crit_interrupt.value = 0
dut.an_ac_perf_interrupt.value = 0
dut.an_ac_hang_pulse.value = 0
dut.an_ac_uncond_dbg_event.value = 0
else:
for i in range(sim.threads):
dut.an_ac_pm_thread_stop[i].value = 0x1
dut.an_ac_external_mchk[i].value = 0
dut.an_ac_sleep_en[i].value = 0
dut.an_ac_ext_interrupt[i].value = 0
dut.an_ac_crit_interrupt[i].value = 0
dut.an_ac_perf_interrupt[i].value = 0
dut.an_ac_hang_pulse[i].value = 0
dut.an_ac_uncond_dbg_event[i].value = 0

await Timer(9, units='ns')

async def config(dut, sim):
"""Configure core, etc. """

#wtf make A2 module to do core-specific stuff
# A2L2 load/store credits
creditsLd = dut.c0.lq0.lsq.arb.load_cred_cnt_d # 8 max
creditsLdMax = dut.c0.lq0.lsq.arb.ld_cred_max # hdw check
creditsSt = dut.c0.lq0.lsq.arb.store_cred_cnt_d # 32 max
creditsStMax = dut.c0.lq0.lsq.arb.st_cred_max # hdw check
creditsLdStSingle = dut.c0.lq0.lsq.arb.spr_xucr0_cred_d.value # 1 total credit
#wtf this affects A2L2 - default=1
#creditsLdStSingle = dut.c0.lq0.lsq.arb.spr_lsucr0_b2b_q.value # 0=crit first, every other 1=crit first, b2b **the a2l2 spec does not say crit must be first**

await RisingEdge(dut.clk_1x)

if sim.config.core.creditsLd is not None:
creditsLd.value = Force(sim.config.core.creditsLd)
creditsLdMax.value = Force(sim.config.core.creditsLd)
sim.msg(f'A2L2: load credits changed from {creditsLd.value.integer} to {sim.config.core.creditsLd}.')
await RisingEdge(dut.clk_1x)
creditsLd.value = Release()

if sim.config.core.creditsSt is not None:
creditsSt.value = Force(sim.config.core.creditsSt)
creditsStMax.value = Force(sim.config.core.creditsSt)
sim.msg(f'A2L2: store credits changed from {creditsSt.value.integer} to {sim.config.core.creditsSt}.')
await RisingEdge(dut.clk_1x)
creditsSt.value = Release()

if sim.config.core.creditsLdStSingle:
creditsLdStSingle = Force(1)
sim.msg(f'A2L2: only one load OR store allowed when credits=1/1.')
await RisingEdge(dut.clk_1x)
creditsLdStSingle.value = Release()

await RisingEdge(dut.clk_1x)

async def coreMonitor(dut, sim):
"""Watch for core events. """

me = 'a2oMonitor'

# errors
creditsLdErr = dut.c0.lq0.lsq.arb.ld_cred_err_q
creditsStErr = dut.c0.lq0.lsq.arb.st_cred_err_q

# watches
iu0Comp = dut.c0.iu_lq_i0_completed
iu0CompIFAR = dut.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar
iu1Comp = dut.c0.iu_lq_i1_completed
iu1CompIFAR = dut.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar
iuCompFlushIFAR = dut.c0.cp_t0_flush_ifar
cp3NIA = dut.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp3_nia_q # nia after last cycle's completions

# queue depths, etc.

errors = [
{'name': 'Load Credits', 'sig': creditsLdErr},
{'name': 'Store Credits', 'sig': creditsStErr},
]

done = False

while not done:

await RisingEdge(dut.clk_1x)

for i in range(len(errors)):
assert errors[i]['sig'].value == 0, f'{me} Error: {errors[i]["name"]}'

comp = ''
if iu0Comp.value == 1:
comp = f'0:{int(iu0CompIFAR.value.binstr + "00", 2):06X} '

if iu1Comp.value == 1:
comp = f'{comp}1:{int(iu1CompIFAR.value.binstr + "00", 2):06X} '

if comp != '':
comp = f'{comp}{int(iuCompFlushIFAR.value.binstr + "00", 2):016X}'
sim.msg(f'C0: CP {comp}')


# trilib/tri.vh:`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5xClk
async def genReset(dut, sim):
"""Generate reset. """

first = True
done = False

while not done:
await RisingEdge(dut.clk_1x)
if sim.cycle < sim.resetCycle:
if first:
dut._log.info(f'[{sim.cycle:08d}] Resetting...')
first = False
dut.nclk[1].value = 1
elif not done:
dut._log.info(f'[{sim.cycle:08d}] Releasing reset.')
dut.nclk[1].value = 0
done = True

async def genClocks(dut, sim):
"""Generate 1x, 2x, 4x clock pulses, depending on parms. """

if sim.clk2x and sim.clk4x:
sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
await cocotb.start(sim.clk1x.start())
sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
await cocotb.start(sim.clk2x.start())
sim.clk4x = Clock(dut.nclk[3], 2, 'ns')
await cocotb.start(sim.clk4x.start())
elif sim.clk2x:
sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
await cocotb.start(sim.clk1x.start())
sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
await cocotb.start(sim.clk2x.start())
else:
sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
await cocotb.start(sim.clk1x.start())


for cycle in range(sim.maxCycles):

sim.cycle = cycle

if cycle % sim.hbCycles == 0:
dut._log.info(f'[{cycle:08d}] ...tick...')

await RisingEdge(dut.clk_1x)

dut._log.info(f'[{sim.cycle:08d}] Reached max cycle. Clocks stopped.')

# ------------------------------------------------------------------------------------------------
# Interfaces

# SCOM
async def scom(dut, sim):
"""scom interface"""

dut.an_ac_scom_dch.value = 0
dut.an_ac_scom_cch.value = 0


# ------------------------------------------------------------------------------------------------
# Do something

@cocotb.test()
async def tb(dut):
"""A Vulgar Display of OpenPower"""

sim = Sim(dut)
sim.mem = Memory(sim)
#sim.memFiles = ['../mem/boot_ieq1.bin.hex'] #wtf cmdline parm
sim.memFiles = ['../mem/boot.bin.hex'] #wtf cmdline parm

for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc.
sim.mem.loadFile(sim.memFiles[i])
if sim.resetAddr is not None and sim.mem.read(sim.resetAddr) == sim.mem.default:
sim.mem.write(sim.resetAddr, sim.resetOp)
sim.msg(f'Set reset fetch @{sim.resetAddr:08X} to {sim.resetOp:08X}.')

# dut.cocotb_icarus
# dut._log.info(sim.top.__dict__)
# {'_handle': <cocotb.simulator.gpi_sim_hdl at 0x55f8fa8a3aa0>,
# '_len': None, '_sub_handles': {}, '_invalid_sub_handles': set(), '_name': 'cocotb_icarus',
# '_type': 'GPI_MODULE', '_fullname': 'cocotb_icarus(GPI_MODULE)', '_path': 'cocotb_icarus.cocotb_icarus',
# '_log': <SimBaseLog cocotb.cocotb_icarus (INFO)>, '_def_name': 'cocotb_icarus', '_def_file': './cocotb_icarus.v',
# '_discovered': False
# }
# dut
# {'_handle': <cocotb.simulator.gpi_sim_hdl at 0x557757943540>,
# '_len': None, '_sub_handles': {'an_ac_pm_thread_stop': ModifiableObject(cocotb_icarus.an_ac_pm_thread_stop),
# 'cocotb_icarus': HierarchyObject(cocotb_icarus.cocotb_icarus with definition cocotb_icarus (at ./cocotb_icarus.v))},
# '_invalid_sub_handles': set(), '_name': 'cocotb_icarus', '_type': 'GPI_MODULE', '_fullname': 'cocotb_icarus(GPI_MODULE)',
# '_path': 'cocotb_icarus', '_log': <SimBaseLog cocotb.cocotb_icarus (INFO)>, '_def_name': '', '_def_file': '',
# '_discovered': False

# init stuff
await init(dut, sim)

# start clocks,reset
await cocotb.start(genClocks(dut, sim))
await cocotb.start(genReset(dut, sim))

# start interfaces
await cocotb.start(scom(dut, sim))

#wtf don't have to instantiate A2L2 first?
#await cocotb.start(A2L2Driver(dut, sim))
#await cocotb.start(A2L2Checker(dut, sim))
#await cocotb.start(A2L2Monitor(dut, sim))
await cocotb.start(A2L2.driver(dut, sim))
await cocotb.start(A2L2.checker(dut, sim))
await cocotb.start(A2L2.monitor(dut, sim))

await Timer((sim.resetCycle + 5)*8, units='ns')
if dut.nclk[1].value != 0:
sim.ok = False
sim.fail = 'Reset active too long!'

# config stuff
await config(dut, sim)

# monitor stuff
await cocotb.start(coreMonitor(dut, sim))

# release thread(s)
dut.an_ac_pm_thread_stop.value = 0
await RisingEdge(dut.clk_1x)
dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')



# should await sim.done
await Timer((sim.maxCycles+100)*8, units='ns')

if sim.ok:
dut._log.info(f'[{sim.cycle:08d}] You has opulence.')
else:
dut._log.info(f'[{sim.cycle:08d}] You are worthless and weak!')
assert False, f'[{sim.cycle:08d}] {sim.fail}'

@ -0,0 +1 @@
../../verilog

@ -0,0 +1,32 @@
#!/usr/bin/python3
# gtkwave process filter
#
# return left 64 of binary

import sys

fi = sys.stdin
fo = sys.stdout
fe = sys.stderr

def dbg(m):
fe.write(m + '\n')
fe.flush()

def main():

while True:

line = fi.readline()
if not line:
return 0

try:
fo.write(f'{int(line[0:32],2):08X}{int(line[32:65],2):08X}\n')
except:
fo.write('\n')

fo.flush()

if __name__ == '__main__':
sys.exit(main())

@ -0,0 +1,32 @@
#!/usr/bin/python3
# gtkwave process filter
#
# return right 64 of binary

import sys

fi = sys.stdin
fo = sys.stdout
fe = sys.stderr

def dbg(m):
fe.write(m + '\n')
fe.flush()

def main():

while True:

line = fi.readline()
if not line:
return 0

try:
fo.write(f'{int(line[-65:-33],2):08X}{int(line[-33:-1],2):08X}\n')
except:
fo.write('\n')

fo.flush()

if __name__ == '__main__':
sys.exit(main())

@ -0,0 +1,943 @@
#!/usr/bin/python3
# gtkwave transaction filter

# interpret a2l2 (req) interface
# needs:
# track multiple outstanding and out-of-order;
# update to show active tag list (credits), etc.
#
# select the signals; F4; name it; format->binary; format->transaction filter; select the signals and create group

import sys
import tempfile
import subprocess

fi = sys.stdin
fo = sys.stdout
fe = sys.stderr

debug = False

def dbg(m):
if debug:
fe.write(m + '\n')
fe.flush()

filterName = 'A2L2 Decode'
transColor = 'DarkRed'

colors = {
#'default':'DeepSkyBlue',
'default':'black',
'data':'DarkGray',
'bctr':'DarkOrange'
}

sigs = [None] * 30
sigNames = {
'ac_an_req' : None,
'ac_an_req_ra[22:63]' : 'RA',
'ac_an_req_thread[0:2]' : 'T',
'ac_an_req_ttype[0:5]' : 'TT',
'ac_an_req_tag[0:5]' : 'Tag',
'ac_an_req_wimg_w' : 'W',
'ac_an_req_wimg_i' : 'I',
'ac_an_req_wimg_m' : 'M',
'ac_an_req_wimg_g' : 'G',
}
sigTypes = {
'RA' : ('08X',),
'T': ('X',),
'TT' : ('02X',),
'Tag' : ('02X',),
'W' : ('nz', 'X'),
'I' : ('nz', 'X'),
'M' : ('nz', 'X'),
'G' : ('nz', 'X'),
}

trans = []
numTrans = 0

class Sig():
def __init__(self, name):
self.name = name
self.values = []
def addValue(self, t, v):
self.values.append((t,v))

class Trans():
def __init__(self):
self.timeReq = 0
self.timeDVal = 0
self.timeLast = 0
self.props = {}

# the last value of each sig is in this transaction (req=1)
def addTrans(time):
global numTrans
t = Trans()
t.timeReq = time
for i in range(len(sigs)):
if sigs[i] == None:
continue
t.props[sigs[i].name] = sigs[i].values[-1][1]
trans.append(t)
numTrans += 1

def main():

t = f'$name {filterName}\n'
t += '#0\n'

inDumpVars = False
startTrans = False
inTrans = False

while True:

l = fi.readline()
if not l:
return 0

dbg(l)

if l.startswith('#'): # time
if startTrans:
dbg('start trans\n')
addTrans(varTime)
startTrans = False
inTrans = True
varTime = int(l[1:-1])
elif inDumpVars:
if l.startswith('$comment data_end'):
inDumpVars = False
if inTrans:
addTrans(varTime)
inTrans = False
elif l.startswith('$'): # ?
pass
else: # value will be either 'vec num' or 'bn' (b=bit,n=num)
if ' ' in l: # vector
v = l.split()[0]
if 'x' in v or 'z' in v:
v = '0' # could mark it and check later
elif v[0] == 'b':
v = hex(int(v[1:], 2))
elif v[0] == 'x':
v = v[1:]
n = int(l.split()[1])
else: # bit
v = l[0]
n = int(l[1:])
sigs[n-1].addValue(varTime, v)
dbg(f'sig {n-1} {v}\n')
if sigs[n-1].name == 'ac_an_req':
dbg(f'transig: {n-1} {v}\n')
if v == '1':
startTrans = True
dbg('about to start trans\n')
elif sigs[n-1].name == 'an_ac_reld_data_vld':
if v == '1':
trans[-1].timeDVal = varTime
trans[-1].timeLast = varTime
inTrans = False
elif l.startswith('$var '):
tokens = l.split() # $var wire 3 2 ac_an_req_thread[0:2] $end 3=width 2=index
n = int(tokens[3]) - 1
sigs[n] = Sig(tokens[4])
elif l.startswith('$dumpvars'):
inDumpVars = True
else:
#t += '#' + str(i) + ' ' + l + '\n'
pass

if l.startswith('$comment data_end'):
# a transaction starts every req=1 cycle
t = ''
for i in range(len(trans)):
t += f'#{trans[i].timeReq} ?{transColor}?'
for p in trans[i].props:
if p in sigNames and sigNames[p] is not None:
n = sigNames[p]
if n in sigTypes and sigTypes[n][0] == 'nz':
if trans[i].props[p] == '1':
t += f'{n}:{int(trans[i].props[p], 16):{sigTypes[n][1]}} '
elif n in sigTypes:
dbg(f'{trans[i].props[p]}\n')
if n == 'T':
t += f'{n}{int(trans[i].props[p], 16):{sigTypes[n][0]}} '
elif n == 'TT' and trans[i].props[p] == '0x0':
t += 'IFETCH '
else:
t += f'{n}:{int(trans[i].props[p], 16):{sigTypes[n][0]}} '
else:
t += f'{n}:{trans[i].props[p]} '
t += '\n'
t += f'#{trans[i].timeLast}\n' # may need to wait till next cyc in case req on back-back?
t += '$finish\n'
fo.write(f'{t}')
fo.flush()


if __name__ == '__main__':
sys.exit(main())

'''
rgb.c from gtkwave

static struct wave_rgb_color colors[] = {
WAVE_RGB_COLOR("alice blue", 240, 248, 255),
WAVE_RGB_COLOR("AliceBlue", 240, 248, 255),
WAVE_RGB_COLOR("antique white", 250, 235, 215),
WAVE_RGB_COLOR("AntiqueWhite", 250, 235, 215),
WAVE_RGB_COLOR("AntiqueWhite1", 255, 239, 219),
WAVE_RGB_COLOR("AntiqueWhite2", 238, 223, 204),
WAVE_RGB_COLOR("AntiqueWhite3", 205, 192, 176),
WAVE_RGB_COLOR("AntiqueWhite4", 139, 131, 120),
WAVE_RGB_COLOR("aquamarine", 127, 255, 212),
WAVE_RGB_COLOR("aquamarine1", 127, 255, 212),
WAVE_RGB_COLOR("aquamarine2", 118, 238, 198),
WAVE_RGB_COLOR("aquamarine3", 102, 205, 170),
WAVE_RGB_COLOR("aquamarine4", 69, 139, 116),
WAVE_RGB_COLOR("azure", 240, 255, 255),
WAVE_RGB_COLOR("azure1", 240, 255, 255),
WAVE_RGB_COLOR("azure2", 224, 238, 238),
WAVE_RGB_COLOR("azure3", 193, 205, 205),
WAVE_RGB_COLOR("azure4", 131, 139, 139),
WAVE_RGB_COLOR("beige", 245, 245, 220),
WAVE_RGB_COLOR("bisque", 255, 228, 196),
WAVE_RGB_COLOR("bisque1", 255, 228, 196),
WAVE_RGB_COLOR("bisque2", 238, 213, 183),
WAVE_RGB_COLOR("bisque3", 205, 183, 158),
WAVE_RGB_COLOR("bisque4", 139, 125, 107),
WAVE_RGB_COLOR("black", 0, 0, 0),
WAVE_RGB_COLOR("blanched almond", 255, 235, 205),
WAVE_RGB_COLOR("BlanchedAlmond", 255, 235, 205),
WAVE_RGB_COLOR("blue", 0, 0, 255),
WAVE_RGB_COLOR("blue violet", 138, 43, 226),
WAVE_RGB_COLOR("blue1", 0, 0, 255),
WAVE_RGB_COLOR("blue2", 0, 0, 238),
WAVE_RGB_COLOR("blue3", 0, 0, 205),
WAVE_RGB_COLOR("blue4", 0, 0, 139),
WAVE_RGB_COLOR("BlueViolet", 138, 43, 226),
WAVE_RGB_COLOR("brown", 165, 42, 42),
WAVE_RGB_COLOR("brown1", 255, 64, 64),
WAVE_RGB_COLOR("brown2", 238, 59, 59),
WAVE_RGB_COLOR("brown3", 205, 51, 51),
WAVE_RGB_COLOR("brown4", 139, 35, 35),
WAVE_RGB_COLOR("burlywood", 222, 184, 135),
WAVE_RGB_COLOR("burlywood1", 255, 211, 155),
WAVE_RGB_COLOR("burlywood2", 238, 197, 145),
WAVE_RGB_COLOR("burlywood3", 205, 170, 125),
WAVE_RGB_COLOR("burlywood4", 139, 115, 85),
WAVE_RGB_COLOR("cadet blue", 95, 158, 160),
WAVE_RGB_COLOR("CadetBlue", 95, 158, 160),
WAVE_RGB_COLOR("CadetBlue1", 152, 245, 255),
WAVE_RGB_COLOR("CadetBlue2", 142, 229, 238),
WAVE_RGB_COLOR("CadetBlue3", 122, 197, 205),
WAVE_RGB_COLOR("CadetBlue4", 83, 134, 139),
WAVE_RGB_COLOR("chartreuse", 127, 255, 0),
WAVE_RGB_COLOR("chartreuse1", 127, 255, 0),
WAVE_RGB_COLOR("chartreuse2", 118, 238, 0),
WAVE_RGB_COLOR("chartreuse3", 102, 205, 0),
WAVE_RGB_COLOR("chartreuse4", 69, 139, 0),
WAVE_RGB_COLOR("chocolate", 210, 105, 30),
WAVE_RGB_COLOR("chocolate1", 255, 127, 36),
WAVE_RGB_COLOR("chocolate2", 238, 118, 33),
WAVE_RGB_COLOR("chocolate3", 205, 102, 29),
WAVE_RGB_COLOR("chocolate4", 139, 69, 19),
WAVE_RGB_COLOR("coral", 255, 127, 80),
WAVE_RGB_COLOR("coral1", 255, 114, 86),
WAVE_RGB_COLOR("coral2", 238, 106, 80),
WAVE_RGB_COLOR("coral3", 205, 91, 69),
WAVE_RGB_COLOR("coral4", 139, 62, 47),
WAVE_RGB_COLOR("cornflower blue", 100, 149, 237),
WAVE_RGB_COLOR("CornflowerBlue", 100, 149, 237),
WAVE_RGB_COLOR("cornsilk", 255, 248, 220),
WAVE_RGB_COLOR("cornsilk1", 255, 248, 220),
WAVE_RGB_COLOR("cornsilk2", 238, 232, 205),
WAVE_RGB_COLOR("cornsilk3", 205, 200, 177),
WAVE_RGB_COLOR("cornsilk4", 139, 136, 120),
WAVE_RGB_COLOR("cyan", 0, 255, 255),
WAVE_RGB_COLOR("cyan1", 0, 255, 255),
WAVE_RGB_COLOR("cyan2", 0, 238, 238),
WAVE_RGB_COLOR("cyan3", 0, 205, 205),
WAVE_RGB_COLOR("cyan4", 0, 139, 139),
WAVE_RGB_COLOR("dark blue", 0, 0, 139),
WAVE_RGB_COLOR("dark cyan", 0, 139, 139),
WAVE_RGB_COLOR("dark goldenrod", 184, 134, 11),
WAVE_RGB_COLOR("dark gray", 169, 169, 169),
WAVE_RGB_COLOR("dark green", 0, 100, 0),
WAVE_RGB_COLOR("dark grey", 169, 169, 169),
WAVE_RGB_COLOR("dark khaki", 189, 183, 107),
WAVE_RGB_COLOR("dark magenta", 139, 0, 139),
WAVE_RGB_COLOR("dark olive green", 85, 107, 47),
WAVE_RGB_COLOR("dark orange", 255, 140, 0),
WAVE_RGB_COLOR("dark orchid", 153, 50, 204),
WAVE_RGB_COLOR("dark red", 139, 0, 0),
WAVE_RGB_COLOR("dark salmon", 233, 150, 122),
WAVE_RGB_COLOR("dark sea green", 143, 188, 143),
WAVE_RGB_COLOR("dark slate blue", 72, 61, 139),
WAVE_RGB_COLOR("dark slate gray", 47, 79, 79),
WAVE_RGB_COLOR("dark slate grey", 47, 79, 79),
WAVE_RGB_COLOR("dark turquoise", 0, 206, 209),
WAVE_RGB_COLOR("dark violet", 148, 0, 211),
WAVE_RGB_COLOR("DarkBlue", 0, 0, 139),
WAVE_RGB_COLOR("DarkCyan", 0, 139, 139),
WAVE_RGB_COLOR("DarkGoldenrod", 184, 134, 11),
WAVE_RGB_COLOR("DarkGoldenrod1", 255, 185, 15),
WAVE_RGB_COLOR("DarkGoldenrod2", 238, 173, 14),
WAVE_RGB_COLOR("DarkGoldenrod3", 205, 149, 12),
WAVE_RGB_COLOR("DarkGoldenrod4", 139, 101, 8),
WAVE_RGB_COLOR("DarkGray", 169, 169, 169),
WAVE_RGB_COLOR("DarkGreen", 0, 100, 0),
WAVE_RGB_COLOR("DarkGrey", 169, 169, 169),
WAVE_RGB_COLOR("DarkKhaki", 189, 183, 107),
WAVE_RGB_COLOR("DarkMagenta", 139, 0, 139),
WAVE_RGB_COLOR("DarkOliveGreen", 85, 107, 47),
WAVE_RGB_COLOR("DarkOliveGreen1", 202, 255, 112),
WAVE_RGB_COLOR("DarkOliveGreen2", 188, 238, 104),
WAVE_RGB_COLOR("DarkOliveGreen3", 162, 205, 90),
WAVE_RGB_COLOR("DarkOliveGreen4", 110, 139, 61),
WAVE_RGB_COLOR("DarkOrange", 255, 140, 0),
WAVE_RGB_COLOR("DarkOrange1", 255, 127, 0),
WAVE_RGB_COLOR("DarkOrange2", 238, 118, 0),
WAVE_RGB_COLOR("DarkOrange3", 205, 102, 0),
WAVE_RGB_COLOR("DarkOrange4", 139, 69, 0),
WAVE_RGB_COLOR("DarkOrchid", 153, 50, 204),
WAVE_RGB_COLOR("DarkOrchid1", 191, 62, 255),
WAVE_RGB_COLOR("DarkOrchid2", 178, 58, 238),
WAVE_RGB_COLOR("DarkOrchid3", 154, 50, 205),
WAVE_RGB_COLOR("DarkOrchid4", 104, 34, 139),
WAVE_RGB_COLOR("DarkRed", 139, 0, 0),
WAVE_RGB_COLOR("DarkSalmon", 233, 150, 122),
WAVE_RGB_COLOR("DarkSeaGreen", 143, 188, 143),
WAVE_RGB_COLOR("DarkSeaGreen1", 193, 255, 193),
WAVE_RGB_COLOR("DarkSeaGreen2", 180, 238, 180),
WAVE_RGB_COLOR("DarkSeaGreen3", 155, 205, 155),
WAVE_RGB_COLOR("DarkSeaGreen4", 105, 139, 105),
WAVE_RGB_COLOR("DarkSlateBlue", 72, 61, 139),
WAVE_RGB_COLOR("DarkSlateGray", 47, 79, 79),
WAVE_RGB_COLOR("DarkSlateGray1", 151, 255, 255),
WAVE_RGB_COLOR("DarkSlateGray2", 141, 238, 238),
WAVE_RGB_COLOR("DarkSlateGray3", 121, 205, 205),
WAVE_RGB_COLOR("DarkSlateGray4", 82, 139, 139),
WAVE_RGB_COLOR("DarkSlateGrey", 47, 79, 79),
WAVE_RGB_COLOR("DarkTurquoise", 0, 206, 209),
WAVE_RGB_COLOR("DarkViolet", 148, 0, 211),
WAVE_RGB_COLOR("deep pink", 255, 20, 147),
WAVE_RGB_COLOR("deep sky blue", 0, 191, 255),
WAVE_RGB_COLOR("DeepPink", 255, 20, 147),
WAVE_RGB_COLOR("DeepPink1", 255, 20, 147),
WAVE_RGB_COLOR("DeepPink2", 238, 18, 137),
WAVE_RGB_COLOR("DeepPink3", 205, 16, 118),
WAVE_RGB_COLOR("DeepPink4", 139, 10, 80),
WAVE_RGB_COLOR("DeepSkyBlue", 0, 191, 255),
WAVE_RGB_COLOR("DeepSkyBlue1", 0, 191, 255),
WAVE_RGB_COLOR("DeepSkyBlue2", 0, 178, 238),
WAVE_RGB_COLOR("DeepSkyBlue3", 0, 154, 205),
WAVE_RGB_COLOR("DeepSkyBlue4", 0, 104, 139),
WAVE_RGB_COLOR("dim gray", 105, 105, 105),
WAVE_RGB_COLOR("dim grey", 105, 105, 105),
WAVE_RGB_COLOR("DimGray", 105, 105, 105),
WAVE_RGB_COLOR("DimGrey", 105, 105, 105),
WAVE_RGB_COLOR("dodger blue", 30, 144, 255),
WAVE_RGB_COLOR("DodgerBlue", 30, 144, 255),
WAVE_RGB_COLOR("DodgerBlue1", 30, 144, 255),
WAVE_RGB_COLOR("DodgerBlue2", 28, 134, 238),
WAVE_RGB_COLOR("DodgerBlue3", 24, 116, 205),
WAVE_RGB_COLOR("DodgerBlue4", 16, 78, 139),
WAVE_RGB_COLOR("firebrick", 178, 34, 34),
WAVE_RGB_COLOR("firebrick1", 255, 48, 48),
WAVE_RGB_COLOR("firebrick2", 238, 44, 44),
WAVE_RGB_COLOR("firebrick3", 205, 38, 38),
WAVE_RGB_COLOR("firebrick4", 139, 26, 26),
WAVE_RGB_COLOR("floral white", 255, 250, 240),
WAVE_RGB_COLOR("FloralWhite", 255, 250, 240),
WAVE_RGB_COLOR("forest green", 34, 139, 34),
WAVE_RGB_COLOR("ForestGreen", 34, 139, 34),
WAVE_RGB_COLOR("gainsboro", 220, 220, 220),
WAVE_RGB_COLOR("ghost white", 248, 248, 255),
WAVE_RGB_COLOR("GhostWhite", 248, 248, 255),
WAVE_RGB_COLOR("gold", 255, 215, 0),
WAVE_RGB_COLOR("gold1", 255, 215, 0),
WAVE_RGB_COLOR("gold2", 238, 201, 0),
WAVE_RGB_COLOR("gold3", 205, 173, 0),
WAVE_RGB_COLOR("gold4", 139, 117, 0),
WAVE_RGB_COLOR("goldenrod", 218, 165, 32),
WAVE_RGB_COLOR("goldenrod1", 255, 193, 37),
WAVE_RGB_COLOR("goldenrod2", 238, 180, 34),
WAVE_RGB_COLOR("goldenrod3", 205, 155, 29),
WAVE_RGB_COLOR("goldenrod4", 139, 105, 20),
WAVE_RGB_COLOR("gray", 190, 190, 190),
WAVE_RGB_COLOR("gray0", 0, 0, 0),
WAVE_RGB_COLOR("gray1", 3, 3, 3),
WAVE_RGB_COLOR("gray10", 26, 26, 26),
WAVE_RGB_COLOR("gray100", 255, 255, 255),
WAVE_RGB_COLOR("gray11", 28, 28, 28),
WAVE_RGB_COLOR("gray12", 31, 31, 31),
WAVE_RGB_COLOR("gray13", 33, 33, 33),
WAVE_RGB_COLOR("gray14", 36, 36, 36),
WAVE_RGB_COLOR("gray15", 38, 38, 38),
WAVE_RGB_COLOR("gray16", 41, 41, 41),
WAVE_RGB_COLOR("gray17", 43, 43, 43),
WAVE_RGB_COLOR("gray18", 46, 46, 46),
WAVE_RGB_COLOR("gray19", 48, 48, 48),
WAVE_RGB_COLOR("gray2", 5, 5, 5),
WAVE_RGB_COLOR("gray20", 51, 51, 51),
WAVE_RGB_COLOR("gray21", 54, 54, 54),
WAVE_RGB_COLOR("gray22", 56, 56, 56),
WAVE_RGB_COLOR("gray23", 59, 59, 59),
WAVE_RGB_COLOR("gray24", 61, 61, 61),
WAVE_RGB_COLOR("gray25", 64, 64, 64),
WAVE_RGB_COLOR("gray26", 66, 66, 66),
WAVE_RGB_COLOR("gray27", 69, 69, 69),
WAVE_RGB_COLOR("gray28", 71, 71, 71),
WAVE_RGB_COLOR("gray29", 74, 74, 74),
WAVE_RGB_COLOR("gray3", 8, 8, 8),
WAVE_RGB_COLOR("gray30", 77, 77, 77),
WAVE_RGB_COLOR("gray31", 79, 79, 79),
WAVE_RGB_COLOR("gray32", 82, 82, 82),
WAVE_RGB_COLOR("gray33", 84, 84, 84),
WAVE_RGB_COLOR("gray34", 87, 87, 87),
WAVE_RGB_COLOR("gray35", 89, 89, 89),
WAVE_RGB_COLOR("gray36", 92, 92, 92),
WAVE_RGB_COLOR("gray37", 94, 94, 94),
WAVE_RGB_COLOR("gray38", 97, 97, 97),
WAVE_RGB_COLOR("gray39", 99, 99, 99),
WAVE_RGB_COLOR("gray4", 10, 10, 10),
WAVE_RGB_COLOR("gray40", 102, 102, 102),
WAVE_RGB_COLOR("gray41", 105, 105, 105),
WAVE_RGB_COLOR("gray42", 107, 107, 107),
WAVE_RGB_COLOR("gray43", 110, 110, 110),
WAVE_RGB_COLOR("gray44", 112, 112, 112),
WAVE_RGB_COLOR("gray45", 115, 115, 115),
WAVE_RGB_COLOR("gray46", 117, 117, 117),
WAVE_RGB_COLOR("gray47", 120, 120, 120),
WAVE_RGB_COLOR("gray48", 122, 122, 122),
WAVE_RGB_COLOR("gray49", 125, 125, 125),
WAVE_RGB_COLOR("gray5", 13, 13, 13),
WAVE_RGB_COLOR("gray50", 127, 127, 127),
WAVE_RGB_COLOR("gray51", 130, 130, 130),
WAVE_RGB_COLOR("gray52", 133, 133, 133),
WAVE_RGB_COLOR("gray53", 135, 135, 135),
WAVE_RGB_COLOR("gray54", 138, 138, 138),
WAVE_RGB_COLOR("gray55", 140, 140, 140),
WAVE_RGB_COLOR("gray56", 143, 143, 143),
WAVE_RGB_COLOR("gray57", 145, 145, 145),
WAVE_RGB_COLOR("gray58", 148, 148, 148),
WAVE_RGB_COLOR("gray59", 150, 150, 150),
WAVE_RGB_COLOR("gray6", 15, 15, 15),
WAVE_RGB_COLOR("gray60", 153, 153, 153),
WAVE_RGB_COLOR("gray61", 156, 156, 156),
WAVE_RGB_COLOR("gray62", 158, 158, 158),
WAVE_RGB_COLOR("gray63", 161, 161, 161),
WAVE_RGB_COLOR("gray64", 163, 163, 163),
WAVE_RGB_COLOR("gray65", 166, 166, 166),
WAVE_RGB_COLOR("gray66", 168, 168, 168),
WAVE_RGB_COLOR("gray67", 171, 171, 171),
WAVE_RGB_COLOR("gray68", 173, 173, 173),
WAVE_RGB_COLOR("gray69", 176, 176, 176),
WAVE_RGB_COLOR("gray7", 18, 18, 18),
WAVE_RGB_COLOR("gray70", 179, 179, 179),
WAVE_RGB_COLOR("gray71", 181, 181, 181),
WAVE_RGB_COLOR("gray72", 184, 184, 184),
WAVE_RGB_COLOR("gray73", 186, 186, 186),
WAVE_RGB_COLOR("gray74", 189, 189, 189),
WAVE_RGB_COLOR("gray75", 191, 191, 191),
WAVE_RGB_COLOR("gray76", 194, 194, 194),
WAVE_RGB_COLOR("gray77", 196, 196, 196),
WAVE_RGB_COLOR("gray78", 199, 199, 199),
WAVE_RGB_COLOR("gray79", 201, 201, 201),
WAVE_RGB_COLOR("gray8", 20, 20, 20),
WAVE_RGB_COLOR("gray80", 204, 204, 204),
WAVE_RGB_COLOR("gray81", 207, 207, 207),
WAVE_RGB_COLOR("gray82", 209, 209, 209),
WAVE_RGB_COLOR("gray83", 212, 212, 212),
WAVE_RGB_COLOR("gray84", 214, 214, 214),
WAVE_RGB_COLOR("gray85", 217, 217, 217),
WAVE_RGB_COLOR("gray86", 219, 219, 219),
WAVE_RGB_COLOR("gray87", 222, 222, 222),
WAVE_RGB_COLOR("gray88", 224, 224, 224),
WAVE_RGB_COLOR("gray89", 227, 227, 227),
WAVE_RGB_COLOR("gray9", 23, 23, 23),
WAVE_RGB_COLOR("gray90", 229, 229, 229),
WAVE_RGB_COLOR("gray91", 232, 232, 232),
WAVE_RGB_COLOR("gray92", 235, 235, 235),
WAVE_RGB_COLOR("gray93", 237, 237, 237),
WAVE_RGB_COLOR("gray94", 240, 240, 240),
WAVE_RGB_COLOR("gray95", 242, 242, 242),
WAVE_RGB_COLOR("gray96", 245, 245, 245),
WAVE_RGB_COLOR("gray97", 247, 247, 247),
WAVE_RGB_COLOR("gray98", 250, 250, 250),
WAVE_RGB_COLOR("gray99", 252, 252, 252),
WAVE_RGB_COLOR("green", 0, 255, 0),
WAVE_RGB_COLOR("green yellow", 173, 255, 47),
WAVE_RGB_COLOR("green1", 0, 255, 0),
WAVE_RGB_COLOR("green2", 0, 238, 0),
WAVE_RGB_COLOR("green3", 0, 205, 0),
WAVE_RGB_COLOR("green4", 0, 139, 0),
WAVE_RGB_COLOR("GreenYellow", 173, 255, 47),
WAVE_RGB_COLOR("grey", 190, 190, 190),
WAVE_RGB_COLOR("grey0", 0, 0, 0),
WAVE_RGB_COLOR("grey1", 3, 3, 3),
WAVE_RGB_COLOR("grey10", 26, 26, 26),
WAVE_RGB_COLOR("grey100", 255, 255, 255),
WAVE_RGB_COLOR("grey11", 28, 28, 28),
WAVE_RGB_COLOR("grey12", 31, 31, 31),
WAVE_RGB_COLOR("grey13", 33, 33, 33),
WAVE_RGB_COLOR("grey14", 36, 36, 36),
WAVE_RGB_COLOR("grey15", 38, 38, 38),
WAVE_RGB_COLOR("grey16", 41, 41, 41),
WAVE_RGB_COLOR("grey17", 43, 43, 43),
WAVE_RGB_COLOR("grey18", 46, 46, 46),
WAVE_RGB_COLOR("grey19", 48, 48, 48),
WAVE_RGB_COLOR("grey2", 5, 5, 5),
WAVE_RGB_COLOR("grey20", 51, 51, 51),
WAVE_RGB_COLOR("grey21", 54, 54, 54),
WAVE_RGB_COLOR("grey22", 56, 56, 56),
WAVE_RGB_COLOR("grey23", 59, 59, 59),
WAVE_RGB_COLOR("grey24", 61, 61, 61),
WAVE_RGB_COLOR("grey25", 64, 64, 64),
WAVE_RGB_COLOR("grey26", 66, 66, 66),
WAVE_RGB_COLOR("grey27", 69, 69, 69),
WAVE_RGB_COLOR("grey28", 71, 71, 71),
WAVE_RGB_COLOR("grey29", 74, 74, 74),
WAVE_RGB_COLOR("grey3", 8, 8, 8),
WAVE_RGB_COLOR("grey30", 77, 77, 77),
WAVE_RGB_COLOR("grey31", 79, 79, 79),
WAVE_RGB_COLOR("grey32", 82, 82, 82),
WAVE_RGB_COLOR("grey33", 84, 84, 84),
WAVE_RGB_COLOR("grey34", 87, 87, 87),
WAVE_RGB_COLOR("grey35", 89, 89, 89),
WAVE_RGB_COLOR("grey36", 92, 92, 92),
WAVE_RGB_COLOR("grey37", 94, 94, 94),
WAVE_RGB_COLOR("grey38", 97, 97, 97),
WAVE_RGB_COLOR("grey39", 99, 99, 99),
WAVE_RGB_COLOR("grey4", 10, 10, 10),
WAVE_RGB_COLOR("grey40", 102, 102, 102),
WAVE_RGB_COLOR("grey41", 105, 105, 105),
WAVE_RGB_COLOR("grey42", 107, 107, 107),
WAVE_RGB_COLOR("grey43", 110, 110, 110),
WAVE_RGB_COLOR("grey44", 112, 112, 112),
WAVE_RGB_COLOR("grey45", 115, 115, 115),
WAVE_RGB_COLOR("grey46", 117, 117, 117),
WAVE_RGB_COLOR("grey47", 120, 120, 120),
WAVE_RGB_COLOR("grey48", 122, 122, 122),
WAVE_RGB_COLOR("grey49", 125, 125, 125),
WAVE_RGB_COLOR("grey5", 13, 13, 13),
WAVE_RGB_COLOR("grey50", 127, 127, 127),
WAVE_RGB_COLOR("grey51", 130, 130, 130),
WAVE_RGB_COLOR("grey52", 133, 133, 133),
WAVE_RGB_COLOR("grey53", 135, 135, 135),
WAVE_RGB_COLOR("grey54", 138, 138, 138),
WAVE_RGB_COLOR("grey55", 140, 140, 140),
WAVE_RGB_COLOR("grey56", 143, 143, 143),
WAVE_RGB_COLOR("grey57", 145, 145, 145),
WAVE_RGB_COLOR("grey58", 148, 148, 148),
WAVE_RGB_COLOR("grey59", 150, 150, 150),
WAVE_RGB_COLOR("grey6", 15, 15, 15),
WAVE_RGB_COLOR("grey60", 153, 153, 153),
WAVE_RGB_COLOR("grey61", 156, 156, 156),
WAVE_RGB_COLOR("grey62", 158, 158, 158),
WAVE_RGB_COLOR("grey63", 161, 161, 161),
WAVE_RGB_COLOR("grey64", 163, 163, 163),
WAVE_RGB_COLOR("grey65", 166, 166, 166),
WAVE_RGB_COLOR("grey66", 168, 168, 168),
WAVE_RGB_COLOR("grey67", 171, 171, 171),
WAVE_RGB_COLOR("grey68", 173, 173, 173),
WAVE_RGB_COLOR("grey69", 176, 176, 176),
WAVE_RGB_COLOR("grey7", 18, 18, 18),
WAVE_RGB_COLOR("grey70", 179, 179, 179),
WAVE_RGB_COLOR("grey71", 181, 181, 181),
WAVE_RGB_COLOR("grey72", 184, 184, 184),
WAVE_RGB_COLOR("grey73", 186, 186, 186),
WAVE_RGB_COLOR("grey74", 189, 189, 189),
WAVE_RGB_COLOR("grey75", 191, 191, 191),
WAVE_RGB_COLOR("grey76", 194, 194, 194),
WAVE_RGB_COLOR("grey77", 196, 196, 196),
WAVE_RGB_COLOR("grey78", 199, 199, 199),
WAVE_RGB_COLOR("grey79", 201, 201, 201),
WAVE_RGB_COLOR("grey8", 20, 20, 20),
WAVE_RGB_COLOR("grey80", 204, 204, 204),
WAVE_RGB_COLOR("grey81", 207, 207, 207),
WAVE_RGB_COLOR("grey82", 209, 209, 209),
WAVE_RGB_COLOR("grey83", 212, 212, 212),
WAVE_RGB_COLOR("grey84", 214, 214, 214),
WAVE_RGB_COLOR("grey85", 217, 217, 217),
WAVE_RGB_COLOR("grey86", 219, 219, 219),
WAVE_RGB_COLOR("grey87", 222, 222, 222),
WAVE_RGB_COLOR("grey88", 224, 224, 224),
WAVE_RGB_COLOR("grey89", 227, 227, 227),
WAVE_RGB_COLOR("grey9", 23, 23, 23),
WAVE_RGB_COLOR("grey90", 229, 229, 229),
WAVE_RGB_COLOR("grey91", 232, 232, 232),
WAVE_RGB_COLOR("grey92", 235, 235, 235),
WAVE_RGB_COLOR("grey93", 237, 237, 237),
WAVE_RGB_COLOR("grey94", 240, 240, 240),
WAVE_RGB_COLOR("grey95", 242, 242, 242),
WAVE_RGB_COLOR("grey96", 245, 245, 245),
WAVE_RGB_COLOR("grey97", 247, 247, 247),
WAVE_RGB_COLOR("grey98", 250, 250, 250),
WAVE_RGB_COLOR("grey99", 252, 252, 252),
WAVE_RGB_COLOR("honeydew", 240, 255, 240),
WAVE_RGB_COLOR("honeydew1", 240, 255, 240),
WAVE_RGB_COLOR("honeydew2", 224, 238, 224),
WAVE_RGB_COLOR("honeydew3", 193, 205, 193),
WAVE_RGB_COLOR("honeydew4", 131, 139, 131),
WAVE_RGB_COLOR("hot pink", 255, 105, 180),
WAVE_RGB_COLOR("HotPink", 255, 105, 180),
WAVE_RGB_COLOR("HotPink1", 255, 110, 180),
WAVE_RGB_COLOR("HotPink2", 238, 106, 167),
WAVE_RGB_COLOR("HotPink3", 205, 96, 144),
WAVE_RGB_COLOR("HotPink4", 139, 58, 98),
WAVE_RGB_COLOR("indian red", 205, 92, 92),
WAVE_RGB_COLOR("IndianRed", 205, 92, 92),
WAVE_RGB_COLOR("IndianRed1", 255, 106, 106),
WAVE_RGB_COLOR("IndianRed2", 238, 99, 99),
WAVE_RGB_COLOR("IndianRed3", 205, 85, 85),
WAVE_RGB_COLOR("IndianRed4", 139, 58, 58),
WAVE_RGB_COLOR("ivory", 255, 255, 240),
WAVE_RGB_COLOR("ivory1", 255, 255, 240),
WAVE_RGB_COLOR("ivory2", 238, 238, 224),
WAVE_RGB_COLOR("ivory3", 205, 205, 193),
WAVE_RGB_COLOR("ivory4", 139, 139, 131),
WAVE_RGB_COLOR("khaki", 240, 230, 140),
WAVE_RGB_COLOR("khaki1", 255, 246, 143),
WAVE_RGB_COLOR("khaki2", 238, 230, 133),
WAVE_RGB_COLOR("khaki3", 205, 198, 115),
WAVE_RGB_COLOR("khaki4", 139, 134, 78),
WAVE_RGB_COLOR("lavender", 230, 230, 250),
WAVE_RGB_COLOR("lavender blush", 255, 240, 245),
WAVE_RGB_COLOR("LavenderBlush", 255, 240, 245),
WAVE_RGB_COLOR("LavenderBlush1", 255, 240, 245),
WAVE_RGB_COLOR("LavenderBlush2", 238, 224, 229),
WAVE_RGB_COLOR("LavenderBlush3", 205, 193, 197),
WAVE_RGB_COLOR("LavenderBlush4", 139, 131, 134),
WAVE_RGB_COLOR("lawn green", 124, 252, 0),
WAVE_RGB_COLOR("LawnGreen", 124, 252, 0),
WAVE_RGB_COLOR("lemon chiffon", 255, 250, 205),
WAVE_RGB_COLOR("LemonChiffon", 255, 250, 205),
WAVE_RGB_COLOR("LemonChiffon1", 255, 250, 205),
WAVE_RGB_COLOR("LemonChiffon2", 238, 233, 191),
WAVE_RGB_COLOR("LemonChiffon3", 205, 201, 165),
WAVE_RGB_COLOR("LemonChiffon4", 139, 137, 112),
WAVE_RGB_COLOR("light blue", 173, 216, 230),
WAVE_RGB_COLOR("light coral", 240, 128, 128),
WAVE_RGB_COLOR("light cyan", 224, 255, 255),
WAVE_RGB_COLOR("light goldenrod", 238, 221, 130),
WAVE_RGB_COLOR("light goldenrod yellow", 250, 250, 210),
WAVE_RGB_COLOR("light gray", 211, 211, 211),
WAVE_RGB_COLOR("light green", 144, 238, 144),
WAVE_RGB_COLOR("light grey", 211, 211, 211),
WAVE_RGB_COLOR("light pink", 255, 182, 193),
WAVE_RGB_COLOR("light salmon", 255, 160, 122),
WAVE_RGB_COLOR("light sea green", 32, 178, 170),
WAVE_RGB_COLOR("light sky blue", 135, 206, 250),
WAVE_RGB_COLOR("light slate blue", 132, 112, 255),
WAVE_RGB_COLOR("light slate gray", 119, 136, 153),
WAVE_RGB_COLOR("light slate grey", 119, 136, 153),
WAVE_RGB_COLOR("light steel blue", 176, 196, 222),
WAVE_RGB_COLOR("light yellow", 255, 255, 224),
WAVE_RGB_COLOR("LightBlue", 173, 216, 230),
WAVE_RGB_COLOR("LightBlue1", 191, 239, 255),
WAVE_RGB_COLOR("LightBlue2", 178, 223, 238),
WAVE_RGB_COLOR("LightBlue3", 154, 192, 205),
WAVE_RGB_COLOR("LightBlue4", 104, 131, 139),
WAVE_RGB_COLOR("LightCoral", 240, 128, 128),
WAVE_RGB_COLOR("LightCyan", 224, 255, 255),
WAVE_RGB_COLOR("LightCyan1", 224, 255, 255),
WAVE_RGB_COLOR("LightCyan2", 209, 238, 238),
WAVE_RGB_COLOR("LightCyan3", 180, 205, 205),
WAVE_RGB_COLOR("LightCyan4", 122, 139, 139),
WAVE_RGB_COLOR("LightGoldenrod", 238, 221, 130),
WAVE_RGB_COLOR("LightGoldenrod1", 255, 236, 139),
WAVE_RGB_COLOR("LightGoldenrod2", 238, 220, 130),
WAVE_RGB_COLOR("LightGoldenrod3", 205, 190, 112),
WAVE_RGB_COLOR("LightGoldenrod4", 139, 129, 76),
WAVE_RGB_COLOR("LightGoldenrodYellow", 250, 250, 210),
WAVE_RGB_COLOR("LightGray", 211, 211, 211),
WAVE_RGB_COLOR("LightGreen", 144, 238, 144),
WAVE_RGB_COLOR("LightGrey", 211, 211, 211),
WAVE_RGB_COLOR("LightPink", 255, 182, 193),
WAVE_RGB_COLOR("LightPink1", 255, 174, 185),
WAVE_RGB_COLOR("LightPink2", 238, 162, 173),
WAVE_RGB_COLOR("LightPink3", 205, 140, 149),
WAVE_RGB_COLOR("LightPink4", 139, 95, 101),
WAVE_RGB_COLOR("LightSalmon", 255, 160, 122),
WAVE_RGB_COLOR("LightSalmon1", 255, 160, 122),
WAVE_RGB_COLOR("LightSalmon2", 238, 149, 114),
WAVE_RGB_COLOR("LightSalmon3", 205, 129, 98),
WAVE_RGB_COLOR("LightSalmon4", 139, 87, 66),
WAVE_RGB_COLOR("LightSeaGreen", 32, 178, 170),
WAVE_RGB_COLOR("LightSkyBlue", 135, 206, 250),
WAVE_RGB_COLOR("LightSkyBlue1", 176, 226, 255),
WAVE_RGB_COLOR("LightSkyBlue2", 164, 211, 238),
WAVE_RGB_COLOR("LightSkyBlue3", 141, 182, 205),
WAVE_RGB_COLOR("LightSkyBlue4", 96, 123, 139),
WAVE_RGB_COLOR("LightSlateBlue", 132, 112, 255),
WAVE_RGB_COLOR("LightSlateGray", 119, 136, 153),
WAVE_RGB_COLOR("LightSlateGrey", 119, 136, 153),
WAVE_RGB_COLOR("LightSteelBlue", 176, 196, 222),
WAVE_RGB_COLOR("LightSteelBlue1", 202, 225, 255),
WAVE_RGB_COLOR("LightSteelBlue2", 188, 210, 238),
WAVE_RGB_COLOR("LightSteelBlue3", 162, 181, 205),
WAVE_RGB_COLOR("LightSteelBlue4", 110, 123, 139),
WAVE_RGB_COLOR("LightYellow", 255, 255, 224),
WAVE_RGB_COLOR("LightYellow1", 255, 255, 224),
WAVE_RGB_COLOR("LightYellow2", 238, 238, 209),
WAVE_RGB_COLOR("LightYellow3", 205, 205, 180),
WAVE_RGB_COLOR("LightYellow4", 139, 139, 122),
WAVE_RGB_COLOR("lime green", 50, 205, 50),
WAVE_RGB_COLOR("LimeGreen", 50, 205, 50),
WAVE_RGB_COLOR("linen", 250, 240, 230),
WAVE_RGB_COLOR("magenta", 255, 0, 255),
WAVE_RGB_COLOR("magenta1", 255, 0, 255),
WAVE_RGB_COLOR("magenta2", 238, 0, 238),
WAVE_RGB_COLOR("magenta3", 205, 0, 205),
WAVE_RGB_COLOR("magenta4", 139, 0, 139),
WAVE_RGB_COLOR("maroon", 176, 48, 96),
WAVE_RGB_COLOR("maroon1", 255, 52, 179),
WAVE_RGB_COLOR("maroon2", 238, 48, 167),
WAVE_RGB_COLOR("maroon3", 205, 41, 144),
WAVE_RGB_COLOR("maroon4", 139, 28, 98),
WAVE_RGB_COLOR("medium aquamarine", 102, 205, 170),
WAVE_RGB_COLOR("medium blue", 0, 0, 205),
WAVE_RGB_COLOR("medium orchid", 186, 85, 211),
WAVE_RGB_COLOR("medium purple", 147, 112, 219),
WAVE_RGB_COLOR("medium sea green", 60, 179, 113),
WAVE_RGB_COLOR("medium slate blue", 123, 104, 238),
WAVE_RGB_COLOR("medium spring green", 0, 250, 154),
WAVE_RGB_COLOR("medium turquoise", 72, 209, 204),
WAVE_RGB_COLOR("medium violet red", 199, 21, 133),
WAVE_RGB_COLOR("MediumAquamarine", 102, 205, 170),
WAVE_RGB_COLOR("MediumBlue", 0, 0, 205),
WAVE_RGB_COLOR("MediumOrchid", 186, 85, 211),
WAVE_RGB_COLOR("MediumOrchid1", 224, 102, 255),
WAVE_RGB_COLOR("MediumOrchid2", 209, 95, 238),
WAVE_RGB_COLOR("MediumOrchid3", 180, 82, 205),
WAVE_RGB_COLOR("MediumOrchid4", 122, 55, 139),
WAVE_RGB_COLOR("MediumPurple", 147, 112, 219),
WAVE_RGB_COLOR("MediumPurple1", 171, 130, 255),
WAVE_RGB_COLOR("MediumPurple2", 159, 121, 238),
WAVE_RGB_COLOR("MediumPurple3", 137, 104, 205),
WAVE_RGB_COLOR("MediumPurple4", 93, 71, 139),
WAVE_RGB_COLOR("MediumSeaGreen", 60, 179, 113),
WAVE_RGB_COLOR("MediumSlateBlue", 123, 104, 238),
WAVE_RGB_COLOR("MediumSpringGreen", 0, 250, 154),
WAVE_RGB_COLOR("MediumTurquoise", 72, 209, 204),
WAVE_RGB_COLOR("MediumVioletRed", 199, 21, 133),
WAVE_RGB_COLOR("midnight blue", 25, 25, 112),
WAVE_RGB_COLOR("MidnightBlue", 25, 25, 112),
WAVE_RGB_COLOR("mint cream", 245, 255, 250),
WAVE_RGB_COLOR("MintCream", 245, 255, 250),
WAVE_RGB_COLOR("misty rose", 255, 228, 225),
WAVE_RGB_COLOR("MistyRose", 255, 228, 225),
WAVE_RGB_COLOR("MistyRose1", 255, 228, 225),
WAVE_RGB_COLOR("MistyRose2", 238, 213, 210),
WAVE_RGB_COLOR("MistyRose3", 205, 183, 181),
WAVE_RGB_COLOR("MistyRose4", 139, 125, 123),
WAVE_RGB_COLOR("moccasin", 255, 228, 181),
WAVE_RGB_COLOR("navajo white", 255, 222, 173),
WAVE_RGB_COLOR("NavajoWhite", 255, 222, 173),
WAVE_RGB_COLOR("NavajoWhite1", 255, 222, 173),
WAVE_RGB_COLOR("NavajoWhite2", 238, 207, 161),
WAVE_RGB_COLOR("NavajoWhite3", 205, 179, 139),
WAVE_RGB_COLOR("NavajoWhite4", 139, 121, 94),
WAVE_RGB_COLOR("navy", 0, 0, 128),
WAVE_RGB_COLOR("navy blue", 0, 0, 128),
WAVE_RGB_COLOR("NavyBlue", 0, 0, 128),
WAVE_RGB_COLOR("old lace", 253, 245, 230),
WAVE_RGB_COLOR("OldLace", 253, 245, 230),
WAVE_RGB_COLOR("olive drab", 107, 142, 35),
WAVE_RGB_COLOR("OliveDrab", 107, 142, 35),
WAVE_RGB_COLOR("OliveDrab1", 192, 255, 62),
WAVE_RGB_COLOR("OliveDrab2", 179, 238, 58),
WAVE_RGB_COLOR("OliveDrab3", 154, 205, 50),
WAVE_RGB_COLOR("OliveDrab4", 105, 139, 34),
WAVE_RGB_COLOR("orange", 255, 165, 0),
WAVE_RGB_COLOR("orange red", 255, 69, 0),
WAVE_RGB_COLOR("orange1", 255, 165, 0),
WAVE_RGB_COLOR("orange2", 238, 154, 0),
WAVE_RGB_COLOR("orange3", 205, 133, 0),
WAVE_RGB_COLOR("orange4", 139, 90, 0),
WAVE_RGB_COLOR("OrangeRed", 255, 69, 0),
WAVE_RGB_COLOR("OrangeRed1", 255, 69, 0),
WAVE_RGB_COLOR("OrangeRed2", 238, 64, 0),
WAVE_RGB_COLOR("OrangeRed3", 205, 55, 0),
WAVE_RGB_COLOR("OrangeRed4", 139, 37, 0),
WAVE_RGB_COLOR("orchid", 218, 112, 214),
WAVE_RGB_COLOR("orchid1", 255, 131, 250),
WAVE_RGB_COLOR("orchid2", 238, 122, 233),
WAVE_RGB_COLOR("orchid3", 205, 105, 201),
WAVE_RGB_COLOR("orchid4", 139, 71, 137),
WAVE_RGB_COLOR("pale goldenrod", 238, 232, 170),
WAVE_RGB_COLOR("pale green", 152, 251, 152),
WAVE_RGB_COLOR("pale turquoise", 175, 238, 238),
WAVE_RGB_COLOR("pale violet red", 219, 112, 147),
WAVE_RGB_COLOR("PaleGoldenrod", 238, 232, 170),
WAVE_RGB_COLOR("PaleGreen", 152, 251, 152),
WAVE_RGB_COLOR("PaleGreen1", 154, 255, 154),
WAVE_RGB_COLOR("PaleGreen2", 144, 238, 144),
WAVE_RGB_COLOR("PaleGreen3", 124, 205, 124),
WAVE_RGB_COLOR("PaleGreen4", 84, 139, 84),
WAVE_RGB_COLOR("PaleTurquoise", 175, 238, 238),
WAVE_RGB_COLOR("PaleTurquoise1", 187, 255, 255),
WAVE_RGB_COLOR("PaleTurquoise2", 174, 238, 238),
WAVE_RGB_COLOR("PaleTurquoise3", 150, 205, 205),
WAVE_RGB_COLOR("PaleTurquoise4", 102, 139, 139),
WAVE_RGB_COLOR("PaleVioletRed", 219, 112, 147),
WAVE_RGB_COLOR("PaleVioletRed1", 255, 130, 171),
WAVE_RGB_COLOR("PaleVioletRed2", 238, 121, 159),
WAVE_RGB_COLOR("PaleVioletRed3", 205, 104, 137),
WAVE_RGB_COLOR("PaleVioletRed4", 139, 71, 93),
WAVE_RGB_COLOR("papaya whip", 255, 239, 213),
WAVE_RGB_COLOR("PapayaWhip", 255, 239, 213),
WAVE_RGB_COLOR("peach puff", 255, 218, 185),
WAVE_RGB_COLOR("PeachPuff", 255, 218, 185),
WAVE_RGB_COLOR("PeachPuff1", 255, 218, 185),
WAVE_RGB_COLOR("PeachPuff2", 238, 203, 173),
WAVE_RGB_COLOR("PeachPuff3", 205, 175, 149),
WAVE_RGB_COLOR("PeachPuff4", 139, 119, 101),
WAVE_RGB_COLOR("peru", 205, 133, 63),
WAVE_RGB_COLOR("pink", 255, 192, 203),
WAVE_RGB_COLOR("pink1", 255, 181, 197),
WAVE_RGB_COLOR("pink2", 238, 169, 184),
WAVE_RGB_COLOR("pink3", 205, 145, 158),
WAVE_RGB_COLOR("pink4", 139, 99, 108),
WAVE_RGB_COLOR("plum", 221, 160, 221),
WAVE_RGB_COLOR("plum1", 255, 187, 255),
WAVE_RGB_COLOR("plum2", 238, 174, 238),
WAVE_RGB_COLOR("plum3", 205, 150, 205),
WAVE_RGB_COLOR("plum4", 139, 102, 139),
WAVE_RGB_COLOR("powder blue", 176, 224, 230),
WAVE_RGB_COLOR("PowderBlue", 176, 224, 230),
WAVE_RGB_COLOR("purple", 160, 32, 240),
WAVE_RGB_COLOR("purple1", 155, 48, 255),
WAVE_RGB_COLOR("purple2", 145, 44, 238),
WAVE_RGB_COLOR("purple3", 125, 38, 205),
WAVE_RGB_COLOR("purple4", 85, 26, 139),
WAVE_RGB_COLOR("red", 255, 0, 0),
WAVE_RGB_COLOR("red1", 255, 0, 0),
WAVE_RGB_COLOR("red2", 238, 0, 0),
WAVE_RGB_COLOR("red3", 205, 0, 0),
WAVE_RGB_COLOR("red4", 139, 0, 0),
WAVE_RGB_COLOR("rosy brown", 188, 143, 143),
WAVE_RGB_COLOR("RosyBrown", 188, 143, 143),
WAVE_RGB_COLOR("RosyBrown1", 255, 193, 193),
WAVE_RGB_COLOR("RosyBrown2", 238, 180, 180),
WAVE_RGB_COLOR("RosyBrown3", 205, 155, 155),
WAVE_RGB_COLOR("RosyBrown4", 139, 105, 105),
WAVE_RGB_COLOR("royal blue", 65, 105, 225),
WAVE_RGB_COLOR("RoyalBlue", 65, 105, 225),
WAVE_RGB_COLOR("RoyalBlue1", 72, 118, 255),
WAVE_RGB_COLOR("RoyalBlue2", 67, 110, 238),
WAVE_RGB_COLOR("RoyalBlue3", 58, 95, 205),
WAVE_RGB_COLOR("RoyalBlue4", 39, 64, 139),
WAVE_RGB_COLOR("saddle brown", 139, 69, 19),
WAVE_RGB_COLOR("SaddleBrown", 139, 69, 19),
WAVE_RGB_COLOR("salmon", 250, 128, 114),
WAVE_RGB_COLOR("salmon1", 255, 140, 105),
WAVE_RGB_COLOR("salmon2", 238, 130, 98),
WAVE_RGB_COLOR("salmon3", 205, 112, 84),
WAVE_RGB_COLOR("salmon4", 139, 76, 57),
WAVE_RGB_COLOR("sandy brown", 244, 164, 96),
WAVE_RGB_COLOR("SandyBrown", 244, 164, 96),
WAVE_RGB_COLOR("sea green", 46, 139, 87),
WAVE_RGB_COLOR("SeaGreen", 46, 139, 87),
WAVE_RGB_COLOR("SeaGreen1", 84, 255, 159),
WAVE_RGB_COLOR("SeaGreen2", 78, 238, 148),
WAVE_RGB_COLOR("SeaGreen3", 67, 205, 128),
WAVE_RGB_COLOR("SeaGreen4", 46, 139, 87),
WAVE_RGB_COLOR("seashell", 255, 245, 238),
WAVE_RGB_COLOR("seashell1", 255, 245, 238),
WAVE_RGB_COLOR("seashell2", 238, 229, 222),
WAVE_RGB_COLOR("seashell3", 205, 197, 191),
WAVE_RGB_COLOR("seashell4", 139, 134, 130),
WAVE_RGB_COLOR("sienna", 160, 82, 45),
WAVE_RGB_COLOR("sienna1", 255, 130, 71),
WAVE_RGB_COLOR("sienna2", 238, 121, 66),
WAVE_RGB_COLOR("sienna3", 205, 104, 57),
WAVE_RGB_COLOR("sienna4", 139, 71, 38),
WAVE_RGB_COLOR("sky blue", 135, 206, 235),
WAVE_RGB_COLOR("SkyBlue", 135, 206, 235),
WAVE_RGB_COLOR("SkyBlue1", 135, 206, 255),
WAVE_RGB_COLOR("SkyBlue2", 126, 192, 238),
WAVE_RGB_COLOR("SkyBlue3", 108, 166, 205),
WAVE_RGB_COLOR("SkyBlue4", 74, 112, 139),
WAVE_RGB_COLOR("slate blue", 106, 90, 205),
WAVE_RGB_COLOR("slate gray", 112, 128, 144),
WAVE_RGB_COLOR("slate grey", 112, 128, 144),
WAVE_RGB_COLOR("SlateBlue", 106, 90, 205),
WAVE_RGB_COLOR("SlateBlue1", 131, 111, 255),
WAVE_RGB_COLOR("SlateBlue2", 122, 103, 238),
WAVE_RGB_COLOR("SlateBlue3", 105, 89, 205),
WAVE_RGB_COLOR("SlateBlue4", 71, 60, 139),
WAVE_RGB_COLOR("SlateGray", 112, 128, 144),
WAVE_RGB_COLOR("SlateGray1", 198, 226, 255),
WAVE_RGB_COLOR("SlateGray2", 185, 211, 238),
WAVE_RGB_COLOR("SlateGray3", 159, 182, 205),
WAVE_RGB_COLOR("SlateGray4", 108, 123, 139),
WAVE_RGB_COLOR("SlateGrey", 112, 128, 144),
WAVE_RGB_COLOR("snow", 255, 250, 250),
WAVE_RGB_COLOR("snow1", 255, 250, 250),
WAVE_RGB_COLOR("snow2", 238, 233, 233),
WAVE_RGB_COLOR("snow3", 205, 201, 201),
WAVE_RGB_COLOR("snow4", 139, 137, 137),
WAVE_RGB_COLOR("spring green", 0, 255, 127),
WAVE_RGB_COLOR("SpringGreen", 0, 255, 127),
WAVE_RGB_COLOR("SpringGreen1", 0, 255, 127),
WAVE_RGB_COLOR("SpringGreen2", 0, 238, 118),
WAVE_RGB_COLOR("SpringGreen3", 0, 205, 102),
WAVE_RGB_COLOR("SpringGreen4", 0, 139, 69),
WAVE_RGB_COLOR("steel blue", 70, 130, 180),
WAVE_RGB_COLOR("SteelBlue", 70, 130, 180),
WAVE_RGB_COLOR("SteelBlue1", 99, 184, 255),
WAVE_RGB_COLOR("SteelBlue2", 92, 172, 238),
WAVE_RGB_COLOR("SteelBlue3", 79, 148, 205),
WAVE_RGB_COLOR("SteelBlue4", 54, 100, 139),
WAVE_RGB_COLOR("tan", 210, 180, 140),
WAVE_RGB_COLOR("tan1", 255, 165, 79),
WAVE_RGB_COLOR("tan2", 238, 154, 73),
WAVE_RGB_COLOR("tan3", 205, 133, 63),
WAVE_RGB_COLOR("tan4", 139, 90, 43),
WAVE_RGB_COLOR("thistle", 216, 191, 216),
WAVE_RGB_COLOR("thistle1", 255, 225, 255),
WAVE_RGB_COLOR("thistle2", 238, 210, 238),
WAVE_RGB_COLOR("thistle3", 205, 181, 205),
WAVE_RGB_COLOR("thistle4", 139, 123, 139),
WAVE_RGB_COLOR("tomato", 255, 99, 71),
WAVE_RGB_COLOR("tomato1", 255, 99, 71),
WAVE_RGB_COLOR("tomato2", 238, 92, 66),
WAVE_RGB_COLOR("tomato3", 205, 79, 57),
WAVE_RGB_COLOR("tomato4", 139, 54, 38),
WAVE_RGB_COLOR("turquoise", 64, 224, 208),
WAVE_RGB_COLOR("turquoise1", 0, 245, 255),
WAVE_RGB_COLOR("turquoise2", 0, 229, 238),
WAVE_RGB_COLOR("turquoise3", 0, 197, 205),
WAVE_RGB_COLOR("turquoise4", 0, 134, 139),
WAVE_RGB_COLOR("violet", 238, 130, 238),
WAVE_RGB_COLOR("violet red", 208, 32, 144),
WAVE_RGB_COLOR("VioletRed", 208, 32, 144),
WAVE_RGB_COLOR("VioletRed1", 255, 62, 150),
WAVE_RGB_COLOR("VioletRed2", 238, 58, 140),
WAVE_RGB_COLOR("VioletRed3", 205, 50, 120),
WAVE_RGB_COLOR("VioletRed4", 139, 34, 82),
WAVE_RGB_COLOR("wheat", 245, 222, 179),
WAVE_RGB_COLOR("wheat1", 255, 231, 186),
WAVE_RGB_COLOR("wheat2", 238, 216, 174),
WAVE_RGB_COLOR("wheat3", 205, 186, 150),
WAVE_RGB_COLOR("wheat4", 139, 126, 102),
WAVE_RGB_COLOR("white", 255, 255, 255),
WAVE_RGB_COLOR("white smoke", 245, 245, 245),
WAVE_RGB_COLOR("WhiteSmoke", 245, 245, 245),
WAVE_RGB_COLOR("yellow", 255, 255, 0),
WAVE_RGB_COLOR("yellow green", 154, 205, 50),
WAVE_RGB_COLOR("yellow1", 255, 255, 0),
WAVE_RGB_COLOR("yellow2", 238, 238, 0),
WAVE_RGB_COLOR("yellow3", 205, 205, 0),
WAVE_RGB_COLOR("yellow4", 139, 139, 0),
WAVE_RGB_COLOR("YellowGreen", 154, 205, 50),
};
'''

@ -0,0 +1,45 @@
#!/usr/bin/python3
# gtkwave process filter
#
# display gpr adr/dat (read, 1 cyc access)
#
# format=binary so justification and data length don't matter

import sys

color = ''

fi = sys.stdin
fo = sys.stdout
fe = sys.stderr

def dbg(m):
fe.write(m + '\n')
fe.flush()

def main():

lastAdr = -1

while True:

line = fi.readline()
if not line:
return 0

try:
if lastAdr == -1:
fo.write(f'{color}XX:XXXXXXXXXXXXXXXX\n')
else:
fo.write(f'{color}{lastAdr:02X}:{int(line[6:70],2):016X}\n')
lastAdr = int(line[0:6],2)
except Exception as e:
fe.write('error!\n')
fe.write(str(e))
fe.flush()
fo.write('filter error!\n')

fo.flush()

if __name__ == '__main__':
sys.exit(main())

@ -0,0 +1,43 @@
#!/usr/bin/python3
# gtkwave process filter
#
# display gpr we/adr/dat
#
# format=binary so justification and data length don't matter

import sys

#colorI = '?LightGray?'
colorI = ''
colorV = '?DarkBlue?'

fi = sys.stdin
fo = sys.stdout
fe = sys.stderr

def dbg(m):
fe.write(m + '\n')
fe.flush()

def main():

while True:

line = fi.readline()
if not line:
return 0

try:
if line[0] == '0':
fo.write(f'{colorI}{int(line[1:7],2):02X}:{int(line[7:71],2):016X}\n')
else:
fo.write(f'{colorV}{int(line[1:7],2):02X}:{int(line[7:71],2):016X}\n')
except Exception as e:
fe.write('error!\n')
fe.write(str(e))
fo.write('filter error!\n')

fo.flush()

if __name__ == '__main__':
sys.exit(main())

@ -0,0 +1,37 @@
#!/usr/bin/python3
# gtkwave process filter
#
# split binary ibuf entry into op/bta/ifar

import sys

fi = sys.stdin
fo = sys.stdout
fe = sys.stderr

def dbg(m):
fe.write(m + '\n')
fe.flush()

# ppc 0:31, ppc+ 32:69, bta 70:89, ifar 90:109
ibufInstrWidth = 70
effIFARWidth = 20
ibufIFARWidth = 20

def main():

while True:

line = fi.readline()
if not line:
return 0

try:
fo.write(f'{int(line[0:32],2):08X} a={int(line[ibufInstrWidth+effIFARWidth:],2)<<2:08X} m={int(line[32:ibufInstrWidth],2):10X} t={int(line[ibufInstrWidth:ibufInstrWidth+effIFARWidth],2)<<2:08X}\n')
except:
fo.write('\n')

fo.flush()

if __name__ == '__main__':
sys.exit(main())

@ -0,0 +1,30 @@
#!/usr/bin/python3
# gtkwave process filter

# does nothing

import sys

fi = sys.stdin
fo = sys.stdout
fe = sys.stderr

debug = False

def dbg(m):
if debug:
fe.write(m + '\n')
fe.flush()

def main():

while True:

l = fi.readline()
if not l:
return 0
fo.write(f'{l}\n')
fo.flush()

if __name__ == '__main__':
sys.exit(main())

@ -0,0 +1,880 @@
#!/usr/bin/python3
# gtkwave process filter

# add:
# pseudo op xlate (rlwinm->shift, etc.)

import sys
import tempfile
import subprocess

fi = sys.stdin
fo = sys.stdout
fe = sys.stderr

debug = False

def dbg(m):
if debug:
fe.write(m + '\n')
fe.flush()

colors = {
#'default':'DeepSkyBlue',
'default':'DarkGreen',
'data':'DarkGray',
'bctr':'DarkOrange',
'x':'red'
}

def dasm(op):
oo = tempfile.NamedTemporaryFile(delete=False, mode='w')
ai = tempfile.NamedTemporaryFile(delete=False, mode='w')
ai.write(f'.long 0x{op}\n')
ai.flush()
#subprocess.run(["powerpc-linux-gnu-as", "-mpower9", "-o", oo.name, ai.name])
subprocess.run(["powerpc-linux-gnu-as", "-ma2", "-o", oo.name, ai.name])
result = subprocess.run(["powerpc-linux-gnu-objdump", "-d", oo.name], capture_output=True)
lines = result.stdout.splitlines()
if len(lines) < 8:
return [f'0x{op}', '']
l = result.stdout.splitlines()[-1]
tokens = l.decode().split('\t')
op = tokens[2].split()
if op[0] == '.long':
op = [f'0x{int(op[1], 16):08X}', '']
else:
op = massage(op)
if len(op) > 1:
return [op[0], ' '.join(op[1:])]
else:
return [op[0], ' ']

# beautify pseudo-ops [op operand1,operand2,...]
def massage(op, hexify=False):
# li r,i = li r,hex(i)
# slwi rx,ry,a = rlwinm rx,ry,a,0,31-a
# mtspr n,r = mtspr name,r
# mfspr r,n = mfspr r,name

sprNames = {
'438': 'tens',
'446': 'tir',
'815': 'tar'
}

if len(op) < 2:
return op

ops = op[1].split(',')
if op[0] == 'li':
op = ['li', f'{ops[0]},0x{int(ops[1]):04X}']
elif op[0] == 'rlwinm':
if int(ops[3]) == 0 and int(ops[4]) == 31-int(ops[2]):
op = ['slwi', f'{ops[0]},{ops[1]},{ops[2]}']
elif op[0] == 'mfspr':
if ops[1] in sprNames:
op = ['mfspr', f'{ops[0]},{sprNames[ops[1]]}']
elif op[0] == 'mtspr':
if ops[0] in sprNames:
op = ['mtspr', f'{sprNames[ops[0]]},{ops[1]}']

if hexify:
for i in range(len(ops)):
try:
if int(ops[i]) > 10:
ops[i] = f'0x{int(ops[i]):X}'
except:
pass
op[1] = ','.join(ops)

return op

def main():

while True:

l = fi.readline()

if not l:
return 0

if l[0] == 'x' or l[0] == 'z':
fo.write(f'?{colors["x"]}?X\n')
else:
t = dasm(l)
ins = t[0]
ops = t[1]
# could convert decimals > 10 to hex in operands
if ins[0:2] == '0x' and 'data' in colors:
color = colors['data']
elif ins in colors:
color = colors[ins]
else:
color = colors['default']
fo.write(f'?{color}?{ins} {ops}\n')

fo.flush()


if __name__ == '__main__':
sys.exit(main())

'''
rgb.c from gtkwave

static struct wave_rgb_color colors[] = {
WAVE_RGB_COLOR("alice blue", 240, 248, 255),
WAVE_RGB_COLOR("AliceBlue", 240, 248, 255),
WAVE_RGB_COLOR("antique white", 250, 235, 215),
WAVE_RGB_COLOR("AntiqueWhite", 250, 235, 215),
WAVE_RGB_COLOR("AntiqueWhite1", 255, 239, 219),
WAVE_RGB_COLOR("AntiqueWhite2", 238, 223, 204),
WAVE_RGB_COLOR("AntiqueWhite3", 205, 192, 176),
WAVE_RGB_COLOR("AntiqueWhite4", 139, 131, 120),
WAVE_RGB_COLOR("aquamarine", 127, 255, 212),
WAVE_RGB_COLOR("aquamarine1", 127, 255, 212),
WAVE_RGB_COLOR("aquamarine2", 118, 238, 198),
WAVE_RGB_COLOR("aquamarine3", 102, 205, 170),
WAVE_RGB_COLOR("aquamarine4", 69, 139, 116),
WAVE_RGB_COLOR("azure", 240, 255, 255),
WAVE_RGB_COLOR("azure1", 240, 255, 255),
WAVE_RGB_COLOR("azure2", 224, 238, 238),
WAVE_RGB_COLOR("azure3", 193, 205, 205),
WAVE_RGB_COLOR("azure4", 131, 139, 139),
WAVE_RGB_COLOR("beige", 245, 245, 220),
WAVE_RGB_COLOR("bisque", 255, 228, 196),
WAVE_RGB_COLOR("bisque1", 255, 228, 196),
WAVE_RGB_COLOR("bisque2", 238, 213, 183),
WAVE_RGB_COLOR("bisque3", 205, 183, 158),
WAVE_RGB_COLOR("bisque4", 139, 125, 107),
WAVE_RGB_COLOR("black", 0, 0, 0),
WAVE_RGB_COLOR("blanched almond", 255, 235, 205),
WAVE_RGB_COLOR("BlanchedAlmond", 255, 235, 205),
WAVE_RGB_COLOR("blue", 0, 0, 255),
WAVE_RGB_COLOR("blue violet", 138, 43, 226),
WAVE_RGB_COLOR("blue1", 0, 0, 255),
WAVE_RGB_COLOR("blue2", 0, 0, 238),
WAVE_RGB_COLOR("blue3", 0, 0, 205),
WAVE_RGB_COLOR("blue4", 0, 0, 139),
WAVE_RGB_COLOR("BlueViolet", 138, 43, 226),
WAVE_RGB_COLOR("brown", 165, 42, 42),
WAVE_RGB_COLOR("brown1", 255, 64, 64),
WAVE_RGB_COLOR("brown2", 238, 59, 59),
WAVE_RGB_COLOR("brown3", 205, 51, 51),
WAVE_RGB_COLOR("brown4", 139, 35, 35),
WAVE_RGB_COLOR("burlywood", 222, 184, 135),
WAVE_RGB_COLOR("burlywood1", 255, 211, 155),
WAVE_RGB_COLOR("burlywood2", 238, 197, 145),
WAVE_RGB_COLOR("burlywood3", 205, 170, 125),
WAVE_RGB_COLOR("burlywood4", 139, 115, 85),
WAVE_RGB_COLOR("cadet blue", 95, 158, 160),
WAVE_RGB_COLOR("CadetBlue", 95, 158, 160),
WAVE_RGB_COLOR("CadetBlue1", 152, 245, 255),
WAVE_RGB_COLOR("CadetBlue2", 142, 229, 238),
WAVE_RGB_COLOR("CadetBlue3", 122, 197, 205),
WAVE_RGB_COLOR("CadetBlue4", 83, 134, 139),
WAVE_RGB_COLOR("chartreuse", 127, 255, 0),
WAVE_RGB_COLOR("chartreuse1", 127, 255, 0),
WAVE_RGB_COLOR("chartreuse2", 118, 238, 0),
WAVE_RGB_COLOR("chartreuse3", 102, 205, 0),
WAVE_RGB_COLOR("chartreuse4", 69, 139, 0),
WAVE_RGB_COLOR("chocolate", 210, 105, 30),
WAVE_RGB_COLOR("chocolate1", 255, 127, 36),
WAVE_RGB_COLOR("chocolate2", 238, 118, 33),
WAVE_RGB_COLOR("chocolate3", 205, 102, 29),
WAVE_RGB_COLOR("chocolate4", 139, 69, 19),
WAVE_RGB_COLOR("coral", 255, 127, 80),
WAVE_RGB_COLOR("coral1", 255, 114, 86),
WAVE_RGB_COLOR("coral2", 238, 106, 80),
WAVE_RGB_COLOR("coral3", 205, 91, 69),
WAVE_RGB_COLOR("coral4", 139, 62, 47),
WAVE_RGB_COLOR("cornflower blue", 100, 149, 237),
WAVE_RGB_COLOR("CornflowerBlue", 100, 149, 237),
WAVE_RGB_COLOR("cornsilk", 255, 248, 220),
WAVE_RGB_COLOR("cornsilk1", 255, 248, 220),
WAVE_RGB_COLOR("cornsilk2", 238, 232, 205),
WAVE_RGB_COLOR("cornsilk3", 205, 200, 177),
WAVE_RGB_COLOR("cornsilk4", 139, 136, 120),
WAVE_RGB_COLOR("cyan", 0, 255, 255),
WAVE_RGB_COLOR("cyan1", 0, 255, 255),
WAVE_RGB_COLOR("cyan2", 0, 238, 238),
WAVE_RGB_COLOR("cyan3", 0, 205, 205),
WAVE_RGB_COLOR("cyan4", 0, 139, 139),
WAVE_RGB_COLOR("dark blue", 0, 0, 139),
WAVE_RGB_COLOR("dark cyan", 0, 139, 139),
WAVE_RGB_COLOR("dark goldenrod", 184, 134, 11),
WAVE_RGB_COLOR("dark gray", 169, 169, 169),
WAVE_RGB_COLOR("dark green", 0, 100, 0),
WAVE_RGB_COLOR("dark grey", 169, 169, 169),
WAVE_RGB_COLOR("dark khaki", 189, 183, 107),
WAVE_RGB_COLOR("dark magenta", 139, 0, 139),
WAVE_RGB_COLOR("dark olive green", 85, 107, 47),
WAVE_RGB_COLOR("dark orange", 255, 140, 0),
WAVE_RGB_COLOR("dark orchid", 153, 50, 204),
WAVE_RGB_COLOR("dark red", 139, 0, 0),
WAVE_RGB_COLOR("dark salmon", 233, 150, 122),
WAVE_RGB_COLOR("dark sea green", 143, 188, 143),
WAVE_RGB_COLOR("dark slate blue", 72, 61, 139),
WAVE_RGB_COLOR("dark slate gray", 47, 79, 79),
WAVE_RGB_COLOR("dark slate grey", 47, 79, 79),
WAVE_RGB_COLOR("dark turquoise", 0, 206, 209),
WAVE_RGB_COLOR("dark violet", 148, 0, 211),
WAVE_RGB_COLOR("DarkBlue", 0, 0, 139),
WAVE_RGB_COLOR("DarkCyan", 0, 139, 139),
WAVE_RGB_COLOR("DarkGoldenrod", 184, 134, 11),
WAVE_RGB_COLOR("DarkGoldenrod1", 255, 185, 15),
WAVE_RGB_COLOR("DarkGoldenrod2", 238, 173, 14),
WAVE_RGB_COLOR("DarkGoldenrod3", 205, 149, 12),
WAVE_RGB_COLOR("DarkGoldenrod4", 139, 101, 8),
WAVE_RGB_COLOR("DarkGray", 169, 169, 169),
WAVE_RGB_COLOR("DarkGreen", 0, 100, 0),
WAVE_RGB_COLOR("DarkGrey", 169, 169, 169),
WAVE_RGB_COLOR("DarkKhaki", 189, 183, 107),
WAVE_RGB_COLOR("DarkMagenta", 139, 0, 139),
WAVE_RGB_COLOR("DarkOliveGreen", 85, 107, 47),
WAVE_RGB_COLOR("DarkOliveGreen1", 202, 255, 112),
WAVE_RGB_COLOR("DarkOliveGreen2", 188, 238, 104),
WAVE_RGB_COLOR("DarkOliveGreen3", 162, 205, 90),
WAVE_RGB_COLOR("DarkOliveGreen4", 110, 139, 61),
WAVE_RGB_COLOR("DarkOrange", 255, 140, 0),
WAVE_RGB_COLOR("DarkOrange1", 255, 127, 0),
WAVE_RGB_COLOR("DarkOrange2", 238, 118, 0),
WAVE_RGB_COLOR("DarkOrange3", 205, 102, 0),
WAVE_RGB_COLOR("DarkOrange4", 139, 69, 0),
WAVE_RGB_COLOR("DarkOrchid", 153, 50, 204),
WAVE_RGB_COLOR("DarkOrchid1", 191, 62, 255),
WAVE_RGB_COLOR("DarkOrchid2", 178, 58, 238),
WAVE_RGB_COLOR("DarkOrchid3", 154, 50, 205),
WAVE_RGB_COLOR("DarkOrchid4", 104, 34, 139),
WAVE_RGB_COLOR("DarkRed", 139, 0, 0),
WAVE_RGB_COLOR("DarkSalmon", 233, 150, 122),
WAVE_RGB_COLOR("DarkSeaGreen", 143, 188, 143),
WAVE_RGB_COLOR("DarkSeaGreen1", 193, 255, 193),
WAVE_RGB_COLOR("DarkSeaGreen2", 180, 238, 180),
WAVE_RGB_COLOR("DarkSeaGreen3", 155, 205, 155),
WAVE_RGB_COLOR("DarkSeaGreen4", 105, 139, 105),
WAVE_RGB_COLOR("DarkSlateBlue", 72, 61, 139),
WAVE_RGB_COLOR("DarkSlateGray", 47, 79, 79),
WAVE_RGB_COLOR("DarkSlateGray1", 151, 255, 255),
WAVE_RGB_COLOR("DarkSlateGray2", 141, 238, 238),
WAVE_RGB_COLOR("DarkSlateGray3", 121, 205, 205),
WAVE_RGB_COLOR("DarkSlateGray4", 82, 139, 139),
WAVE_RGB_COLOR("DarkSlateGrey", 47, 79, 79),
WAVE_RGB_COLOR("DarkTurquoise", 0, 206, 209),
WAVE_RGB_COLOR("DarkViolet", 148, 0, 211),
WAVE_RGB_COLOR("deep pink", 255, 20, 147),
WAVE_RGB_COLOR("deep sky blue", 0, 191, 255),
WAVE_RGB_COLOR("DeepPink", 255, 20, 147),
WAVE_RGB_COLOR("DeepPink1", 255, 20, 147),
WAVE_RGB_COLOR("DeepPink2", 238, 18, 137),
WAVE_RGB_COLOR("DeepPink3", 205, 16, 118),
WAVE_RGB_COLOR("DeepPink4", 139, 10, 80),
WAVE_RGB_COLOR("DeepSkyBlue", 0, 191, 255),
WAVE_RGB_COLOR("DeepSkyBlue1", 0, 191, 255),
WAVE_RGB_COLOR("DeepSkyBlue2", 0, 178, 238),
WAVE_RGB_COLOR("DeepSkyBlue3", 0, 154, 205),
WAVE_RGB_COLOR("DeepSkyBlue4", 0, 104, 139),
WAVE_RGB_COLOR("dim gray", 105, 105, 105),
WAVE_RGB_COLOR("dim grey", 105, 105, 105),
WAVE_RGB_COLOR("DimGray", 105, 105, 105),
WAVE_RGB_COLOR("DimGrey", 105, 105, 105),
WAVE_RGB_COLOR("dodger blue", 30, 144, 255),
WAVE_RGB_COLOR("DodgerBlue", 30, 144, 255),
WAVE_RGB_COLOR("DodgerBlue1", 30, 144, 255),
WAVE_RGB_COLOR("DodgerBlue2", 28, 134, 238),
WAVE_RGB_COLOR("DodgerBlue3", 24, 116, 205),
WAVE_RGB_COLOR("DodgerBlue4", 16, 78, 139),
WAVE_RGB_COLOR("firebrick", 178, 34, 34),
WAVE_RGB_COLOR("firebrick1", 255, 48, 48),
WAVE_RGB_COLOR("firebrick2", 238, 44, 44),
WAVE_RGB_COLOR("firebrick3", 205, 38, 38),
WAVE_RGB_COLOR("firebrick4", 139, 26, 26),
WAVE_RGB_COLOR("floral white", 255, 250, 240),
WAVE_RGB_COLOR("FloralWhite", 255, 250, 240),
WAVE_RGB_COLOR("forest green", 34, 139, 34),
WAVE_RGB_COLOR("ForestGreen", 34, 139, 34),
WAVE_RGB_COLOR("gainsboro", 220, 220, 220),
WAVE_RGB_COLOR("ghost white", 248, 248, 255),
WAVE_RGB_COLOR("GhostWhite", 248, 248, 255),
WAVE_RGB_COLOR("gold", 255, 215, 0),
WAVE_RGB_COLOR("gold1", 255, 215, 0),
WAVE_RGB_COLOR("gold2", 238, 201, 0),
WAVE_RGB_COLOR("gold3", 205, 173, 0),
WAVE_RGB_COLOR("gold4", 139, 117, 0),
WAVE_RGB_COLOR("goldenrod", 218, 165, 32),
WAVE_RGB_COLOR("goldenrod1", 255, 193, 37),
WAVE_RGB_COLOR("goldenrod2", 238, 180, 34),
WAVE_RGB_COLOR("goldenrod3", 205, 155, 29),
WAVE_RGB_COLOR("goldenrod4", 139, 105, 20),
WAVE_RGB_COLOR("gray", 190, 190, 190),
WAVE_RGB_COLOR("gray0", 0, 0, 0),
WAVE_RGB_COLOR("gray1", 3, 3, 3),
WAVE_RGB_COLOR("gray10", 26, 26, 26),
WAVE_RGB_COLOR("gray100", 255, 255, 255),
WAVE_RGB_COLOR("gray11", 28, 28, 28),
WAVE_RGB_COLOR("gray12", 31, 31, 31),
WAVE_RGB_COLOR("gray13", 33, 33, 33),
WAVE_RGB_COLOR("gray14", 36, 36, 36),
WAVE_RGB_COLOR("gray15", 38, 38, 38),
WAVE_RGB_COLOR("gray16", 41, 41, 41),
WAVE_RGB_COLOR("gray17", 43, 43, 43),
WAVE_RGB_COLOR("gray18", 46, 46, 46),
WAVE_RGB_COLOR("gray19", 48, 48, 48),
WAVE_RGB_COLOR("gray2", 5, 5, 5),
WAVE_RGB_COLOR("gray20", 51, 51, 51),
WAVE_RGB_COLOR("gray21", 54, 54, 54),
WAVE_RGB_COLOR("gray22", 56, 56, 56),
WAVE_RGB_COLOR("gray23", 59, 59, 59),
WAVE_RGB_COLOR("gray24", 61, 61, 61),
WAVE_RGB_COLOR("gray25", 64, 64, 64),
WAVE_RGB_COLOR("gray26", 66, 66, 66),
WAVE_RGB_COLOR("gray27", 69, 69, 69),
WAVE_RGB_COLOR("gray28", 71, 71, 71),
WAVE_RGB_COLOR("gray29", 74, 74, 74),
WAVE_RGB_COLOR("gray3", 8, 8, 8),
WAVE_RGB_COLOR("gray30", 77, 77, 77),
WAVE_RGB_COLOR("gray31", 79, 79, 79),
WAVE_RGB_COLOR("gray32", 82, 82, 82),
WAVE_RGB_COLOR("gray33", 84, 84, 84),
WAVE_RGB_COLOR("gray34", 87, 87, 87),
WAVE_RGB_COLOR("gray35", 89, 89, 89),
WAVE_RGB_COLOR("gray36", 92, 92, 92),
WAVE_RGB_COLOR("gray37", 94, 94, 94),
WAVE_RGB_COLOR("gray38", 97, 97, 97),
WAVE_RGB_COLOR("gray39", 99, 99, 99),
WAVE_RGB_COLOR("gray4", 10, 10, 10),
WAVE_RGB_COLOR("gray40", 102, 102, 102),
WAVE_RGB_COLOR("gray41", 105, 105, 105),
WAVE_RGB_COLOR("gray42", 107, 107, 107),
WAVE_RGB_COLOR("gray43", 110, 110, 110),
WAVE_RGB_COLOR("gray44", 112, 112, 112),
WAVE_RGB_COLOR("gray45", 115, 115, 115),
WAVE_RGB_COLOR("gray46", 117, 117, 117),
WAVE_RGB_COLOR("gray47", 120, 120, 120),
WAVE_RGB_COLOR("gray48", 122, 122, 122),
WAVE_RGB_COLOR("gray49", 125, 125, 125),
WAVE_RGB_COLOR("gray5", 13, 13, 13),
WAVE_RGB_COLOR("gray50", 127, 127, 127),
WAVE_RGB_COLOR("gray51", 130, 130, 130),
WAVE_RGB_COLOR("gray52", 133, 133, 133),
WAVE_RGB_COLOR("gray53", 135, 135, 135),
WAVE_RGB_COLOR("gray54", 138, 138, 138),
WAVE_RGB_COLOR("gray55", 140, 140, 140),
WAVE_RGB_COLOR("gray56", 143, 143, 143),
WAVE_RGB_COLOR("gray57", 145, 145, 145),
WAVE_RGB_COLOR("gray58", 148, 148, 148),
WAVE_RGB_COLOR("gray59", 150, 150, 150),
WAVE_RGB_COLOR("gray6", 15, 15, 15),
WAVE_RGB_COLOR("gray60", 153, 153, 153),
WAVE_RGB_COLOR("gray61", 156, 156, 156),
WAVE_RGB_COLOR("gray62", 158, 158, 158),
WAVE_RGB_COLOR("gray63", 161, 161, 161),
WAVE_RGB_COLOR("gray64", 163, 163, 163),
WAVE_RGB_COLOR("gray65", 166, 166, 166),
WAVE_RGB_COLOR("gray66", 168, 168, 168),
WAVE_RGB_COLOR("gray67", 171, 171, 171),
WAVE_RGB_COLOR("gray68", 173, 173, 173),
WAVE_RGB_COLOR("gray69", 176, 176, 176),
WAVE_RGB_COLOR("gray7", 18, 18, 18),
WAVE_RGB_COLOR("gray70", 179, 179, 179),
WAVE_RGB_COLOR("gray71", 181, 181, 181),
WAVE_RGB_COLOR("gray72", 184, 184, 184),
WAVE_RGB_COLOR("gray73", 186, 186, 186),
WAVE_RGB_COLOR("gray74", 189, 189, 189),
WAVE_RGB_COLOR("gray75", 191, 191, 191),
WAVE_RGB_COLOR("gray76", 194, 194, 194),
WAVE_RGB_COLOR("gray77", 196, 196, 196),
WAVE_RGB_COLOR("gray78", 199, 199, 199),
WAVE_RGB_COLOR("gray79", 201, 201, 201),
WAVE_RGB_COLOR("gray8", 20, 20, 20),
WAVE_RGB_COLOR("gray80", 204, 204, 204),
WAVE_RGB_COLOR("gray81", 207, 207, 207),
WAVE_RGB_COLOR("gray82", 209, 209, 209),
WAVE_RGB_COLOR("gray83", 212, 212, 212),
WAVE_RGB_COLOR("gray84", 214, 214, 214),
WAVE_RGB_COLOR("gray85", 217, 217, 217),
WAVE_RGB_COLOR("gray86", 219, 219, 219),
WAVE_RGB_COLOR("gray87", 222, 222, 222),
WAVE_RGB_COLOR("gray88", 224, 224, 224),
WAVE_RGB_COLOR("gray89", 227, 227, 227),
WAVE_RGB_COLOR("gray9", 23, 23, 23),
WAVE_RGB_COLOR("gray90", 229, 229, 229),
WAVE_RGB_COLOR("gray91", 232, 232, 232),
WAVE_RGB_COLOR("gray92", 235, 235, 235),
WAVE_RGB_COLOR("gray93", 237, 237, 237),
WAVE_RGB_COLOR("gray94", 240, 240, 240),
WAVE_RGB_COLOR("gray95", 242, 242, 242),
WAVE_RGB_COLOR("gray96", 245, 245, 245),
WAVE_RGB_COLOR("gray97", 247, 247, 247),
WAVE_RGB_COLOR("gray98", 250, 250, 250),
WAVE_RGB_COLOR("gray99", 252, 252, 252),
WAVE_RGB_COLOR("green", 0, 255, 0),
WAVE_RGB_COLOR("green yellow", 173, 255, 47),
WAVE_RGB_COLOR("green1", 0, 255, 0),
WAVE_RGB_COLOR("green2", 0, 238, 0),
WAVE_RGB_COLOR("green3", 0, 205, 0),
WAVE_RGB_COLOR("green4", 0, 139, 0),
WAVE_RGB_COLOR("GreenYellow", 173, 255, 47),
WAVE_RGB_COLOR("grey", 190, 190, 190),
WAVE_RGB_COLOR("grey0", 0, 0, 0),
WAVE_RGB_COLOR("grey1", 3, 3, 3),
WAVE_RGB_COLOR("grey10", 26, 26, 26),
WAVE_RGB_COLOR("grey100", 255, 255, 255),
WAVE_RGB_COLOR("grey11", 28, 28, 28),
WAVE_RGB_COLOR("grey12", 31, 31, 31),
WAVE_RGB_COLOR("grey13", 33, 33, 33),
WAVE_RGB_COLOR("grey14", 36, 36, 36),
WAVE_RGB_COLOR("grey15", 38, 38, 38),
WAVE_RGB_COLOR("grey16", 41, 41, 41),
WAVE_RGB_COLOR("grey17", 43, 43, 43),
WAVE_RGB_COLOR("grey18", 46, 46, 46),
WAVE_RGB_COLOR("grey19", 48, 48, 48),
WAVE_RGB_COLOR("grey2", 5, 5, 5),
WAVE_RGB_COLOR("grey20", 51, 51, 51),
WAVE_RGB_COLOR("grey21", 54, 54, 54),
WAVE_RGB_COLOR("grey22", 56, 56, 56),
WAVE_RGB_COLOR("grey23", 59, 59, 59),
WAVE_RGB_COLOR("grey24", 61, 61, 61),
WAVE_RGB_COLOR("grey25", 64, 64, 64),
WAVE_RGB_COLOR("grey26", 66, 66, 66),
WAVE_RGB_COLOR("grey27", 69, 69, 69),
WAVE_RGB_COLOR("grey28", 71, 71, 71),
WAVE_RGB_COLOR("grey29", 74, 74, 74),
WAVE_RGB_COLOR("grey3", 8, 8, 8),
WAVE_RGB_COLOR("grey30", 77, 77, 77),
WAVE_RGB_COLOR("grey31", 79, 79, 79),
WAVE_RGB_COLOR("grey32", 82, 82, 82),
WAVE_RGB_COLOR("grey33", 84, 84, 84),
WAVE_RGB_COLOR("grey34", 87, 87, 87),
WAVE_RGB_COLOR("grey35", 89, 89, 89),
WAVE_RGB_COLOR("grey36", 92, 92, 92),
WAVE_RGB_COLOR("grey37", 94, 94, 94),
WAVE_RGB_COLOR("grey38", 97, 97, 97),
WAVE_RGB_COLOR("grey39", 99, 99, 99),
WAVE_RGB_COLOR("grey4", 10, 10, 10),
WAVE_RGB_COLOR("grey40", 102, 102, 102),
WAVE_RGB_COLOR("grey41", 105, 105, 105),
WAVE_RGB_COLOR("grey42", 107, 107, 107),
WAVE_RGB_COLOR("grey43", 110, 110, 110),
WAVE_RGB_COLOR("grey44", 112, 112, 112),
WAVE_RGB_COLOR("grey45", 115, 115, 115),
WAVE_RGB_COLOR("grey46", 117, 117, 117),
WAVE_RGB_COLOR("grey47", 120, 120, 120),
WAVE_RGB_COLOR("grey48", 122, 122, 122),
WAVE_RGB_COLOR("grey49", 125, 125, 125),
WAVE_RGB_COLOR("grey5", 13, 13, 13),
WAVE_RGB_COLOR("grey50", 127, 127, 127),
WAVE_RGB_COLOR("grey51", 130, 130, 130),
WAVE_RGB_COLOR("grey52", 133, 133, 133),
WAVE_RGB_COLOR("grey53", 135, 135, 135),
WAVE_RGB_COLOR("grey54", 138, 138, 138),
WAVE_RGB_COLOR("grey55", 140, 140, 140),
WAVE_RGB_COLOR("grey56", 143, 143, 143),
WAVE_RGB_COLOR("grey57", 145, 145, 145),
WAVE_RGB_COLOR("grey58", 148, 148, 148),
WAVE_RGB_COLOR("grey59", 150, 150, 150),
WAVE_RGB_COLOR("grey6", 15, 15, 15),
WAVE_RGB_COLOR("grey60", 153, 153, 153),
WAVE_RGB_COLOR("grey61", 156, 156, 156),
WAVE_RGB_COLOR("grey62", 158, 158, 158),
WAVE_RGB_COLOR("grey63", 161, 161, 161),
WAVE_RGB_COLOR("grey64", 163, 163, 163),
WAVE_RGB_COLOR("grey65", 166, 166, 166),
WAVE_RGB_COLOR("grey66", 168, 168, 168),
WAVE_RGB_COLOR("grey67", 171, 171, 171),
WAVE_RGB_COLOR("grey68", 173, 173, 173),
WAVE_RGB_COLOR("grey69", 176, 176, 176),
WAVE_RGB_COLOR("grey7", 18, 18, 18),
WAVE_RGB_COLOR("grey70", 179, 179, 179),
WAVE_RGB_COLOR("grey71", 181, 181, 181),
WAVE_RGB_COLOR("grey72", 184, 184, 184),
WAVE_RGB_COLOR("grey73", 186, 186, 186),
WAVE_RGB_COLOR("grey74", 189, 189, 189),
WAVE_RGB_COLOR("grey75", 191, 191, 191),
WAVE_RGB_COLOR("grey76", 194, 194, 194),
WAVE_RGB_COLOR("grey77", 196, 196, 196),
WAVE_RGB_COLOR("grey78", 199, 199, 199),
WAVE_RGB_COLOR("grey79", 201, 201, 201),
WAVE_RGB_COLOR("grey8", 20, 20, 20),
WAVE_RGB_COLOR("grey80", 204, 204, 204),
WAVE_RGB_COLOR("grey81", 207, 207, 207),
WAVE_RGB_COLOR("grey82", 209, 209, 209),
WAVE_RGB_COLOR("grey83", 212, 212, 212),
WAVE_RGB_COLOR("grey84", 214, 214, 214),
WAVE_RGB_COLOR("grey85", 217, 217, 217),
WAVE_RGB_COLOR("grey86", 219, 219, 219),
WAVE_RGB_COLOR("grey87", 222, 222, 222),
WAVE_RGB_COLOR("grey88", 224, 224, 224),
WAVE_RGB_COLOR("grey89", 227, 227, 227),
WAVE_RGB_COLOR("grey9", 23, 23, 23),
WAVE_RGB_COLOR("grey90", 229, 229, 229),
WAVE_RGB_COLOR("grey91", 232, 232, 232),
WAVE_RGB_COLOR("grey92", 235, 235, 235),
WAVE_RGB_COLOR("grey93", 237, 237, 237),
WAVE_RGB_COLOR("grey94", 240, 240, 240),
WAVE_RGB_COLOR("grey95", 242, 242, 242),
WAVE_RGB_COLOR("grey96", 245, 245, 245),
WAVE_RGB_COLOR("grey97", 247, 247, 247),
WAVE_RGB_COLOR("grey98", 250, 250, 250),
WAVE_RGB_COLOR("grey99", 252, 252, 252),
WAVE_RGB_COLOR("honeydew", 240, 255, 240),
WAVE_RGB_COLOR("honeydew1", 240, 255, 240),
WAVE_RGB_COLOR("honeydew2", 224, 238, 224),
WAVE_RGB_COLOR("honeydew3", 193, 205, 193),
WAVE_RGB_COLOR("honeydew4", 131, 139, 131),
WAVE_RGB_COLOR("hot pink", 255, 105, 180),
WAVE_RGB_COLOR("HotPink", 255, 105, 180),
WAVE_RGB_COLOR("HotPink1", 255, 110, 180),
WAVE_RGB_COLOR("HotPink2", 238, 106, 167),
WAVE_RGB_COLOR("HotPink3", 205, 96, 144),
WAVE_RGB_COLOR("HotPink4", 139, 58, 98),
WAVE_RGB_COLOR("indian red", 205, 92, 92),
WAVE_RGB_COLOR("IndianRed", 205, 92, 92),
WAVE_RGB_COLOR("IndianRed1", 255, 106, 106),
WAVE_RGB_COLOR("IndianRed2", 238, 99, 99),
WAVE_RGB_COLOR("IndianRed3", 205, 85, 85),
WAVE_RGB_COLOR("IndianRed4", 139, 58, 58),
WAVE_RGB_COLOR("ivory", 255, 255, 240),
WAVE_RGB_COLOR("ivory1", 255, 255, 240),
WAVE_RGB_COLOR("ivory2", 238, 238, 224),
WAVE_RGB_COLOR("ivory3", 205, 205, 193),
WAVE_RGB_COLOR("ivory4", 139, 139, 131),
WAVE_RGB_COLOR("khaki", 240, 230, 140),
WAVE_RGB_COLOR("khaki1", 255, 246, 143),
WAVE_RGB_COLOR("khaki2", 238, 230, 133),
WAVE_RGB_COLOR("khaki3", 205, 198, 115),
WAVE_RGB_COLOR("khaki4", 139, 134, 78),
WAVE_RGB_COLOR("lavender", 230, 230, 250),
WAVE_RGB_COLOR("lavender blush", 255, 240, 245),
WAVE_RGB_COLOR("LavenderBlush", 255, 240, 245),
WAVE_RGB_COLOR("LavenderBlush1", 255, 240, 245),
WAVE_RGB_COLOR("LavenderBlush2", 238, 224, 229),
WAVE_RGB_COLOR("LavenderBlush3", 205, 193, 197),
WAVE_RGB_COLOR("LavenderBlush4", 139, 131, 134),
WAVE_RGB_COLOR("lawn green", 124, 252, 0),
WAVE_RGB_COLOR("LawnGreen", 124, 252, 0),
WAVE_RGB_COLOR("lemon chiffon", 255, 250, 205),
WAVE_RGB_COLOR("LemonChiffon", 255, 250, 205),
WAVE_RGB_COLOR("LemonChiffon1", 255, 250, 205),
WAVE_RGB_COLOR("LemonChiffon2", 238, 233, 191),
WAVE_RGB_COLOR("LemonChiffon3", 205, 201, 165),
WAVE_RGB_COLOR("LemonChiffon4", 139, 137, 112),
WAVE_RGB_COLOR("light blue", 173, 216, 230),
WAVE_RGB_COLOR("light coral", 240, 128, 128),
WAVE_RGB_COLOR("light cyan", 224, 255, 255),
WAVE_RGB_COLOR("light goldenrod", 238, 221, 130),
WAVE_RGB_COLOR("light goldenrod yellow", 250, 250, 210),
WAVE_RGB_COLOR("light gray", 211, 211, 211),
WAVE_RGB_COLOR("light green", 144, 238, 144),
WAVE_RGB_COLOR("light grey", 211, 211, 211),
WAVE_RGB_COLOR("light pink", 255, 182, 193),
WAVE_RGB_COLOR("light salmon", 255, 160, 122),
WAVE_RGB_COLOR("light sea green", 32, 178, 170),
WAVE_RGB_COLOR("light sky blue", 135, 206, 250),
WAVE_RGB_COLOR("light slate blue", 132, 112, 255),
WAVE_RGB_COLOR("light slate gray", 119, 136, 153),
WAVE_RGB_COLOR("light slate grey", 119, 136, 153),
WAVE_RGB_COLOR("light steel blue", 176, 196, 222),
WAVE_RGB_COLOR("light yellow", 255, 255, 224),
WAVE_RGB_COLOR("LightBlue", 173, 216, 230),
WAVE_RGB_COLOR("LightBlue1", 191, 239, 255),
WAVE_RGB_COLOR("LightBlue2", 178, 223, 238),
WAVE_RGB_COLOR("LightBlue3", 154, 192, 205),
WAVE_RGB_COLOR("LightBlue4", 104, 131, 139),
WAVE_RGB_COLOR("LightCoral", 240, 128, 128),
WAVE_RGB_COLOR("LightCyan", 224, 255, 255),
WAVE_RGB_COLOR("LightCyan1", 224, 255, 255),
WAVE_RGB_COLOR("LightCyan2", 209, 238, 238),
WAVE_RGB_COLOR("LightCyan3", 180, 205, 205),
WAVE_RGB_COLOR("LightCyan4", 122, 139, 139),
WAVE_RGB_COLOR("LightGoldenrod", 238, 221, 130),
WAVE_RGB_COLOR("LightGoldenrod1", 255, 236, 139),
WAVE_RGB_COLOR("LightGoldenrod2", 238, 220, 130),
WAVE_RGB_COLOR("LightGoldenrod3", 205, 190, 112),
WAVE_RGB_COLOR("LightGoldenrod4", 139, 129, 76),
WAVE_RGB_COLOR("LightGoldenrodYellow", 250, 250, 210),
WAVE_RGB_COLOR("LightGray", 211, 211, 211),
WAVE_RGB_COLOR("LightGreen", 144, 238, 144),
WAVE_RGB_COLOR("LightGrey", 211, 211, 211),
WAVE_RGB_COLOR("LightPink", 255, 182, 193),
WAVE_RGB_COLOR("LightPink1", 255, 174, 185),
WAVE_RGB_COLOR("LightPink2", 238, 162, 173),
WAVE_RGB_COLOR("LightPink3", 205, 140, 149),
WAVE_RGB_COLOR("LightPink4", 139, 95, 101),
WAVE_RGB_COLOR("LightSalmon", 255, 160, 122),
WAVE_RGB_COLOR("LightSalmon1", 255, 160, 122),
WAVE_RGB_COLOR("LightSalmon2", 238, 149, 114),
WAVE_RGB_COLOR("LightSalmon3", 205, 129, 98),
WAVE_RGB_COLOR("LightSalmon4", 139, 87, 66),
WAVE_RGB_COLOR("LightSeaGreen", 32, 178, 170),
WAVE_RGB_COLOR("LightSkyBlue", 135, 206, 250),
WAVE_RGB_COLOR("LightSkyBlue1", 176, 226, 255),
WAVE_RGB_COLOR("LightSkyBlue2", 164, 211, 238),
WAVE_RGB_COLOR("LightSkyBlue3", 141, 182, 205),
WAVE_RGB_COLOR("LightSkyBlue4", 96, 123, 139),
WAVE_RGB_COLOR("LightSlateBlue", 132, 112, 255),
WAVE_RGB_COLOR("LightSlateGray", 119, 136, 153),
WAVE_RGB_COLOR("LightSlateGrey", 119, 136, 153),
WAVE_RGB_COLOR("LightSteelBlue", 176, 196, 222),
WAVE_RGB_COLOR("LightSteelBlue1", 202, 225, 255),
WAVE_RGB_COLOR("LightSteelBlue2", 188, 210, 238),
WAVE_RGB_COLOR("LightSteelBlue3", 162, 181, 205),
WAVE_RGB_COLOR("LightSteelBlue4", 110, 123, 139),
WAVE_RGB_COLOR("LightYellow", 255, 255, 224),
WAVE_RGB_COLOR("LightYellow1", 255, 255, 224),
WAVE_RGB_COLOR("LightYellow2", 238, 238, 209),
WAVE_RGB_COLOR("LightYellow3", 205, 205, 180),
WAVE_RGB_COLOR("LightYellow4", 139, 139, 122),
WAVE_RGB_COLOR("lime green", 50, 205, 50),
WAVE_RGB_COLOR("LimeGreen", 50, 205, 50),
WAVE_RGB_COLOR("linen", 250, 240, 230),
WAVE_RGB_COLOR("magenta", 255, 0, 255),
WAVE_RGB_COLOR("magenta1", 255, 0, 255),
WAVE_RGB_COLOR("magenta2", 238, 0, 238),
WAVE_RGB_COLOR("magenta3", 205, 0, 205),
WAVE_RGB_COLOR("magenta4", 139, 0, 139),
WAVE_RGB_COLOR("maroon", 176, 48, 96),
WAVE_RGB_COLOR("maroon1", 255, 52, 179),
WAVE_RGB_COLOR("maroon2", 238, 48, 167),
WAVE_RGB_COLOR("maroon3", 205, 41, 144),
WAVE_RGB_COLOR("maroon4", 139, 28, 98),
WAVE_RGB_COLOR("medium aquamarine", 102, 205, 170),
WAVE_RGB_COLOR("medium blue", 0, 0, 205),
WAVE_RGB_COLOR("medium orchid", 186, 85, 211),
WAVE_RGB_COLOR("medium purple", 147, 112, 219),
WAVE_RGB_COLOR("medium sea green", 60, 179, 113),
WAVE_RGB_COLOR("medium slate blue", 123, 104, 238),
WAVE_RGB_COLOR("medium spring green", 0, 250, 154),
WAVE_RGB_COLOR("medium turquoise", 72, 209, 204),
WAVE_RGB_COLOR("medium violet red", 199, 21, 133),
WAVE_RGB_COLOR("MediumAquamarine", 102, 205, 170),
WAVE_RGB_COLOR("MediumBlue", 0, 0, 205),
WAVE_RGB_COLOR("MediumOrchid", 186, 85, 211),
WAVE_RGB_COLOR("MediumOrchid1", 224, 102, 255),
WAVE_RGB_COLOR("MediumOrchid2", 209, 95, 238),
WAVE_RGB_COLOR("MediumOrchid3", 180, 82, 205),
WAVE_RGB_COLOR("MediumOrchid4", 122, 55, 139),
WAVE_RGB_COLOR("MediumPurple", 147, 112, 219),
WAVE_RGB_COLOR("MediumPurple1", 171, 130, 255),
WAVE_RGB_COLOR("MediumPurple2", 159, 121, 238),
WAVE_RGB_COLOR("MediumPurple3", 137, 104, 205),
WAVE_RGB_COLOR("MediumPurple4", 93, 71, 139),
WAVE_RGB_COLOR("MediumSeaGreen", 60, 179, 113),
WAVE_RGB_COLOR("MediumSlateBlue", 123, 104, 238),
WAVE_RGB_COLOR("MediumSpringGreen", 0, 250, 154),
WAVE_RGB_COLOR("MediumTurquoise", 72, 209, 204),
WAVE_RGB_COLOR("MediumVioletRed", 199, 21, 133),
WAVE_RGB_COLOR("midnight blue", 25, 25, 112),
WAVE_RGB_COLOR("MidnightBlue", 25, 25, 112),
WAVE_RGB_COLOR("mint cream", 245, 255, 250),
WAVE_RGB_COLOR("MintCream", 245, 255, 250),
WAVE_RGB_COLOR("misty rose", 255, 228, 225),
WAVE_RGB_COLOR("MistyRose", 255, 228, 225),
WAVE_RGB_COLOR("MistyRose1", 255, 228, 225),
WAVE_RGB_COLOR("MistyRose2", 238, 213, 210),
WAVE_RGB_COLOR("MistyRose3", 205, 183, 181),
WAVE_RGB_COLOR("MistyRose4", 139, 125, 123),
WAVE_RGB_COLOR("moccasin", 255, 228, 181),
WAVE_RGB_COLOR("navajo white", 255, 222, 173),
WAVE_RGB_COLOR("NavajoWhite", 255, 222, 173),
WAVE_RGB_COLOR("NavajoWhite1", 255, 222, 173),
WAVE_RGB_COLOR("NavajoWhite2", 238, 207, 161),
WAVE_RGB_COLOR("NavajoWhite3", 205, 179, 139),
WAVE_RGB_COLOR("NavajoWhite4", 139, 121, 94),
WAVE_RGB_COLOR("navy", 0, 0, 128),
WAVE_RGB_COLOR("navy blue", 0, 0, 128),
WAVE_RGB_COLOR("NavyBlue", 0, 0, 128),
WAVE_RGB_COLOR("old lace", 253, 245, 230),
WAVE_RGB_COLOR("OldLace", 253, 245, 230),
WAVE_RGB_COLOR("olive drab", 107, 142, 35),
WAVE_RGB_COLOR("OliveDrab", 107, 142, 35),
WAVE_RGB_COLOR("OliveDrab1", 192, 255, 62),
WAVE_RGB_COLOR("OliveDrab2", 179, 238, 58),
WAVE_RGB_COLOR("OliveDrab3", 154, 205, 50),
WAVE_RGB_COLOR("OliveDrab4", 105, 139, 34),
WAVE_RGB_COLOR("orange", 255, 165, 0),
WAVE_RGB_COLOR("orange red", 255, 69, 0),
WAVE_RGB_COLOR("orange1", 255, 165, 0),
WAVE_RGB_COLOR("orange2", 238, 154, 0),
WAVE_RGB_COLOR("orange3", 205, 133, 0),
WAVE_RGB_COLOR("orange4", 139, 90, 0),
WAVE_RGB_COLOR("OrangeRed", 255, 69, 0),
WAVE_RGB_COLOR("OrangeRed1", 255, 69, 0),
WAVE_RGB_COLOR("OrangeRed2", 238, 64, 0),
WAVE_RGB_COLOR("OrangeRed3", 205, 55, 0),
WAVE_RGB_COLOR("OrangeRed4", 139, 37, 0),
WAVE_RGB_COLOR("orchid", 218, 112, 214),
WAVE_RGB_COLOR("orchid1", 255, 131, 250),
WAVE_RGB_COLOR("orchid2", 238, 122, 233),
WAVE_RGB_COLOR("orchid3", 205, 105, 201),
WAVE_RGB_COLOR("orchid4", 139, 71, 137),
WAVE_RGB_COLOR("pale goldenrod", 238, 232, 170),
WAVE_RGB_COLOR("pale green", 152, 251, 152),
WAVE_RGB_COLOR("pale turquoise", 175, 238, 238),
WAVE_RGB_COLOR("pale violet red", 219, 112, 147),
WAVE_RGB_COLOR("PaleGoldenrod", 238, 232, 170),
WAVE_RGB_COLOR("PaleGreen", 152, 251, 152),
WAVE_RGB_COLOR("PaleGreen1", 154, 255, 154),
WAVE_RGB_COLOR("PaleGreen2", 144, 238, 144),
WAVE_RGB_COLOR("PaleGreen3", 124, 205, 124),
WAVE_RGB_COLOR("PaleGreen4", 84, 139, 84),
WAVE_RGB_COLOR("PaleTurquoise", 175, 238, 238),
WAVE_RGB_COLOR("PaleTurquoise1", 187, 255, 255),
WAVE_RGB_COLOR("PaleTurquoise2", 174, 238, 238),
WAVE_RGB_COLOR("PaleTurquoise3", 150, 205, 205),
WAVE_RGB_COLOR("PaleTurquoise4", 102, 139, 139),
WAVE_RGB_COLOR("PaleVioletRed", 219, 112, 147),
WAVE_RGB_COLOR("PaleVioletRed1", 255, 130, 171),
WAVE_RGB_COLOR("PaleVioletRed2", 238, 121, 159),
WAVE_RGB_COLOR("PaleVioletRed3", 205, 104, 137),
WAVE_RGB_COLOR("PaleVioletRed4", 139, 71, 93),
WAVE_RGB_COLOR("papaya whip", 255, 239, 213),
WAVE_RGB_COLOR("PapayaWhip", 255, 239, 213),
WAVE_RGB_COLOR("peach puff", 255, 218, 185),
WAVE_RGB_COLOR("PeachPuff", 255, 218, 185),
WAVE_RGB_COLOR("PeachPuff1", 255, 218, 185),
WAVE_RGB_COLOR("PeachPuff2", 238, 203, 173),
WAVE_RGB_COLOR("PeachPuff3", 205, 175, 149),
WAVE_RGB_COLOR("PeachPuff4", 139, 119, 101),
WAVE_RGB_COLOR("peru", 205, 133, 63),
WAVE_RGB_COLOR("pink", 255, 192, 203),
WAVE_RGB_COLOR("pink1", 255, 181, 197),
WAVE_RGB_COLOR("pink2", 238, 169, 184),
WAVE_RGB_COLOR("pink3", 205, 145, 158),
WAVE_RGB_COLOR("pink4", 139, 99, 108),
WAVE_RGB_COLOR("plum", 221, 160, 221),
WAVE_RGB_COLOR("plum1", 255, 187, 255),
WAVE_RGB_COLOR("plum2", 238, 174, 238),
WAVE_RGB_COLOR("plum3", 205, 150, 205),
WAVE_RGB_COLOR("plum4", 139, 102, 139),
WAVE_RGB_COLOR("powder blue", 176, 224, 230),
WAVE_RGB_COLOR("PowderBlue", 176, 224, 230),
WAVE_RGB_COLOR("purple", 160, 32, 240),
WAVE_RGB_COLOR("purple1", 155, 48, 255),
WAVE_RGB_COLOR("purple2", 145, 44, 238),
WAVE_RGB_COLOR("purple3", 125, 38, 205),
WAVE_RGB_COLOR("purple4", 85, 26, 139),
WAVE_RGB_COLOR("red", 255, 0, 0),
WAVE_RGB_COLOR("red1", 255, 0, 0),
WAVE_RGB_COLOR("red2", 238, 0, 0),
WAVE_RGB_COLOR("red3", 205, 0, 0),
WAVE_RGB_COLOR("red4", 139, 0, 0),
WAVE_RGB_COLOR("rosy brown", 188, 143, 143),
WAVE_RGB_COLOR("RosyBrown", 188, 143, 143),
WAVE_RGB_COLOR("RosyBrown1", 255, 193, 193),
WAVE_RGB_COLOR("RosyBrown2", 238, 180, 180),
WAVE_RGB_COLOR("RosyBrown3", 205, 155, 155),
WAVE_RGB_COLOR("RosyBrown4", 139, 105, 105),
WAVE_RGB_COLOR("royal blue", 65, 105, 225),
WAVE_RGB_COLOR("RoyalBlue", 65, 105, 225),
WAVE_RGB_COLOR("RoyalBlue1", 72, 118, 255),
WAVE_RGB_COLOR("RoyalBlue2", 67, 110, 238),
WAVE_RGB_COLOR("RoyalBlue3", 58, 95, 205),
WAVE_RGB_COLOR("RoyalBlue4", 39, 64, 139),
WAVE_RGB_COLOR("saddle brown", 139, 69, 19),
WAVE_RGB_COLOR("SaddleBrown", 139, 69, 19),
WAVE_RGB_COLOR("salmon", 250, 128, 114),
WAVE_RGB_COLOR("salmon1", 255, 140, 105),
WAVE_RGB_COLOR("salmon2", 238, 130, 98),
WAVE_RGB_COLOR("salmon3", 205, 112, 84),
WAVE_RGB_COLOR("salmon4", 139, 76, 57),
WAVE_RGB_COLOR("sandy brown", 244, 164, 96),
WAVE_RGB_COLOR("SandyBrown", 244, 164, 96),
WAVE_RGB_COLOR("sea green", 46, 139, 87),
WAVE_RGB_COLOR("SeaGreen", 46, 139, 87),
WAVE_RGB_COLOR("SeaGreen1", 84, 255, 159),
WAVE_RGB_COLOR("SeaGreen2", 78, 238, 148),
WAVE_RGB_COLOR("SeaGreen3", 67, 205, 128),
WAVE_RGB_COLOR("SeaGreen4", 46, 139, 87),
WAVE_RGB_COLOR("seashell", 255, 245, 238),
WAVE_RGB_COLOR("seashell1", 255, 245, 238),
WAVE_RGB_COLOR("seashell2", 238, 229, 222),
WAVE_RGB_COLOR("seashell3", 205, 197, 191),
WAVE_RGB_COLOR("seashell4", 139, 134, 130),
WAVE_RGB_COLOR("sienna", 160, 82, 45),
WAVE_RGB_COLOR("sienna1", 255, 130, 71),
WAVE_RGB_COLOR("sienna2", 238, 121, 66),
WAVE_RGB_COLOR("sienna3", 205, 104, 57),
WAVE_RGB_COLOR("sienna4", 139, 71, 38),
WAVE_RGB_COLOR("sky blue", 135, 206, 235),
WAVE_RGB_COLOR("SkyBlue", 135, 206, 235),
WAVE_RGB_COLOR("SkyBlue1", 135, 206, 255),
WAVE_RGB_COLOR("SkyBlue2", 126, 192, 238),
WAVE_RGB_COLOR("SkyBlue3", 108, 166, 205),
WAVE_RGB_COLOR("SkyBlue4", 74, 112, 139),
WAVE_RGB_COLOR("slate blue", 106, 90, 205),
WAVE_RGB_COLOR("slate gray", 112, 128, 144),
WAVE_RGB_COLOR("slate grey", 112, 128, 144),
WAVE_RGB_COLOR("SlateBlue", 106, 90, 205),
WAVE_RGB_COLOR("SlateBlue1", 131, 111, 255),
WAVE_RGB_COLOR("SlateBlue2", 122, 103, 238),
WAVE_RGB_COLOR("SlateBlue3", 105, 89, 205),
WAVE_RGB_COLOR("SlateBlue4", 71, 60, 139),
WAVE_RGB_COLOR("SlateGray", 112, 128, 144),
WAVE_RGB_COLOR("SlateGray1", 198, 226, 255),
WAVE_RGB_COLOR("SlateGray2", 185, 211, 238),
WAVE_RGB_COLOR("SlateGray3", 159, 182, 205),
WAVE_RGB_COLOR("SlateGray4", 108, 123, 139),
WAVE_RGB_COLOR("SlateGrey", 112, 128, 144),
WAVE_RGB_COLOR("snow", 255, 250, 250),
WAVE_RGB_COLOR("snow1", 255, 250, 250),
WAVE_RGB_COLOR("snow2", 238, 233, 233),
WAVE_RGB_COLOR("snow3", 205, 201, 201),
WAVE_RGB_COLOR("snow4", 139, 137, 137),
WAVE_RGB_COLOR("spring green", 0, 255, 127),
WAVE_RGB_COLOR("SpringGreen", 0, 255, 127),
WAVE_RGB_COLOR("SpringGreen1", 0, 255, 127),
WAVE_RGB_COLOR("SpringGreen2", 0, 238, 118),
WAVE_RGB_COLOR("SpringGreen3", 0, 205, 102),
WAVE_RGB_COLOR("SpringGreen4", 0, 139, 69),
WAVE_RGB_COLOR("steel blue", 70, 130, 180),
WAVE_RGB_COLOR("SteelBlue", 70, 130, 180),
WAVE_RGB_COLOR("SteelBlue1", 99, 184, 255),
WAVE_RGB_COLOR("SteelBlue2", 92, 172, 238),
WAVE_RGB_COLOR("SteelBlue3", 79, 148, 205),
WAVE_RGB_COLOR("SteelBlue4", 54, 100, 139),
WAVE_RGB_COLOR("tan", 210, 180, 140),
WAVE_RGB_COLOR("tan1", 255, 165, 79),
WAVE_RGB_COLOR("tan2", 238, 154, 73),
WAVE_RGB_COLOR("tan3", 205, 133, 63),
WAVE_RGB_COLOR("tan4", 139, 90, 43),
WAVE_RGB_COLOR("thistle", 216, 191, 216),
WAVE_RGB_COLOR("thistle1", 255, 225, 255),
WAVE_RGB_COLOR("thistle2", 238, 210, 238),
WAVE_RGB_COLOR("thistle3", 205, 181, 205),
WAVE_RGB_COLOR("thistle4", 139, 123, 139),
WAVE_RGB_COLOR("tomato", 255, 99, 71),
WAVE_RGB_COLOR("tomato1", 255, 99, 71),
WAVE_RGB_COLOR("tomato2", 238, 92, 66),
WAVE_RGB_COLOR("tomato3", 205, 79, 57),
WAVE_RGB_COLOR("tomato4", 139, 54, 38),
WAVE_RGB_COLOR("turquoise", 64, 224, 208),
WAVE_RGB_COLOR("turquoise1", 0, 245, 255),
WAVE_RGB_COLOR("turquoise2", 0, 229, 238),
WAVE_RGB_COLOR("turquoise3", 0, 197, 205),
WAVE_RGB_COLOR("turquoise4", 0, 134, 139),
WAVE_RGB_COLOR("violet", 238, 130, 238),
WAVE_RGB_COLOR("violet red", 208, 32, 144),
WAVE_RGB_COLOR("VioletRed", 208, 32, 144),
WAVE_RGB_COLOR("VioletRed1", 255, 62, 150),
WAVE_RGB_COLOR("VioletRed2", 238, 58, 140),
WAVE_RGB_COLOR("VioletRed3", 205, 50, 120),
WAVE_RGB_COLOR("VioletRed4", 139, 34, 82),
WAVE_RGB_COLOR("wheat", 245, 222, 179),
WAVE_RGB_COLOR("wheat1", 255, 231, 186),
WAVE_RGB_COLOR("wheat2", 238, 216, 174),
WAVE_RGB_COLOR("wheat3", 205, 186, 150),
WAVE_RGB_COLOR("wheat4", 139, 126, 102),
WAVE_RGB_COLOR("white", 255, 255, 255),
WAVE_RGB_COLOR("white smoke", 245, 245, 245),
WAVE_RGB_COLOR("WhiteSmoke", 245, 245, 245),
WAVE_RGB_COLOR("yellow", 255, 255, 0),
WAVE_RGB_COLOR("yellow green", 154, 205, 50),
WAVE_RGB_COLOR("yellow1", 255, 255, 0),
WAVE_RGB_COLOR("yellow2", 238, 238, 0),
WAVE_RGB_COLOR("yellow3", 205, 205, 0),
WAVE_RGB_COLOR("yellow4", 139, 139, 0),
WAVE_RGB_COLOR("YellowGreen", 154, 205, 50),
};
'''

@ -0,0 +1,56 @@
#!/usr/bin/python3
# gtkwave process filter
#
# display valid+anything else (inc. just valid)
#
# format=binary so justification and data length don't matter
# valid is on left

import sys

colorI = ''
colorV = '?DarkBlue?'
colorX = '?red?'

fi = sys.stdin
fo = sys.stdout
fe = sys.stderr

debug = False

def dbg(m):
if debug:
fe.write(m + '\n')
fe.flush()

def main():

while True:

line = fi.readline()
if not line:
return 0

try:
if line[0] == 'x' or line[0] == 'z':
fo.write(f'{colorX}{line[0]}\n')
elif line[0] == '0':
if len(line) > 2:
fo.write(f'{colorI}{int(line[1:],2):02X}\n')
else:
fo.write(f'{colorI}\n')
else:
if len(line) > 2:
fo.write(f'{colorV}{int(line[1:],2):02X}\n')
else:
fo.write(f'{colorV}\n')

except Exception as e:
fe.write('error!\n')
fe.write(str(e))
fo.write('filter error!\n')

fo.flush()

if __name__ == '__main__':
sys.exit(main())

@ -0,0 +1,33 @@
# init for a2o

# install acts on highlighted traces; filter=0 uninstalls

#set which_f [gtkwave::setCurrentTranslateFile ./gtkf-alias.py]
#puts "$which_f"
#gtkwave::installFileFilter $which_f

#set which_f [gtkwave::setCurrentTranslateProc ./gtkf-ppc.py]
#puts "$which_f"
#gtkwave::installProcFilter $which_f

set sigs [gtkwave::getDisplayedSignals]
puts "$sigs"

# cant figure out how to unhighlight all; somehow it is remembering after reinvoke
# unhighlight all
foreach sig $sigs {
puts "$sig off"
gtkwave::setTraceHighlightFromNameMatch $sig off
}

# highlight bus
set h [list {A2L2_AC_AN}] ;# combined - does it work?
set n [gtkwave::highlightSignalsFromList $h]

if {$h > 0} {
set f [gtkwave::setCurrentTranslateTransProc ./gtkf-a2l2.py]
gtkwave::installTransFilter $f
} else {
puts "Didn't apply trans filter to [lindex $h 0]"
}

@ -0,0 +1,2 @@
color_value white
force_toolbars on

@ -0,0 +1,982 @@
48000400
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000CE0
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000A00
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480000BC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7CBE6AA6
2C250000
408200EC
3C608C00
3800001F
38400015
38800000
3900025F
7C7CFBA6
7C4011A6
7C8009A6
7D0001A6
4C00012C
81400A08
3800001E
3C801000
3900025F
65081000
7D4011A6
7C8009A6
7D0001A6
4C00012C
3C608800
3800000F
3840003F
38800000
3900025F
7C7CFBA6
7C4011A6
7C8009A6
7D0001A6
4C00012C
3800000D
3C801000
3900025F
65081000
7D4011A6
7C8009A6
7D0001A6
4C00012C
81400A00
7D400124
4C00012C
3C200300
7C334BA6
38200000
7C3603A6
7C3D43A6
7C3C43A6
3C40FE00
7C5053A6
7C56FAA6
70420200
7C56FBA6
7C3053A6
7C3453A6
80200A04
7021000F
7C366BA6
4C00012C
48000014
81400A00
7D400124
4C00012C
48000004
80200A04
74218000
40820008
480006F1
80200A04
3C407FFF
6042FFFF
7C211038
90200A04
7CBE6AA6
78A53664
38A50A80
81650000
E9850008
E9A50010
80200A04
70210010
4182001C
80400A0C
3C204400
60210012
F8220000
7C2803A6
48000014
48000005
7C2802A6
38210030
7C2803A6
7D7B03A6
7DBA03A6
7D816378
7C7E6AA6
7C4C42A6
F8450030
4C000064
60000000
60000000
60000000
44000022
7CBE6AA6
78A53664
38A50A80
7C4C42A6
F8450038
2C230000
41820148
48000044
48000040
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480000FC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480000FC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480001DC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
8002B000
80000001
000000BF
10000000
48000070
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
8002F000
00000000
00000000
1003FF00
00000000
100004B0
00000000
10030000
00000000
10031FFF
00000000
10030000
00000000
00000000
00000000
00000000
8002F000
00000000
00000000
1003DF00
00000000
100004B0
00000000
10032000
00000000
10033FFF
00000000
10032000
00000000
00000000
00000000
00000000
8002F000
00000000
00000000
1003BF00
00000000
100004B0
00000000
10034000
00000000
10035FFF
00000000
10034000
00000000
00000000
00000000
00000000
8002F000
00000000
00000000
10039F00
00000000
100004B0
00000000
10036000
00000000
10037FFF
00000000
10036000
00000000
00000000
00000000
00000000
48000080
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7CBE6AA6
78A53664
38A50A80
38C50018
E8E60000
38C50020
E9060000
7D074050
39080001
7D0903A6
38C00000
7CE83B78
98C80000
39080001
4200FFF8
39050028
F8E80000
4E800020
480000B8
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
80000A00
7C000124
4C00012C
4BFFF894
480000F0
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7C0802A6
2C230001
41820038
2C230010
41820070
2C230100
418200A8
2C230107
41820120
3860FFFF
7C0803A6
4C000064
60000000
60000000
60000000
60000000
7C7E6AA6
4C000064
48000038
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7C6C42A6
4C000064
48000038
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7CBE6AA6
78A53664
38A50A80
38C50028
E8E60000
98870000
38E70001
39050020
E9080000
7C274000
38600000
40810010
39050018
E8E80000
3860FFFF
F8E60000
4C000064
4800003C
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7C6902A6
4BFFFCBD
7C6903A6
7C0803A6
38600000
4C000064

@ -0,0 +1,982 @@
48000400
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000CE0
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000A00
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480000BC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7CBE6AA6
2C250000
408200EC
3C608C00
3800001F
38400415
38800000
3900025F
7C7CFBA6
7C4011A6
7C8009A6
7D0001A6
4C00012C
81400A08
3800001E
3C801000
3900025F
65081000
7D4011A6
7C8009A6
7D0001A6
4C00012C
3C608800
3800000F
3840043F
38800000
3900025F
7C7CFBA6
7C4011A6
7C8009A6
7D0001A6
4C00012C
3800000D
3C801000
3900025F
65081000
7D4011A6
7C8009A6
7D0001A6
4C00012C
81400A00
7D400124
4C00012C
3C200300
7C334BA6
38200000
7C3603A6
7C3D43A6
7C3C43A6
3C40FE00
7C5053A6
7C56FAA6
70420200
7C56FBA6
7C3053A6
7C3453A6
80200A04
7021000F
7C366BA6
4C00012C
48000014
81400A00
7D400124
4C00012C
48000004
80200A04
74218000
40820008
480006F1
80200A04
3C407FFF
6042FFFF
7C211038
90200A04
7CBE6AA6
78A53664
38A50A80
81650000
E9850008
E9A50010
80200A04
70210010
4182001C
80400A0C
3C204400
60210012
F8220000
7C2803A6
48000014
48000005
7C2802A6
38210030
7C2803A6
7D7B03A6
7DBA03A6
7D816378
7C7E6AA6
7C4C42A6
F8450030
4C000064
60000000
60000000
60000000
44000022
7CBE6AA6
78A53664
38A50A80
7C4C42A6
F8450038
2C230000
41820148
48000044
48000040
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480000FC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480000FC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480001DC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
8002B000
80000001
000000BF
10000000
48000070
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
8002F000
00000000
00000000
1003FF00
00000000
100004B0
00000000
10030000
00000000
10031FFF
00000000
10030000
00000000
00000000
00000000
00000000
8002F000
00000000
00000000
1003DF00
00000000
100004B0
00000000
10032000
00000000
10033FFF
00000000
10032000
00000000
00000000
00000000
00000000
8002F000
00000000
00000000
1003BF00
00000000
100004B0
00000000
10034000
00000000
10035FFF
00000000
10034000
00000000
00000000
00000000
00000000
8002F000
00000000
00000000
10039F00
00000000
100004B0
00000000
10036000
00000000
10037FFF
00000000
10036000
00000000
00000000
00000000
00000000
48000080
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7CBE6AA6
78A53664
38A50A80
38C50018
E8E60000
38C50020
E9060000
7D074050
39080001
7D0903A6
38C00000
7CE83B78
98C80000
39080001
4200FFF8
39050028
F8E80000
4E800020
480000B8
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
80000A00
7C000124
4C00012C
4BFFF894
480000F0
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7C0802A6
2C230001
41820038
2C230010
41820070
2C230100
418200A8
2C230107
41820120
3860FFFF
7C0803A6
4C000064
60000000
60000000
60000000
60000000
7C7E6AA6
4C000064
48000038
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7C6C42A6
4C000064
48000038
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7CBE6AA6
78A53664
38A50A80
38C50028
E8E60000
98870000
38E70001
39050020
E9080000
7C274000
38600000
40810010
39050018
E8E80000
3860FFFF
F8E60000
4C000064
4800003C
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7C6902A6
4BFFFCBD
7C6903A6
7C0803A6
38600000
4C000064

@ -0,0 +1,982 @@
48000400
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000CE0
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000A00
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480000BC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7CBE6AA6
2C250000
408200EC
3C608C00
3800001F
38400015
38800000
3900025F
7C7CFBA6
7C4011A6
7C8009A6
7D0001A6
4C00012C
81400A08
3800001E
3C801000
3900025F
65081000
7D4011A6
7C8009A6
7D0001A6
4C00012C
3C608800
3800000F
3840003F
38800000
3900025F
7C7CFBA6
7C4011A6
7C8009A6
7D0001A6
4C00012C
3800000D
3C801000
3900025F
65081000
7D4011A6
7C8009A6
7D0001A6
4C00012C
81400A00
7D400124
4C00012C
3C200300
7C334BA6
38200000
7C3603A6
7C3D43A6
7C3C43A6
3C40FE00
7C5053A6
7C56FAA6
70420200
7C56FBA6
7C3053A6
7C3453A6
80200A04
7021000F
7C366BA6
4C00012C
48000014
81400A00
7D400124
4C00012C
48000004
80200A04
74218000
40820008
480006F1
80200A04
3C407FFF
6042FFFF
7C211038
90200A04
7CBE6AA6
78A53664
38A50A80
81650000
E9850008
E9A50010
80200A04
70210010
4182001C
80400A0C
3C204400
60210012
F8220000
7C2803A6
48000014
48000005
7C2802A6
38210030
7C2803A6
7D7B03A6
7DBA03A6
7D816378
7C7E6AA6
7C4C42A6
F8450030
4C000064
60000000
60000000
60000000
44000022
7CBE6AA6
78A53664
38A50A80
7C4C42A6
F8450038
2C230000
41820148
48000044
48000040
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480000FC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480000FC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480001DC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
8002B000
80000001
000000BF
10000000
48000070
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
8002F000
00000000
00000000
1003FF00
00000000
100004B0
00000000
10030000
00000000
10031FFF
00000000
10030000
00000000
00000000
00000000
00000000
8002F000
00000000
00000000
1003DF00
00000000
100004B0
00000000
10032000
00000000
10033FFF
00000000
10032000
00000000
00000000
00000000
00000000
8002F000
00000000
00000000
1003BF00
00000000
100004B0
00000000
10034000
00000000
10035FFF
00000000
10034000
00000000
00000000
00000000
00000000
8002F000
00000000
00000000
10039F00
00000000
100004B0
00000000
10036000
00000000
10037FFF
00000000
10036000
00000000
00000000
00000000
00000000
48000080
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7CBE6AA6
78A53664
38A50A80
38C50018
E8E60000
38C50020
E9060000
7D074050
39080001
7D0903A6
38C00000
7CE83B78
98C80000
39080001
4200FFF8
39050028
F8E80000
4E800020
480000B8
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
80000A00
7C000124
4C00012C
4BFFF894
480000F0
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7C0802A6
2C230001
41820038
2C230010
41820070
2C230100
418200A8
2C230107
41820120
3860FFFF
7C0803A6
4C000064
60000000
60000000
60000000
60000000
7C7E6AA6
4C000064
48000038
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7C6C42A6
4C000064
48000038
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7CBE6AA6
78A53664
38A50A80
38C50028
E8E60000
98870000
38E70001
39050020
E9080000
7C274000
38600000
40810010
39050018
E8E80000
3860FFFF
F8E60000
4C000064
4800003C
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7C6902A6
4BFFFCBD
7C6903A6
7C0803A6
38600000
4C000064

@ -0,0 +1,127 @@
# Simulation

Building with cocotb, verilator, icarus...

```
cd coco
```

## cocotb + Icarus

* A2L2 python interface partially implemented
* original boot code makes it to jump to (missing) test
* makegtkw creates netlist

```
make -f Makefile.icarus run
...
7353.00ns INFO [00000919] C0: CP 0:00056C 000000000000056C
7369.00ns INFO [00000921] C0: CP 0:000570 0000000000000570
7377.00ns INFO [00000922] RELD tag=08 48000000480000FC6000000060000000 1of4 crit
7385.00ns INFO [00000923] RELD tag=08 60000000600000006000000060000000 2of4
7393.00ns INFO [00000924] RELD tag=08 60000000600000006000000060000000 3of4
7401.00ns INFO [00000925] RELD tag=08 60000000600000006000000060000000 4of4
7433.00ns INFO [00000929] T0 IFETCH 00000640 tag=09 len=6 WIMG:0 reld data:935
7481.00ns INFO [00000935] RELD tag=09 60000000600000006000000060000000 1of4 crit
7481.00ns INFO [00000935] C0: CP 0:000574 0000000000000574
7489.00ns INFO [00000936] RELD tag=09 60000000600000006000000060000000 2of4
7497.00ns INFO [00000937] RELD tag=09 60000000600000006000000060000000 3of4
7505.00ns INFO [00000938] RELD tag=09 60000000600000006000000060000000 4of4
7593.00ns INFO [00000949] C0: CP 0:000578 1:00057C 0000000000000578
7697.00ns INFO [00000962] C0: CP 0:000580 0000000000000580
7793.00ns INFO [00000974] C0: CP 0:000584 0000000000000584
7801.00ns INFO [00000975] T0 IFETCH 00000700 tag=08 len=6 WIMG:0 reld data:981
7849.00ns INFO [00000981] RELD tag=08 48000000480000FC6000000060000000 1of4 crit
7857.00ns INFO [00000982] RELD tag=08 60000000600000006000000060000000 2of4
7857.00ns INFO [00000982] C0: CP 0:000588 1:00058C 0000000000000588
7865.00ns INFO [00000983] RELD tag=08 60000000600000006000000060000000 3of4
7873.00ns INFO [00000984] RELD tag=08 60000000600000006000000060000000 4of4
7905.00ns INFO [00000988] T0 IFETCH 00000740 tag=09 len=6 WIMG:0 reld data:994
7953.00ns INFO [00000994] RELD tag=09 60000000600000006000000060000000 1of4 crit
7961.00ns INFO [00000995] RELD tag=09 60000000600000006000000060000000 2of4
7969.00ns INFO [00000996] RELD tag=09 60000000600000006000000060000000 3of4
7977.00ns INFO [00000997] RELD tag=09 60000000600000006000000060000000 4of4
8001.00ns INFO [00001000] ...tick...
8009.00ns INFO [00001001] T0 IFETCH 100004B0 tag=08 len=6 LE WIMG:0 reld data:1007
8057.00ns INFO [00001007] RELD tag=08 00000000000000000000000000000000 1of4
8065.00ns INFO [00001008] RELD tag=08 00000000000000000000000000000000 2of4
8073.00ns INFO [00001009] RELD tag=08 00000000000000000000000000000000 3of4
8081.00ns INFO [00001010] RELD tag=08 00000000000000000000000000000000 4of4 crit
8113.00ns INFO [00001014] T0 IFETCH 100004C0 tag=09 len=6 LE WIMG:0 reld data:1020
8161.00ns INFO [00001020] RELD tag=09 00000000000000000000000000000000 1of4 crit
8169.00ns INFO [00001021] RELD tag=09 00000000000000000000000000000000 2of4
8177.00ns INFO [00001022] RELD tag=09 00000000000000000000000000000000 3of4
8185.00ns INFO [00001023] RELD tag=09 00000000000000000000000000000000 4of4
8257.00ns INFO [00001032] T0 IFETCH 000000E0 tag=08 len=6 WIMG:0 reld data:1038
8257.00ns INFO Test stopped by this forked coroutine
8257.00ns INFO tb failed
Traceback (most recent call last):
File "/home/wtf/projects/a2o-opf/dev/sim/coco/A2L2.py", line 405, in A2L2Monitor
assert False, (f'{me}: Bad IFetch @={ra:08X}') #wtf want this to end back in main code for summary
AssertionError: A2L2 Monitor: Bad IFetch @=000000E0
8257.00ns INFO **************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
**************************************************************************************
** tb.tb FAIL 8257.00 154.07 53.59 **
**************************************************************************************
** TESTS=0 PASS=0 FAIL=1 SKIP=0 8257.00 154.09 53.58 **
**************************************************************************************


```

## Verilator (can't build with coco so far)


* build and run a few hardcoded ops

```
verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims c.v tb.cpp
make -C obj_dir -f Vc.mk Vc
obj_dir/Vc
Tracing enabled.
00000001Resetting...
00000001Thread stop=3
00000011Releasing reset.
00000201Thread stop=0
00000213 ac_an_req: T0 ra=FFFFFFF0
00000216 an_ac_rsp: data=00000000000000000000000048000002
00000236 ac_an_req: T0 ra=00000000
00000239 an_ac_rsp: data=48000400000000000000000000000000
00000251 ac_an_req: T0 ra=00000400
00000254 an_ac_rsp: data=382000017C366BA67C366BA67C3E6AA6
00000263 ac_an_req: T0 ra=00000410
00000266 an_ac_rsp: data=4C00012C2C0100003820066041820008
00000275 ac_an_req: T0 ra=00000420
00000278 an_ac_rsp: data=382101007C2903A64E80042000000000
00000287 ac_an_req: T0 ra=00000430
00000290 an_ac_rsp: data=00000000000000000000000000000000
00000299 ac_an_req: T0 ra=00000440
00000302 an_ac_rsp: data=00000000000000000000000000000000
00000311 ac_an_req: T0 ra=00000450
00000314 an_ac_rsp: data=00000000000000000000000000000000
00000319 ac_an_req: T0 ra=00000410
00000322 an_ac_rsp: data=4C00012C2C0100003820066041820008
00000331 ac_an_req: T0 ra=00000420
00000334 an_ac_rsp: data=382101007C2903A64E80042000000000
00000344 ac_an_req: T0 ra=00000420
00000347 an_ac_rsp: data=382101007C2903A64E80042000000000
00000356 ac_an_req: T0 ra=00000430
00000359 an_ac_rsp: data=00000000000000000000000000000000
00000369 ac_an_req: T0 ra=00000660
00000372 an_ac_rsp: data=48000040000000000000000000000000
00000384 ac_an_req: T0 ra=000006A0
00000387 an_ac_rsp: data=48000040000000000000000000000000
00000399 ac_an_req: T0 ra=000006E0
00000402 an_ac_rsp: data=48000040000000000000000000000000
00000414 ac_an_req: T0 ra=00000720
00000417 an_ac_rsp: data=48000040000000000000000000000000
00000429 ac_an_req: T0 ra=00000760
00000432 an_ac_rsp: data=48000040000000000000000000000000
00000444 ac_an_req: T0 ra=000007A0
00000447 an_ac_rsp: data=48000040000000000000000000000000
00000459 ac_an_req: T0 ra=000007E0
00000462 an_ac_rsp: data=48000040000000000000000000000000
00000474 ac_an_req: T0 ra=00000820
...
```

Binary file not shown.

@ -0,0 +1,982 @@
48000400
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000CE0
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000A00
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480000BC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7CBE6AA6
2C250000
408200EC
3C608C00
3800001F
38400015
38800000
3900025F
7C7CFBA6
7C4011A6
7C8009A6
7D0001A6
4C00012C
81400A08
3800001E
3C801000
3900025F
65081000
7D4011A6
7C8009A6
7D0001A6
4C00012C
3C608800
3800000F
3840003F
38800000
3900025F
7C7CFBA6
7C4011A6
7C8009A6
7D0001A6
4C00012C
3800000D
3C801000
3900025F
65081000
7D4011A6
7C8009A6
7D0001A6
4C00012C
81400A00
7D400124
4C00012C
3C200300
7C334BA6
38200000
7C3603A6
7C3D43A6
7C3C43A6
3C40FE00
7C5053A6
7C56FAA6
70420200
7C56FBA6
7C3053A6
7C3453A6
80200A04
7021000F
7C366BA6
4C00012C
48000014
81400A00
7D400124
4C00012C
48000004
80200A04
74218000
40820008
480006F1
80200A04
3C407FFF
6042FFFF
7C211038
90200A04
7CBE6AA6
78A53664
38A50A80
81650000
E9850008
E9A50010
80200A04
70210010
4182001C
80400A0C
3C204400
60210012
F8220000
7C2803A6
48000014
48000005
7C2802A6
38210030
7C2803A6
7D7B03A6
7DBA03A6
7D816378
7C7E6AA6
7C4C42A6
F8450030
4C000064
60000000
60000000
60000000
44000022
7CBE6AA6
78A53664
38A50A80
7C4C42A6
F8450038
2C230000
41820148
48000044
48000040
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480000FC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480000FC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
48000000
4800001C
60000000
60000000
60000000
60000000
60000000
60000000
48000000
480001DC
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
8002B000
80000001
000000BF
10000000
48000070
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
8002F000
00000000
00000000
1003FF00
00000000
100004B0
00000000
10030000
00000000
10031FFF
00000000
10030000
00000000
00000000
00000000
00000000
8002F000
00000000
00000000
1003DF00
00000000
100004B0
00000000
10032000
00000000
10033FFF
00000000
10032000
00000000
00000000
00000000
00000000
8002F000
00000000
00000000
1003BF00
00000000
100004B0
00000000
10034000
00000000
10035FFF
00000000
10034000
00000000
00000000
00000000
00000000
8002F000
00000000
00000000
10039F00
00000000
100004B0
00000000
10036000
00000000
10037FFF
00000000
10036000
00000000
00000000
00000000
00000000
48000080
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7CBE6AA6
78A53664
38A50A80
38C50018
E8E60000
38C50020
E9060000
7D074050
39080001
7D0903A6
38C00000
7CE83B78
98C80000
39080001
4200FFF8
39050028
F8E80000
4E800020
480000B8
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
80000A00
7C000124
4C00012C
4BFFF894
480000F0
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7C0802A6
2C230001
41820038
2C230010
41820070
2C230100
418200A8
2C230107
41820120
3860FFFF
7C0803A6
4C000064
60000000
60000000
60000000
60000000
7C7E6AA6
4C000064
48000038
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7C6C42A6
4C000064
48000038
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7CBE6AA6
78A53664
38A50A80
38C50028
E8E60000
98870000
38E70001
39050020
E9080000
7C274000
38600000
40810010
39050018
E8E80000
3860FFFF
F8E60000
4C000064
4800003C
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
60000000
7C6902A6
4BFFFCBD
7C6903A6
7C0803A6
38600000
4C000064

@ -0,0 +1,3 @@

boot: file format elf32-powerpc

@ -0,0 +1,913 @@
1 # © IBM Corp. 2020
2 # Licensed under and subject to the terms of the CC-BY 4.0
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
4 # Additional rights, including the right to physically implement a softcore
5 # that is compliant with the required sections of the Power ISA
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
7 # This README will be updated with additional information when OpenPOWER's
8 # license is available.
9
10 # boot kernel
11 # set up translations
12 # set up timer facilities
13 # set up threads
14 # call user code
15 # process user rc
16
17 # todo:
18 # 1. skip_printf_init flag should be threaded
19
20 .include "defines.s"
1 # © IBM Corp. 2020
2 # Licensed under and subject to the terms of the CC-BY 4.0
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
4 # Additional rights, including the right to physically implement a softcore
5 # that is compliant with the required sections of the Power ISA
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
7 # This README will be updated with additional information when OpenPOWER's
8 # license is available.
9
10 #-----------------------------------------
11 # Defines
12 #-----------------------------------------
13
14 # Regs
15
16 .set r0, 0
17 .set r1, 1
18 .set r2, 2
19 .set r3, 3
20 .set r4, 4
21 .set r5, 5
22 .set r6, 6
23 .set r7, 7
24 .set r8, 8
25 .set r9, 9
26 .set r10,10
27 .set r11,11
28 .set r12,12
29 .set r13,13
30 .set r14,14
31 .set r15,15
32 .set r16,16
33 .set r17,17
34 .set r18,18
35 .set r19,19
36 .set r20,20
37 .set r21,21
38 .set r22,22
39 .set r23,23
40 .set r24,24
41 .set r25,25
42 .set r26,26
43 .set r27,27
44 .set r28,28
45 .set r29,29
46 .set r30,30
47 .set r31,31
48
49 .set f0, 0
50 .set f1, 1
51 .set f2, 2
52 .set f3, 3
53 .set f4, 4
54 .set f5, 5
55 .set f6, 6
56 .set f7, 7
57 .set f8, 8
58 .set f9, 9
59 .set f10,10
60 .set f11,11
61 .set f12,12
62 .set f13,13
63 .set f14,14
64 .set f15,15
65 .set f16,16
66 .set f17,17
67 .set f18,18
68 .set f19,19
69 .set f20,20
70 .set f21,21
71 .set f22,22
72 .set f23,23
73 .set f24,24
74 .set f25,25
75 .set f26,26
76 .set f27,27
77 .set f28,28
78 .set f29,29
79 .set f30,30
80 .set f31,31
81
82 .set cr0, 0
83 .set cr1, 1
84 .set cr2, 2
85 .set cr3, 3
86 .set cr4, 4
87 .set cr5, 5
88 .set cr6, 6
89 .set cr7, 7
90
91 # SPR numbers
92
93 .set srr0, 26
94 .set srr1, 27
95 .set epcr, 307
96 .set tar, 815
97
98 .set dbsr, 304
99 .set dbcr0, 308
100 .set dbcr1, 309
101 .set dbcr2, 310
102 .set dbcr3, 848
103
104 .set ivpr, 63
105
106 .set iucr0, 1011
107 .set iucr1, 883
108 .set iucr2, 884
109
110 .set iudbg0, 888
111 .set iudbg1, 889
112 .set iudbg2, 890
113 .set iulfsr, 891
114 .set iullcr, 892
115
116 .set mmucr0, 1020
117 .set mmucr1, 1021
118 .set mmucr2, 1022
119 .set mmucr3, 1023
120
121 .set tb, 268
122 .set tbl, 284
123 .set tbh, 285
124
125 .set dec, 22
126 .set udec, 550
127 .set tsr, 336
128 .set tcr, 340
129
130 .set xucr0, 1014
131 .set xucr1, 851
132 .set xucr2, 1016
133 .set xucr3, 852
134 .set xucr4, 853
135
136 .set tens, 438
137 .set tenc, 439
138 .set tensr, 437
139
140 .set pid, 48
141 .set pir, 286
142 .set pvr, 287
143 .set tir, 446
144
21
22 .section .text
23 start:
24
25 int_000:
26 0000 48000400 b boot_start
27
28 # critical input
29 0004 4800001C .align 5
29 60000000
29 60000000
29 60000000
29 60000000
30 int_020:
31 0020 48000000 b .
32
33 # debug
34 0024 4800001C .align 5
34 60000000
34 60000000
34 60000000
34 60000000
35 int_040:
36 0040 48000000 b .
37
38 # dsi
39 0044 4800001C .align 5
39 60000000
39 60000000
39 60000000
39 60000000
40 int_060:
41 0060 48000000 b .
42
43 # isi
44 0064 4800001C .align 5
44 60000000
44 60000000
44 60000000
44 60000000
45 int_080:
46 0080 48000000 b .
47
48 # external
49 0084 4800001C .align 5
49 60000000
49 60000000
49 60000000
49 60000000
50 int_0A0:
51 00a0 48000000 b .
52
53 # alignment
54 00a4 4800001C .align 5
54 60000000
54 60000000
54 60000000
54 60000000
55 int_0C0:
56 00c0 48000000 b .
57
58 # program
59 00c4 4800001C .align 5
59 60000000
59 60000000
59 60000000
59 60000000
60 int_0E0:
61 00e0 48000000 b .
62
63 # fp unavailable
64 00e4 4800001C .align 5
64 60000000
64 60000000
64 60000000
64 60000000
65 int_100:
66 0100 48000000 b .
67
68 # sc
69 0104 4800001C .align 5
69 60000000
69 60000000
69 60000000
69 60000000
70 int_120:
71 0120 48000CE0 b int_120_handler
72
73 # apu unavailable
74 0124 4800001C .align 5
74 60000000
74 60000000
74 60000000
74 60000000
75 int_140:
76 0140 48000000 b .
77
78 # decrementer
79 0144 4800001C .align 5
79 60000000
79 60000000
79 60000000
79 60000000
80 int_160:
81 0160 48000000 b .
82
83 # fit
84 0164 4800001C .align 5
84 60000000
84 60000000
84 60000000
84 60000000
85 int_180:
86 0180 48000000 b .
87
88 # watchdog
89 0184 4800001C .align 5
89 60000000
89 60000000
89 60000000
89 60000000
90 int_1A0:
91 01a0 48000000 b .
92
93 # dtlb
94 01a4 4800001C .align 5
94 60000000
94 60000000
94 60000000
94 60000000
95 int_1C0:
96 01c0 48000000 b .
97
98 # itlb
99 01c4 4800001C .align 5
99 60000000
99 60000000
99 60000000
99 60000000
100 int_1E0:
101 01e0 48000000 b .
102
103 # vector unavailable
104 01e4 4800001C .align 5
104 60000000
104 60000000
104 60000000
104 60000000
105 int_200:
106 0200 48000000 b .
107
108 #
109 0204 4800001C .align 5
109 60000000
109 60000000
109 60000000
109 60000000
110 int_220:
111 0220 48000000 b .
112
113 #
114 0224 4800001C .align 5
114 60000000
114 60000000
114 60000000
114 60000000
115 int_240:
116 0240 48000000 b .
117
118 #
119 0244 4800001C .align 5
119 60000000
119 60000000
119 60000000
119 60000000
120 int_260:
121 0260 48000000 b .
122
123 # doorbell
124 0264 4800001C .align 5
124 60000000
124 60000000
124 60000000
124 60000000
125 int_280:
126 0280 48000000 b .
127
128 # doorbell critical
129 0284 4800001C .align 5
129 60000000
129 60000000
129 60000000
129 60000000
130 int_2A0:
131 02a0 48000000 b .
132
133 # doorbell guest
134 02a4 4800001C .align 5
134 60000000
134 60000000
134 60000000
134 60000000
135 int_2C0:
136 02c0 48000000 b .
137
138 # doorbell guest critical
139 02c4 4800001C .align 5
139 60000000
139 60000000
139 60000000
139 60000000
140 int_2E0:
141 02e0 48000000 b .
142
143 # hvsc
144 02e4 4800001C .align 8
144 60000000
144 60000000
144 60000000
144 60000000
145 int_300:
146 0300 48000A00 b int_300_handler
147
148 # hvpriv
149 0304 4800001C .align 5
149 60000000
149 60000000
149 60000000
149 60000000
150 int_320:
151 0320 48000000 b .
152
153 # lrat
154 0324 4800001C .align 5
154 60000000
154 60000000
154 60000000
154 60000000
155 int_340:
156 0340 48000000 b .
157
158 # -------------------------------------------------------------------------------------------------
159 # initial translation
160 # both erats:
161 # 00000000 1M: (boot)
162 # 10000000 1M: (test)
163
164 0344 480000BC .align 8
164 60000000
164 60000000
164 60000000
164 60000000
165 boot_start:
166
167 0400 7CBE6AA6 mfspr r5,tir # who am i?
168 0404 2C250000 cmpdi r5,0x00 # skip unless T0
169 0408 408200EC bne init_t123
170
171 040c 3C608C00 lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
172 # derat 31 @00000000
173
174 0410 3800001F li r0,0x001F # entry #31
175 0414 38400015 li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
176 0418 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
177 041c 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
178
179 0420 7C7CFBA6 mtspr mmucr0,r3
180 0424 7C4011A6 eratwe r2,r0,2
181 0428 7C8009A6 eratwe r4,r0,1
182 042c 7D0001A6 eratwe r8,r0,0
183 0430 4C00012C isync
184
185 0434 81400A08 lwz r10,CONFIG+S_ERATW2(r0) # load parms for erat settings
186
187 # derat 30 @100000000
188
189 0438 3800001E li r0,0x001E # entry #30
190 043c 3C801000 lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
191 0440 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
192 0444 65081000 oris r8,r8,0x1000
193
194 0448 7D4011A6 eratwe r10,r0,2
195 044c 7C8009A6 eratwe r4,r0,1
196 0450 7D0001A6 eratwe r8,r0,0
197 0454 4C00012C isync
198
199 0458 3C608800 lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
200 # ierat 15 @00000000
201
202 045c 3800000F li r0,0x000F # entry #15
203 0460 3840003F li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
204 0464 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
205 0468 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
206
207 046c 7C7CFBA6 mtspr mmucr0,r3
208 0470 7C4011A6 eratwe r2,r0,2
209 0474 7C8009A6 eratwe r4,r0,1
210 0478 7D0001A6 eratwe r8,r0,0
211 047c 4C00012C isync
212
213 # *** leave the init'd entry 14 for MT access to FFFFFFC0
214 # ierat 13 @10000000
215
216 0480 3800000D li r0,0x000D # entry #13
217 0484 3C801000 lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
218 0488 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
219 048c 65081000 oris r8,r8,0x1000
220
221 0490 7D4011A6 eratwe r10,r0,2
222 0494 7C8009A6 eratwe r4,r0,1
223 0498 7D0001A6 eratwe r8,r0,0
224 049c 4C00012C isync
225
226 # -------------------------------------------------------------------------------------------------
227 # init
228 #
229
230 # T0-only
231 # set up any core facilities, then enable the others if config'd
232 init_t0:
233
234 # switch to 64b
235
236 04a0 81400A00 lwz r10,CONFIG+S_MSR(r0)
237 04a4 7D400124 mtmsr r10
238 04a8 4C00012C isync
239
240 # other init
241
242 04ac 3C200300 lis r1,0x0300 # icm=gicm=1
243 04b0 7C334BA6 mtspr epcr,r1
244
245 # set up timer facs
246
247 04b4 38200000 li r1,0 # clear
248 04b8 7C3603A6 mtspr dec,r1
249 04bc 7C3D43A6 mtspr tbh,r1
250 04c0 7C3C43A6 mtspr tbl,r1
251
252 04c4 3C40FE00 lis r2,0xFE00 # mask: clear enw,wis,wrs,dis,fis,udis
253 04c8 7C5053A6 mtspr tsr,r2
254
255 04cc 7C56FAA6 mfspr r2,xucr0
256 04d0 70420200 andi. r2,r2,0x0200 # set tcs=0
257 04d4 7C56FBA6 mtspr xucr0,r2
258
259 04d8 7C3053A6 mtspr tsr,r1 # clear tsr
260 04dc 7C3453A6 mtspr tcr,r1 # disable all timers
261
262 # set thread configuration
263
264 04e0 80200A04 lwz r1,CONFIG+S_FLAGS(r0)
265 04e4 7021000F andi. r1,r1,0xF
266 04e8 7C366BA6 mtspr tens,r1 # 60:63 = tid 3:0 enabled
267 #not r1,r1
268 #mtspr tenc,r1 # in case T0 is marked disabled
269 04ec 4C00012C isync
270
271 04f0 48000014 b boot_complete
272
273 # except T0
274 # just worry about myself
275
276 init_t123:
277
278 # switch to 64b
279
280 04f4 81400A00 lwz r10,CONFIG+S_MSR(r0)
281 04f8 7D400124 mtmsr r10
282 04fc 4C00012C isync
283
284 0500 48000004 b boot_complete
285
286 # -------------------------------------------------------------------------------------------------
287 boot_complete:
288
289 # set up thread and hop to it
290
291 0504 80200A04 lwz r1,CONFIG+S_FLAGS(r0)
292 0508 74218000 andis. r1,r1,0x8000 # 1=skip initial printf init
293 050c 40820008 bne boot_complete_1
294 0510 480006F1 bl printf_reset # wipe buffer
295
296 boot_complete_1:
297
298 0514 80200A04 lwz r1,CONFIG+S_FLAGS(r0)
299 0518 3C407FFF lis r2,0x7FFF # clear printf flag
300 051c 6042FFFF ori r2,r2,0xFFFF
301 0520 7C211038 and r1,r1,r2
302 0524 90200A04 stw r1,CONFIG+S_FLAGS(r0)
303
304 0528 7CBE6AA6 mfspr r5,tir # who am i?
305 052c 78A53664 sldi r5,r5,6 # 64B offset
306 0530 38A50A80 addi r5,r5,CONFIG+T_CONFIG
307
308 0534 81650000 lwz r11,T_MSR(r5)
309 0538 E9850008 ld r12,T_STACK(r5)
310 053c E9A50010 ld r13,T_ENTRY(r5)
311
312 0540 80200A04 lwz r1,CONFIG+S_FLAGS(r0)
313 0544 70210010 andi. r1,r1,FLAG_EOT_SC
314 0548 4182001C beq eot_blr
315
316 eot_sc:
317
318 054c 80400A0C lwz r2,CONFIG+S_EOT_SC(r0)
319 0550 3C204400 lis r1,0x4400 # 'sc 1'
320 0554 60210012 ori r1,r1,0022
321 0558 F8220000 std r1,0x0(r2)
322 055c 7C2803A6 mtlr r1 # prog will blr to sc
323 0560 48000014 b process_start
324
325 eot_blr:
326
327 0564 48000005 bl 4
328 0568 7C2802A6 mflr r1
329 056c 38210030 addi r1,r1,0x30 # !!!!!!!!!!!!!!! <-- WARNING!
330 0570 7C2803A6 mtlr r1 # prog will blr to exec_complete
331
332 process_start:
333
334 0574 7D7B03A6 mtspr srr1,r11 # msr
335 0578 7DBA03A6 mtspr srr0,r13 # @entry
336 057c 7D816378 mr r1,r12 # @stack
337 0580 7C7E6AA6 mfspr r3,tir # tid - main(tid) if yall want it
338
339 0584 7C4C42A6 mfspr r2,tb
340 0588 F8450030 std r2,T_TIMER_START(r5)
341 058c 4C000064 rfi
342 0590 60000000 nop # !!!!!!!!!!!!!!! pads for lr calc
343 0594 60000000 nop
344 0598 60000000 nop
345
346 # -------------------------------------------------------------------------------------------------
347 exec_complete:
348 # allow blr to here, or it will be entered by sc directly
349
350 # user blr'd here...
351 059c 44000022 sc 1 # hvsc back to sup state
352
353 exec_complete_sup:
354 05a0 7CBE6AA6 mfspr r5,tir # who am i?
355 05a4 78A53664 sldi r5,r5,6 # 64B offset
356 05a8 38A50A80 addi r5,r5,CONFIG+T_CONFIG
357
358 05ac 7C4C42A6 mfspr r2,tb
359 05b0 F8450038 std r2,T_TIMER_END(r5)
360
361 05b4 2C230000 cmpdi r3,0 # check rc
362 05b8 41820148 beq pass
363 05bc 48000044 b fail
364
365 # -------------------------------------------------------------------------------------------------
366 # dead zone
367 05c0 48000040 .align 8
367 60000000
367 60000000
367 60000000
367 60000000
368 fail:
369 0600 48000000 b .
370
371 # -------------------------------------------------------------------------------------------------
372 # happy ending
373 0604 480000FC .align 8
373 60000000
373 60000000
373 60000000
373 60000000
374 pass:
375 0700 48000000 b .
376
377 # -------------------------------------------------------------------------------------------------
378
379 # dec
380 0704 480000FC .align 11
380 60000000
380 60000000
380 60000000
380 60000000
381 int_800:
382 0800 48000000 b .
383
384 # perf
385 0804 4800001C .align 5
385 60000000
385 60000000
385 60000000
385 60000000
386 int_820:
387 0820 48000000 b .
388
389 .set CONFIG,0x0A00
390 # -------------------------------------------------------------------------------------------------
391 # config info
392 0824 480001DC .align 9
392 60000000
392 60000000
392 60000000
392 60000000
393
394 0a00 8002B000 .long 0x8002B000 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
395 0a04 80000001 .long 0x80000001 # flags: skip_printf_init=0 eot_sc=27 thr_en=28:31(T3:T0)
396 0a08 000000BF .long 0x000000BF # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wi
397 0a0c 10000000 .long 0x10000000 # @user eot sc
398
399 # per-thread configs (64B each)
400 0a10 48000070 .align 7
400 60000000
400 60000000
400 60000000
400 60000000
401 0a80 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
402 0a84 00000000 .long 0x00000000 #
403 0a88 00000000 .long 0x00000000 #
404 0a8c 1003FF00 .long 0x1003FF00 # @stack
405 0a90 00000000 .long 0x00000000 #
406 0a94 100004B0 .long 0x100004B0 # @entry
407 0a98 00000000 .long 0
408 0a9c 10030000 .long 0x10030000 # @print_start
409 0aa0 00000000 .long 0
410 0aa4 10031FFF .long 0x10031FFF # @print_end
411 0aa8 00000000 .long 0
412 0aac 10030000 .long 0x10030000 # print ptr
413 0ab0 00000000 .quad 0 # start tb
413 00000000
414 0ab8 00000000 .quad 0 # end tb
414 00000000
415
416 0ac0 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
417 0ac4 00000000 .long 0x00000000 #
418 0ac8 00000000 .long 0x00000000 #
419 0acc 1003DF00 .long 0x1003DF00 # @stack
420 0ad0 00000000 .long 0x00000000 #
421 0ad4 100004B0 .long 0x100004B0 # @entry
422 0ad8 00000000 .long 0
423 0adc 10032000 .long 0x10032000 # @print_start
424 0ae0 00000000 .long 0
425 0ae4 10033FFF .long 0x10033FFF # @print_end
426 0ae8 00000000 .long 0
427 0aec 10032000 .long 0x10032000 # print ptr
428 0af0 00000000 .quad 0 # start tb
428 00000000
429 0af8 00000000 .quad 0 # end tb
429 00000000
430
431 0b00 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
432 0b04 00000000 .long 0x00000000 # flags
433 0b08 00000000 .long 0x00000000 #
434 0b0c 1003BF00 .long 0x1003BF00 # @stack
435 0b10 00000000 .long 0x00000000 #
436 0b14 100004B0 .long 0x100004B0 # @entry
437 0b18 00000000 .long 0
438 0b1c 10034000 .long 0x10034000 # @print_start
439 0b20 00000000 .long 0
440 0b24 10035FFF .long 0x10035FFF # @print_end
441 0b28 00000000 .long 0
442 0b2c 10034000 .long 0x10034000 # print ptr
443 0b30 00000000 .quad 0 # start tb
443 00000000
444 0b38 00000000 .quad 0 # end tb
444 00000000
445
446 0b40 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
447 0b44 00000000 .long 0x00000000 # flags
448 0b48 00000000 .long 0x00000000 #
449 0b4c 10039F00 .long 0x10039F00 # @stack
450 0b50 00000000 .long 0x00000000 #
451 0b54 100004B0 .long 0x100004B0 # @entry
452 0b58 00000000 .long 0
453 0b5c 10036000 .long 0x10036000 # @print_start
454 0b60 00000000 .long 0
455 0b64 10037FFF .long 0x10037FFF # @print_end
456 0b68 00000000 .long 0
457 0b6c 10036000 .long 0x10036000 # print ptr
458 0b70 00000000 .quad 0 # start tb
458 00000000
459 0b78 00000000 .quad 0 # end tb
459 00000000
460
461
462 .set S_MSR,0x00
463 .set S_FLAGS,0x04
464 .set S_ERATW2,0x08
465 .set S_EOT_SC,0x0C
466
467 .set T_CONFIG,0x80
468 .set T_MSR,0x00
469 .set T_FLAGS,0x04
470 .set T_STACK,0x08
471 .set T_ENTRY,0x10
472 .set T_TIMER_START,0x30
473 .set T_TIMER_END,0x38
474 .set T_PRINTSTART, 0x18
475 .set T_PRINTEND, 0x20
476 .set T_PRINTF, 0x28
477 .set FLAG_EOT_SC,0x10
478
479
480 # -------------------------------------------------------------------------------------------------
481 # other stuff
482 0b80 48000080 .align 10
482 60000000
482 60000000
482 60000000
482 60000000
483
484 # clear buffer and reset pointer to start
485 .align 6
486 printf_reset:
487
488 0c00 7CBE6AA6 mfspr r5,tir # who am i?
489 0c04 78A53664 sldi r5,r5,6 # 64B offset
490 0c08 38A50A80 addi r5,r5,CONFIG+T_CONFIG
491
492 0c0c 38C50018 addi r6,r5,T_PRINTSTART
493 0c10 E8E60000 ld r7,0(r6) # buffer start
494 0c14 38C50020 addi r6,r5,T_PRINTEND
495 0c18 E9060000 ld r8,0(r6) # buffer end
496 0c1c 7D074050 sub r8,r8,r7
497 0c20 39080001 addi r8,r8,1 # num bytes
498
499 0c24 7D0903A6 mtctr r8
500 0c28 38C00000 li r6,0
501 0c2c 7CE83B78 mr r8,r7
502 printf_reset_clr:
503 0c30 98C80000 stb r6,0(r8)
504 0c34 39080001 addi r8,r8,1
505 0c38 4200FFF8 bdnz printf_reset_clr
506
507 0c3c 39050028 addi r8,r5,T_PRINTF
508 0c40 F8E80000 std r7,0(r8) # reset ptr
509
510 0c44 4E800020 blr
511
512
513 # hvsc
514 0c48 480000B8 .align 8
514 60000000
514 60000000
514 60000000
514 60000000
515 # go to exec_complete_sup in sup mode
516 int_300_handler:
517
518 0d00 80000A00 lwz r0,CONFIG+S_MSR(r0)
519 0d04 7C000124 mtmsr r0
520 0d08 4C00012C isync
521 0d0c 4BFFF894 b exec_complete_sup
522
523 # sc
524 0d10 480000F0 .align 8
524 60000000
524 60000000
524 60000000
524 60000000
525 # r3 is id, remaining are function-specific
526 # not preserving r0, r3-r9 right now
527 #
528 # 0001 whoami
529 # 0010 tick
530 # 0100 putchar r4=c
531 # 0106 printf_mode *NI*
532 # 0107 printf_rst
533 #
534 int_120_handler:
535
536 0e00 7C0802A6 mflr r0
537
538 0e04 2C230001 cmpdi r3,0x0001
539 0e08 41820038 beq sc_whoami
540 0e0c 2C230010 cmpdi r3,0x0010
541 0e10 41820070 beq sc_tick
542 0e14 2C230100 cmpdi r3,0x100
543 0e18 418200A8 beq sc_putchar
544 0e1c 2C230107 cmpdi r3,0x107
545 0e20 41820120 beq sc_printf_rst
546
547 0e24 3860FFFF li r3,-1
548 0e28 7C0803A6 mtlr r0
549 0e2c 4C000064 rfi
550
551 # thread id
552 0e30 60000000 .align 6
552 60000000
552 60000000
552 60000000
553 sc_whoami:
554 0e40 7C7E6AA6 mfspr r3,tir
555 0e44 4C000064 rfi
556
557 # tb
558 0e48 48000038 .align 6
558 60000000
558 60000000
558 60000000
558 60000000
559 sc_tick:
560 0e80 7C6C42A6 mfspr r3,tb
561 0e84 4C000064 rfi
562
563 # wrap buffer; could add flag to stop when full, or reset
564 0e88 48000038 .align 6
564 60000000
564 60000000
564 60000000
564 60000000
565 sc_putchar:
566
567 0ec0 7CBE6AA6 mfspr r5,tir # who am i?
568 0ec4 78A53664 sldi r5,r5,6 # 64B offset
569 0ec8 38A50A80 addi r5,r5,CONFIG+T_CONFIG
570
571 0ecc 38C50028 addi r6,r5,T_PRINTF
572 0ed0 E8E60000 ld r7,0(r6) # buffer ptr
573 0ed4 98870000 stb r4,0(r7) # store char
574 0ed8 38E70001 addi r7,r7,1
575
576 0edc 39050020 addi r8,r5,T_PRINTEND
577 0ee0 E9080000 ld r8,0(r8) # buffer end
578 0ee4 7C274000 cmpd r7,r8
579 0ee8 38600000 li r3,0 # rc=normal
580 0eec 40810010 ble sc_putchar_ok
581 0ef0 39050018 addi r8,r5,T_PRINTSTART
582 0ef4 E8E80000 ld r7,0(r8) # buffer start
583 0ef8 3860FFFF li r3,-1 # rc=full
584 sc_putchar_ok:
585 0efc F8E60000 std r7,0(r6) # save ptr
586
587 0f00 4C000064 rfi
588
589 # clear buffer and reset pointer to start
590 0f04 4800003C .align 6
590 60000000
590 60000000
590 60000000
590 60000000
591 sc_printf_rst:
592
593 0f40 7C6902A6 mfctr r3
594
595 0f44 4BFFFCBD bl printf_reset
596
597 0f48 7C6903A6 mtctr r3
598 0f4c 7C0803A6 mtlr r0
599 0f50 38600000 li r3,0
600
601 0f54 4C000064 rfi
602

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# © IBM Corp. 2020
# Licensed under and subject to the terms of the CC-BY 4.0
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
# Additional rights, including the right to physically implement a softcore
# that is compliant with the required sections of the Power ISA
# Specification, will be available at no cost via the OpenPOWER Foundation.
# This README will be updated with additional information when OpenPOWER's
# license is available.

# boot kernel
# set up translations
# set up timer facilities
# set up threads
# call user code
# process user rc

# todo:
# 1. skip_printf_init flag should be threaded

.include "defines.s"

.section .text
start:

int_000:
b boot_start

# critical input
.align 5
int_020:
b .

# debug
.align 5
int_040:
b .

# dsi
.align 5
int_060:
b .

# isi
.align 5
int_080:
b .

# external
.align 5
int_0A0:
b .

# alignment
.align 5
int_0C0:
b .

# program
.align 5
int_0E0:
b .

# fp unavailable
.align 5
int_100:
b .

# sc
.align 5
int_120:
b int_120_handler

# apu unavailable
.align 5
int_140:
b .

# decrementer
.align 5
int_160:
b .

# fit
.align 5
int_180:
b .

# watchdog
.align 5
int_1A0:
b .

# dtlb
.align 5
int_1C0:
b .

# itlb
.align 5
int_1E0:
b .

# vector unavailable
.align 5
int_200:
b .

#
.align 5
int_220:
b .

#
.align 5
int_240:
b .

#
.align 5
int_260:
b .

# doorbell
.align 5
int_280:
b .

# doorbell critical
.align 5
int_2A0:
b .

# doorbell guest
.align 5
int_2C0:
b .

# doorbell guest critical
.align 5
int_2E0:
b .

# hvsc
.align 8
int_300:
b int_300_handler

# hvpriv
.align 5
int_320:
b .

# lrat
.align 5
int_340:
b .

# ------------------------------------------------------------------------------------------------------------------------------
# initial translation
# both erats:
# 00000000 1M: (boot)
# 10000000 1M: (test)

.align 8
boot_start:

mfspr r5,tir # who am i?
cmpdi r5,0x00 # skip unless T0
bne init_t123

lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
# derat 31 @00000000

li r0,0x001F # entry #31
li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G

mtspr mmucr0,r3
eratwe r2,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync

lwz r10,CONFIG+S_ERATW2(r0) # load parms for erat settings

# derat 30 @100000000

li r0,0x001E # entry #30
lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
oris r8,r8,0x1000

eratwe r10,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync

lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
# ierat 15 @00000000

li r0,0x000F # entry #15
li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G

mtspr mmucr0,r3
eratwe r2,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync

# *** leave the init'd entry 14 for MT access to FFFFFFC0
# ierat 13 @10000000

li r0,0x000D # entry #13
lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
oris r8,r8,0x1000

eratwe r10,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync

# ------------------------------------------------------------------------------------------------------------------------------
# init
#

# T0-only
# set up any core facilities, then enable the others if config'd
init_t0:

# switch to 64b

lwz r10,CONFIG+S_MSR(r0)
mtmsr r10
isync

# other init

lis r1,0x0300 # icm=gicm=1
mtspr epcr,r1

# set up timer facs

li r1,0 # clear
mtspr dec,r1
mtspr tbh,r1
mtspr tbl,r1

lis r2,0xFE00 # mask: clear enw,wis,wrs,dis,fis,udis
mtspr tsr,r2

mfspr r2,xucr0
andi. r2,r2,0x0200 # set tcs=0
mtspr xucr0,r2

mtspr tsr,r1 # clear tsr
mtspr tcr,r1 # disable all timers

# set thread configuration

lwz r1,CONFIG+S_FLAGS(r0)
andi. r1,r1,0xF
mtspr tens,r1 # 60:63 = tid 3:0 enabled
#not r1,r1
#mtspr tenc,r1 # in case T0 is marked disabled
isync

b boot_complete

# except T0
# just worry about myself

init_t123:

# switch to 64b

lwz r10,CONFIG+S_MSR(r0)
mtmsr r10
isync

b boot_complete

# ------------------------------------------------------------------------------------------------------------------------------
boot_complete:

# set up thread and hop to it

lwz r1,CONFIG+S_FLAGS(r0)
andis. r1,r1,0x8000 # 1=skip initial printf init
bne boot_complete_1
bl printf_reset # wipe buffer

boot_complete_1:

lwz r1,CONFIG+S_FLAGS(r0)
lis r2,0x7FFF # clear printf flag
ori r2,r2,0xFFFF
and r1,r1,r2
stw r1,CONFIG+S_FLAGS(r0)

mfspr r5,tir # who am i?
sldi r5,r5,6 # 64B offset
addi r5,r5,CONFIG+T_CONFIG

lwz r11,T_MSR(r5)
ld r12,T_STACK(r5)
ld r13,T_ENTRY(r5)

lwz r1,CONFIG+S_FLAGS(r0)
andi. r1,r1,FLAG_EOT_SC
beq eot_blr

eot_sc:

lwz r2,CONFIG+S_EOT_SC(r0)
lis r1,0x4400 # 'sc 1'
ori r1,r1,0022
std r1,0x0(r2)
mtlr r1 # prog will blr to sc
b process_start

eot_blr:

bl 4
mflr r1
addi r1,r1,0x30 # !!!!!!!!!!!!!!! <-- WARNING!
mtlr r1 # prog will blr to exec_complete

process_start:

mtspr srr1,r11 # msr
mtspr srr0,r13 # @entry
mr r1,r12 # @stack
mfspr r3,tir # tid - main(tid) if yall want it

mfspr r2,tb
std r2,T_TIMER_START(r5)
rfi
nop # !!!!!!!!!!!!!!! pads for lr calc
nop
nop

# ------------------------------------------------------------------------------------------------------------------------------
exec_complete:
# allow blr to here, or it will be entered by sc directly

# user blr'd here...
sc 1 # hvsc back to sup state

exec_complete_sup:
mfspr r5,tir # who am i?
sldi r5,r5,6 # 64B offset
addi r5,r5,CONFIG+T_CONFIG

mfspr r2,tb
std r2,T_TIMER_END(r5)

cmpdi r3,0 # check rc
beq pass
b fail

# ------------------------------------------------------------------------------------------------------------------------------
# dead zone
.align 8
fail:
b .

# ------------------------------------------------------------------------------------------------------------------------------
# happy ending
.align 8
pass:
b .

# ------------------------------------------------------------------------------------------------------------------------------

# dec
.align 11
int_800:
b .

# perf
.align 5
int_820:
b .

.set CONFIG,0x0A00
# ------------------------------------------------------------------------------------------------------------------------------
# config info
.align 9

.long 0x8002B000 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
.long 0x80000001 # flags: skip_printf_init=0 eot_sc=27 thr_en=28:31(T3:T0)
.long 0x000000BF # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
.long 0x10000000 # @user eot sc

# per-thread configs (64B each)
.align 7
.long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
.long 0x00000000 #
.long 0x00000000 #
.long 0x1003FF00 # @stack
.long 0x00000000 #
.long 0x100004B0 # @entry
.long 0
.long 0x10030000 # @print_start
.long 0
.long 0x10031FFF # @print_end
.long 0
.long 0x10030000 # print ptr
.quad 0 # start tb
.quad 0 # end tb

.long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
.long 0x00000000 #
.long 0x00000000 #
.long 0x1003DF00 # @stack
.long 0x00000000 #
.long 0x100004B0 # @entry
.long 0
.long 0x10032000 # @print_start
.long 0
.long 0x10033FFF # @print_end
.long 0
.long 0x10032000 # print ptr
.quad 0 # start tb
.quad 0 # end tb

.long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
.long 0x00000000 # flags
.long 0x00000000 #
.long 0x1003BF00 # @stack
.long 0x00000000 #
.long 0x100004B0 # @entry
.long 0
.long 0x10034000 # @print_start
.long 0
.long 0x10035FFF # @print_end
.long 0
.long 0x10034000 # print ptr
.quad 0 # start tb
.quad 0 # end tb

.long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
.long 0x00000000 # flags
.long 0x00000000 #
.long 0x10039F00 # @stack
.long 0x00000000 #
.long 0x100004B0 # @entry
.long 0
.long 0x10036000 # @print_start
.long 0
.long 0x10037FFF # @print_end
.long 0
.long 0x10036000 # print ptr
.quad 0 # start tb
.quad 0 # end tb


.set S_MSR,0x00
.set S_FLAGS,0x04
.set S_ERATW2,0x08
.set S_EOT_SC,0x0C

.set T_CONFIG,0x80
.set T_MSR,0x00
.set T_FLAGS,0x04
.set T_STACK,0x08
.set T_ENTRY,0x10
.set T_TIMER_START,0x30
.set T_TIMER_END,0x38
.set T_PRINTSTART, 0x18
.set T_PRINTEND, 0x20
.set T_PRINTF, 0x28
.set FLAG_EOT_SC,0x10


# ------------------------------------------------------------------------------------------------------------------------------
# other stuff
.align 10

# clear buffer and reset pointer to start
.align 6
printf_reset:

mfspr r5,tir # who am i?
sldi r5,r5,6 # 64B offset
addi r5,r5,CONFIG+T_CONFIG

addi r6,r5,T_PRINTSTART
ld r7,0(r6) # buffer start
addi r6,r5,T_PRINTEND
ld r8,0(r6) # buffer end
sub r8,r8,r7
addi r8,r8,1 # num bytes

mtctr r8
li r6,0
mr r8,r7
printf_reset_clr:
stb r6,0(r8)
addi r8,r8,1
bdnz printf_reset_clr

addi r8,r5,T_PRINTF
std r7,0(r8) # reset ptr

blr


# hvsc
.align 8
# go to exec_complete_sup in sup mode
int_300_handler:

lwz r0,CONFIG+S_MSR(r0)
mtmsr r0
isync
b exec_complete_sup

# sc
.align 8
# r3 is id, remaining are function-specific
# not preserving r0, r3-r9 right now
#
# 0001 whoami
# 0010 tick
# 0100 putchar r4=c
# 0106 printf_mode *NI*
# 0107 printf_rst
#
int_120_handler:

mflr r0

cmpdi r3,0x0001
beq sc_whoami
cmpdi r3,0x0010
beq sc_tick
cmpdi r3,0x100
beq sc_putchar
cmpdi r3,0x107
beq sc_printf_rst

li r3,-1
mtlr r0
rfi

# thread id
.align 6
sc_whoami:
mfspr r3,tir
rfi

# tb
.align 6
sc_tick:
mfspr r3,tb
rfi

# wrap buffer; could add flag to stop when full, or reset
.align 6
sc_putchar:

mfspr r5,tir # who am i?
sldi r5,r5,6 # 64B offset
addi r5,r5,CONFIG+T_CONFIG

addi r6,r5,T_PRINTF
ld r7,0(r6) # buffer ptr
stb r4,0(r7) # store char
addi r7,r7,1

addi r8,r5,T_PRINTEND
ld r8,0(r8) # buffer end
cmpd r7,r8
li r3,0 # rc=normal
ble sc_putchar_ok
addi r8,r5,T_PRINTSTART
ld r7,0(r8) # buffer start
li r3,-1 # rc=full
sc_putchar_ok:
std r7,0(r6) # save ptr

rfi

# clear buffer and reset pointer to start
.align 6
sc_printf_rst:

mfctr r3

bl printf_reset

mtctr r3
mtlr r0
li r3,0

rfi

@ -0,0 +1,144 @@
# © IBM Corp. 2020
# Licensed under and subject to the terms of the CC-BY 4.0
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
# Additional rights, including the right to physically implement a softcore
# that is compliant with the required sections of the Power ISA
# Specification, will be available at no cost via the OpenPOWER Foundation.
# This README will be updated with additional information when OpenPOWER's
# license is available.

#-----------------------------------------
# Defines
#-----------------------------------------

# Regs

.set r0, 0
.set r1, 1
.set r2, 2
.set r3, 3
.set r4, 4
.set r5, 5
.set r6, 6
.set r7, 7
.set r8, 8
.set r9, 9
.set r10,10
.set r11,11
.set r12,12
.set r13,13
.set r14,14
.set r15,15
.set r16,16
.set r17,17
.set r18,18
.set r19,19
.set r20,20
.set r21,21
.set r22,22
.set r23,23
.set r24,24
.set r25,25
.set r26,26
.set r27,27
.set r28,28
.set r29,29
.set r30,30
.set r31,31

.set f0, 0
.set f1, 1
.set f2, 2
.set f3, 3
.set f4, 4
.set f5, 5
.set f6, 6
.set f7, 7
.set f8, 8
.set f9, 9
.set f10,10
.set f11,11
.set f12,12
.set f13,13
.set f14,14
.set f15,15
.set f16,16
.set f17,17
.set f18,18
.set f19,19
.set f20,20
.set f21,21
.set f22,22
.set f23,23
.set f24,24
.set f25,25
.set f26,26
.set f27,27
.set f28,28
.set f29,29
.set f30,30
.set f31,31

.set cr0, 0
.set cr1, 1
.set cr2, 2
.set cr3, 3
.set cr4, 4
.set cr5, 5
.set cr6, 6
.set cr7, 7

# SPR numbers

.set srr0, 26
.set srr1, 27
.set epcr, 307
.set tar, 815

.set dbsr, 304
.set dbcr0, 308
.set dbcr1, 309
.set dbcr2, 310
.set dbcr3, 848

.set ivpr, 63

.set iucr0, 1011
.set iucr1, 883
.set iucr2, 884

.set iudbg0, 888
.set iudbg1, 889
.set iudbg2, 890
.set iulfsr, 891
.set iullcr, 892

.set mmucr0, 1020
.set mmucr1, 1021
.set mmucr2, 1022
.set mmucr3, 1023

.set tb, 268
.set tbl, 284
.set tbh, 285

.set dec, 22
.set udec, 550
.set tsr, 336
.set tcr, 340

.set xucr0, 1014
.set xucr1, 851
.set xucr2, 1016
.set xucr3, 852
.set xucr4, 853

.set tens, 438
.set tenc, 439
.set tensr, 437

.set pid, 48
.set pir, 286
.set pvr, 287
.set tir, 446

@ -0,0 +1,13 @@
#

```
powerpc-linux-gnu-as -a64 -mbig-endian -ma2 boot.s -ahlnd -o boot.o > boot.lst
powerpc-linux-gnu-objdump -d boot.o > boot.d

# creat binary
powerpc-linux-gnu-objcopy -O binary boot.o boot.bin

# create ascii hex
../bin/bin2init boot.bin

```

@ -0,0 +1,27 @@
#!/usr/bin/python3

# read .bin (objcopy -O binary x.elf x.bin) and create ascii block file

import sys
from binascii import hexlify, unhexlify

def x2d(i):
return int(i, 16)

inFile = sys.argv[1]
#size = sys.argv[2]

outFile = inFile + '.hex'

lines = []
with open(inFile, 'rb') as binFile:
word = binFile.read(4)
while word:
hex = hexlify(word)
lines.append(hex.decode('utf-8').upper() + '\n')
word = binFile.read(4)

# need to pad to full size?
with open(outFile, 'w') as txtFile:
txtFile.writelines(lines)

@ -0,0 +1,194 @@
# Synthesis

```
yosys -s synth.yo &> yosys.txt
```

## Arrays

```
grep tri_1 verilog/work/*
verilog/work/fu_fpr.v: tri_144x78_2r4w fpr0(
verilog/work/fu_fpr.v: tri_144x78_2r4w fpr1(
verilog/work/iuq_ic_dir.v: tri_128x34_4w_1r1w idir(
verilog/work/mmq.v: tri_128x168_1w_0 tlb_array0(
verilog/work/mmq.v: tri_128x168_1w_0 tlb_array1(
verilog/work/mmq.v: tri_128x168_1w_0 tlb_array2(
verilog/work/mmq.v: tri_128x168_1w_0 tlb_array3(
verilog/work/mmq.v: tri_128x16_1r1w_1 lru_array0(
verilog/work/rv.v: tri_144x78_2r4w
verilog/work/xu_gpr.v: tri_144x78_2r4w gpr0(
verilog/work/xu_gpr.v: tri_144x78_2r4w gpr1(

grep tri_2 verilog/work/*
verilog/work/lq_data.v: tri_256x144_8w_1r1w #(.addressable_ports(256), .addressbus_width(8), .port_bitwidth(144), .bit_write_type(9), .ways(8)) tridcarr(

grep tri_3 verilog/work/*
verilog/work/lq_pfetch.v: tri_32x70_2w_1r1w rpt(

grep tri_5 verilog/work/*
verilog/work/iuq_ic_dir.v: tri_512x162_4w_0 idata(

grep tri_6 verilog/work/*
verilog/work/iuq_btb.v: tri_64x72_1r1w btb0(
verilog/work/lq_ctl.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(
verilog/work/lq_ldq_relq.v: tri_64x144_1r1w rdat(
verilog/work/lq_lsq.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(
verilog/work/xu_spr.v: tri_64x72_1r1w xu_spr_aspr(

grep tri_bht verilog/work/*
verilog/work/iuq.v: tri_bht_1024x8_1r1w bht0(
verilog/work/iuq.v: tri_bht_1024x8_1r1w bht1(
verilog/work/iuq.v: tri_bht_512x4_1r1w bht2(

grep tri_cam verilog/work/*
verilog/work/iuq_ic_ierat.v: tri_cam_16x143_1r1w1c ierat_cam(
verilog/work/lq_derat.v: tri_cam_32x143_1r1w1c derat_cam(

grep tri_iuq verilog/work/*
verilog/work/iuq_cpl.v: tri_iuq_cpl_arr #(.ADDRESSABLE_PORTS(64), .ADDRESSBUS_WIDTH(6), .PORT_BITWIDTH(entry_length), .LATCHED_READ(1'b1), .LATCHED_READ_DATA(1'b1), .LATCHED_WRITE(1'b1))
```

## By Unit

* XU (GPR, SPR)
verilog/work/xu_gpr.v: tri_144x78_2r4w gpr0(
verilog/work/xu_gpr.v: tri_144x78_2r4w gpr1(
verilog/work/xu_spr.v: tri_64x72_1r1w xu_spr_aspr(

* FU (FPR)
verilog/work/fu_fpr.v: tri_144x78_2r4w fpr0(
verilog/work/fu_fpr.v: tri_144x78_2r4w fpr1(

* RV (LQ)
verilog/work/rv.v: tri_144x78_2r4w

* IU (CPL, ERAT, DIR, DATA, BTB, BHT)
verilog/work/iuq_cpl.v: tri_iuq_cpl_arr #(.ADDRESSABLE_PORTS(64), .ADDRESSBUS_WIDTH(6), .PORT_BITWIDTH(entry_length), .LATCHED_READ(1'b1), .LATCHED_READ_DATA(1'b1), .LATCHED_WRITE(1'b1))
verilog/work/iuq_ic_ierat.v: tri_cam_16x143_1r1w1c ierat_cam(
verilog/work/iuq_ic_dir.v: tri_128x34_4w_1r1w idir(
verilog/work/iuq_ic_dir.v: tri_512x162_4w_0 idata(
verilog/work/iuq_btb.v: tri_64x72_1r1w btb0(
verilog/work/iuq.v: tri_bht_1024x8_1r1w bht0(
verilog/work/iuq.v: tri_bht_1024x8_1r1w bht1(
verilog/work/iuq.v: tri_bht_512x4_1r1w bht2(

* LQ (ERAT, DIR, DATA. PFETCH, RLDQ, STQ)
verilog/work/lq_derat.v: tri_cam_32x143_1r1w1c derat_cam(
verilog/work/lq_pfetch.v: tri_32x70_2w_1r1w rpt(
verilog/work/lq_data.v: tri_256x144_8w_1r1w #(.addressable_ports(256), .addressbus_width(8), .port_bitwidth(144), .bit_write_type(9), .ways(8)) tridcarr(
verilog/work/lq_ctl.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(
verilog/work/lq_ldq_relq.v: tri_64x144_1r1w rdat(
verilog/work/lq_lsq.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(

* MMU (TLB)
verilog/work/mmq.v: tri_128x168_1w_0 tlb_array0(
verilog/work/mmq.v: tri_128x168_1w_0 tlb_array1(
verilog/work/mmq.v: tri_128x168_1w_0 tlb_array2(
verilog/work/mmq.v: tri_128x168_1w_0 tlb_array3(
verilog/work/mmq.v: tri_128x16_1r1w_1 lru_array0(

## By Type

### Normal

* tri_144x78_2r4w
verilog/work/xu_gpr.v: tri_144x78_2r4w gpr0(
verilog/work/xu_gpr.v: tri_144x78_2r4w gpr1(
verilog/work/fu_fpr.v: tri_144x78_2r4w fpr0(
verilog/work/fu_fpr.v: tri_144x78_2r4w fpr1(
verilog/work/rv.v: tri_144x78_2r4w

* tri_64x72_1r1w
verilog/work/xu_spr.v: tri_64x72_1r1w xu_spr_aspr(
verilog/work/iuq_btb.v: tri_64x72_1r1w btb0(

* tri_512x162_4w_0
verilog/work/iuq_ic_dir.v: tri_512x162_4w_0 idata(

* tri_32x70_2w_1r1w
verilog/work/lq_pfetch.v: tri_32x70_2w_1r1w rpt(

* tri_256x144_8w_1r1w
verilog/work/lq_data.v: tri_256x144_8w_1r1w #(.addressable_ports(256), .addressbus_width(8), .port_bitwidth(144), .bit_write_type(9), .ways(8)) tridcarr(

* tri_64x34_8w_1r1w
verilog/work/lq_ctl.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(
verilog/work/lq_lsq.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(

* tri_64x144_1r1w
verilog/work/lq_ldq_relq.v: tri_64x144_1r1w rdat(

* tri_128x168_1w_0
verilog/work/mmq.v: tri_128x168_1w_0 tlb_array0(
verilog/work/mmq.v: tri_128x168_1w_0 tlb_array1(
verilog/work/mmq.v: tri_128x168_1w_0 tlb_array2(
verilog/work/mmq.v: tri_128x168_1w_0 tlb_array3(

* tri_128x16_1r1w_1
verilog/work/mmq.v: tri_128x16_1r1w_1 lru_array0(

### Complex

#### Branch History

* tri_bht_1024x8_1r1w
verilog/work/iuq.v: tri_bht_1024x8_1r1w bht0(
verilog/work/iuq.v: tri_bht_1024x8_1r1w bht1(
* inner array:
tri_512x16_1r1w_1 bht0(


* tri_bht_512x4_1r1w
verilog/work/iuq.v: tri_bht_512x4_1r1w bht2(
* inner array:
tri_512x16_1r1w_1 bht0(


#### Completion

* tri_iuq_cpl_arr
verilog/work/iuq_cpl.v: tri_iuq_cpl_arr #(.ADDRESSABLE_PORTS(64), .ADDRESSBUS_WIDTH(6), .PORT_BITWIDTH(entry_length), .LATCHED_READ(1'b1), .LATCHED_READ_DATA(1'b1), .LATCHED_WRITE(1'b1))
* inner arrays (143)
RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D0(
RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D1(
* =2x64x143

#### ERATs (CAM)

* tri_cam_16x143_1r1w1c
verilog/work/iuq_ic_ierat.v: tri_cam_16x143_1r1w1c ierat_cam(

* tri_cam_32x143_1r1w1c
verilog/work/lq_derat.v: tri_cam_32x143_1r1w1c derat_cam(


## Summary

* the difficult arrays are the 2r4w (gpr, fpr, rv) and the cams; everything else is 1r1w

* cpl array is 1r1w (written in iu6, read in cp0), arranged even/odd for i0/i1; CPL_Q_DEPTH=32 means 32 even + 32 odd(?)

* some of these are directly changed with gen parameters; others may be do-able with some combo or parameters/spr settings/simple logic changes

* GPR rename pool size
* FPR rename pool size
* completion queue depth
* IERAT size
* IC size
* IC ways
* BTB size
* BHT size
* DERAT size
* DC size
* DC ways
* TLB size
* TLB ways

* e.g. no xlate, small caches

* IERAT, DERAT replaced with single-entry always-hit (no CAMs)
* IC, DC 1W small data
* no TLB
* alter BTB, BHT, rename, completion as necessary
* mmu logic (and fpu if not needed) could be dropped

@ -0,0 +1,13 @@
#read_verilog ../verilog/unisims
# blockbox versions
read_verilog ../verilog/unisims_synth

read_verilog -I../verilog/trilib ../verilog/trilib/*
read_verilog -I../verilog/trilib ../verilog/work/*

hierarchy -top c

proc; opt; memory -nomap; opt -fast
#check -assert

#synth -top c

@ -0,0 +1 @@
../verilog

@ -0,0 +1,174 @@
// © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`ifndef _tri_a2o_vh_
`define _tri_a2o_vh_

`include "tri.vh"

// Use this line for 1 thread. Comment out for 2 thread design.
//`define THREADS1

`define gpr_t 3'b000
`define cr_t 3'b001
`define lr_t 3'b010
`define ctr_t 3'b011
`define xer_t 3'b100
`define spr_t 3'b101
`define axu0_t 3'b110
`define axu1_t 3'b111

`ifdef THREADS1
`define THREADS 1
`define THREAD_POOL_ENC 0
`define THREADS_POOL_ENC 0
`else
`define THREADS 2
`define THREAD_POOL_ENC 1
`define THREADS_POOL_ENC 1
`endif
`define EFF_IFAR_ARCH 62
`define EFF_IFAR_WIDTH 20
`define EFF_IFAR 20
`define FPR_POOL_ENC 6
`define REGMODE 6
`define FPR_POOL 64
`define REAL_IFAR_WIDTH 42
`define EMQ_ENTRIES 4
`define GPR_WIDTH 64
`define ITAG_SIZE_ENC 7
`define CPL_Q_DEPTH 32
`define CPL_Q_DEPTH_ENC 6
`define GPR_WIDTH_ENC 6
`define GPR_POOL_ENC 6
`define GPR_POOL 64
`define GPR_UCODE_POOL 4
`define CR_POOL_ENC 5
`define CR_POOL 24
`define CR_UCODE_POOL 1
`define BR_POOL_ENC 3
`define BR_POOL 8
`define LR_POOL_ENC 3
`define LR_POOL 8
`define LR_UCODE_POOL 0
`define CTR_POOL_ENC 3
`define CTR_POOL 8
`define CTR_UCODE_POOL 0
`define XER_POOL_ENC 4
`define XER_POOL 12
`define XER_UCODE_POOL 0
`define LDSTQ_ENTRIES 16
`define LDSTQ_ENTRIES_ENC 4
`define STQ_ENTRIES 12
`define STQ_ENTRIES_ENC 4
`define STQ_FWD_ENTRIES 4 // number of stq entries that can be forwarded from
`define STQ_DATA_SIZE 64 // 64 or 128 Bit store data sizes supported
`define DC_SIZE 15 // 14 => 16K L1D$, 15 => 32K L1D$
`define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE
`define LMQ_ENTRIES 8
`define LMQ_ENTRIES_ENC 3
`define LGQ_ENTRIES 8
`define AXU_SPARE_ENC 3
`define RV_FX0_ENTRIES 12
`define RV_FX1_ENTRIES 12
`define RV_LQ_ENTRIES 16
`define RV_AXU0_ENTRIES 12
`define RV_AXU1_ENTRIES 0
`define RV_FX0_ENTRIES_ENC 4
`define RV_FX1_ENTRIES_ENC 4
`define RV_LQ_ENTRIES_ENC 4
`define RV_AXU0_ENTRIES_ENC 4
`define RV_AXU1_ENTRIES_ENC 1
`define UCODE_ENTRIES 8
`define UCODE_ENTRIES_ENC 3
`define FXU1_ENABLE 1
`define TYPE_WIDTH 3
`define IBUFF_INSTR_WIDTH 70
`define IBUFF_IFAR_WIDTH 20
`define IBUFF_DEPTH 16
`define PF_IAR_BITS 12 // number of IAR bits used by prefetch
`define FXU0_PIPE_START 1
`define FXU0_PIPE_END 8
`define FXU1_PIPE_START 1
`define FXU1_PIPE_END 5
`define LQ_LOAD_PIPE_START 4
`define LQ_LOAD_PIPE_END 8
`define LQ_REL_PIPE_START 2
`define LQ_REL_PIPE_END 4
`define LOAD_CREDITS 8
`define STORE_CREDITS 4
`define IUQ_ENTRIES 4 // Instruction Fetch Queue Size
`define MMQ_ENTRIES 2 // MMU Queue Size
`define CR_WIDTH 4
`define BUILD_PFETCH 1 // 1=> include pfetch in the build, 0=> build without pfetch
`define PF_IFAR_WIDTH 12
`define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch
`define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries)
`define PFETCH_Q_SIZE 8 // number of entries
`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings)
`define XER_WIDTH 10

`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT
`define INIT_IUCR0 16'h00FA // BP enabled
`define INIT_MASK 2'b10
`define RELQ_INCLUDE 0 // Reload Queue Included

`define G_BRANCH_LEN `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1

`define INIT_CPCR0 32'h0C0C100C // 000a aaaa 000b bbbb 000c cccc 000d dddd watermarks: a=fx0 b=fx1 c=ls d=sq ---- um p.543 wrong!; was this in vlog: hex 0C0C100C = 202117132
//`define INIT_CPCR0 32'h01010201 // 1/1/2/1

`define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504
//`define INIT_CPCR1 32'h00010100 // 1/1

// IERAT boot config entry values
`define IERAT_BCFG_EPN_0TO15 0
`define IERAT_BCFG_EPN_16TO31 0
`define IERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G
`define IERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
`define IERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff
`define IERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8181 for 512M, 65535 for 4G
`define IERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
`define IERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page
`define IERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page
`define IERAT_BCFG_ATTR 0 // u0-u3, endian

// DERAT boot config entry values
`define DERAT_BCFG_EPN_0TO15 0
`define DERAT_BCFG_EPN_16TO31 0
`define DERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G
`define DERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
`define DERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff
`define DERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8191 for 512M, 65535 for 4G
`define DERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
`define DERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page
`define DERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page
`define DERAT_BCFG_ATTR 0 // u0-u3, endian

// Do NOT add any defines below this line
`endif //_tri_a2o_vh_

@ -0,0 +1,266 @@
// © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.


// small-core test - see what parms work
// all the _enc's should be created automatically (clog2)

`ifndef _tri_a2o_vh_
`define _tri_a2o_vh_

`include "tri.vh"

`define THREADS1

// -----------------------------------------------------------------------------------------------------------------
// updates
// * some may have restrictions (by design or by coding)
// * some may be dependent
// * some may be dependent on reg settings

// breaks sim
//`define CPL_Q_DEPTH 8
//`define CPL_Q_DEPTH_ENC 3

//`define EMQ_ENTRIES 1
//`define LDSTQ_ENTRIES 4
//`define LDSTQ_ENTRIES_ENC 2
`define LMQ_ENTRIES 4
`define LMQ_ENTRIES_ENC 2
`define LGQ_ENTRIES 4

// needs src updates

// limited to 5+:
// ../../verilog/work/iuq_ibuf.v:383: error: part select buffer_valid_q[0:-1] is out of order.
// ../../verilog/work/iuq_ibuf.v:410: error: part select buffer_head_q[0:-1] is out of order.
//`define IBUFF_DEPTH 5

// limited to 14/15(?)
//`define DC_SIZE 14 // fails sim

// STQ_FWD_ENTRIES must be 1 or more less than STQ_ENTRIES:
// ../../verilog/work/lq_stq.v:2972: error: part select ex4_fwd_sel[4:3] is out of order.
//`define STQ_ENTRIES 4
//`define STQ_ENTRIES_ENC 2
//`define STQ_FWD_ENTRIES 3

//`define GPR_POOL 8
//`define GPR_POOL_ENC 3
//`define GPR_UCODE_POOL 2
//`define FPR_POOL 2
//`define FPR_POOL_ENC 1
//`define CR_POOL 8
//`define CR_POOL_ENC 3
//`define CR_UCODE_POOL 1
//`define BR_POOL 8
//`define BR_POOL_ENC 3
//`define LR_POOL 8
//`define LR_POOL_ENC 3
//`define LR_UCODE_POOL 0
//`define CTR_POOL 8
//`define CTR_POOL_ENC 3
//`define CTR_UCODE_POOL 0
//`define XER_POOL 8
//`define XER_POOL_ENC 3
//`define XER_UCODE_POOL 0
//`define RV_FX0_ENTRIES 4
//`define RV_FX0_ENTRIES_ENC 2
//`define RV_FX1_ENTRIES 4
//`define RV_FX1_ENTRIES_ENC 2
//`define RV_LQ_ENTRIES 4
//`define RV_LQ_ENTRIES_ENC 2
//`define RV_AXU0_ENTRIES 4
//`define RV_AXU0_ENTRIES_ENC 2
//`define UCODE_ENTRIES 2
//`define UCODE_ENTRIES_ENC 1

// other interesting to try...
//`define FXU1_ENABLE 0
//`define BUILD_PFETCH 0
//`define INCLUDE_IERAT_BYPASS 0

// things to add in code
// 1. ic_size
// 2. ierat_entries (and/or needs to be replacement code? e.g. no mmu, all hits)
// 3. derat_entries (and/or needs to be replacement code? e.g. no mmu, all hits)

// -----------------------------------------------------------------------------------------------------------------


`define gpr_t 3'b000
`define cr_t 3'b001
`define lr_t 3'b010
`define ctr_t 3'b011
`define xer_t 3'b100
`define spr_t 3'b101
`define axu0_t 3'b110
`define axu1_t 3'b111

`ifdef THREADS1
`define THREADS 1
`define THREAD_POOL_ENC 0
`define THREADS_POOL_ENC 0
`else
`define THREADS 2
`define THREAD_POOL_ENC 1
`define THREADS_POOL_ENC 1
`endif

`define EFF_IFAR_ARCH 62
`define EFF_IFAR_WIDTH 20
`define EFF_IFAR 20
`define REGMODE 6
`define REAL_IFAR_WIDTH 42
`define GPR_WIDTH 64
`define GPR_WIDTH_ENC 6
`define ITAG_SIZE_ENC 7

`define CPL_Q_DEPTH 32
`define CPL_Q_DEPTH_ENC 6
`define GPR_POOL_ENC 6
`define GPR_POOL 64
`define GPR_UCODE_POOL 4
`define FPR_POOL 64
`define FPR_POOL_ENC 6
`define CR_POOL_ENC 5
`define CR_POOL 24
`define CR_UCODE_POOL 1
`define BR_POOL_ENC 3
`define BR_POOL 8
`define LR_POOL_ENC 3
`define LR_POOL 8
`define LR_UCODE_POOL 0
`define CTR_POOL_ENC 3
`define CTR_POOL 8
`define CTR_UCODE_POOL 0
`define XER_POOL_ENC 4
`define XER_POOL 12
`define XER_UCODE_POOL 0

`define EMQ_ENTRIES 4
`define LDSTQ_ENTRIES 16 // ls order queue
`define LDSTQ_ENTRIES_ENC 4
//`define LMQ_ENTRIES 8 // load miss queue
//`define LMQ_ENTRIES_ENC 3
//`define LGQ_ENTRIES 8 // load gather queue

`define STQ_ENTRIES 12 // store queue
`define STQ_ENTRIES_ENC 4
`define STQ_FWD_ENTRIES 4 // number of stq entries that can be forwarded from
`define STQ_DATA_SIZE 64 // 64 or 128 Bit store data sizes supported

`define DC_SIZE 15 // 14 => 16K L1D$, 15 => 32K L1D$
`define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE

`define AXU_SPARE_ENC 3

`define RV_FX0_ENTRIES 12
`define RV_FX0_ENTRIES_ENC 4
`define RV_FX1_ENTRIES 12
`define RV_FX1_ENTRIES_ENC 4
`define RV_LQ_ENTRIES 16
`define RV_LQ_ENTRIES_ENC 4
`define RV_AXU0_ENTRIES 12
`define RV_AXU0_ENTRIES_ENC 4
`define RV_AXU1_ENTRIES 0
`define RV_AXU1_ENTRIES_ENC 1
`define UCODE_ENTRIES 8
`define UCODE_ENTRIES_ENC 3

`define FXU1_ENABLE 1

`define TYPE_WIDTH 3
`define IBUFF_INSTR_WIDTH 70
`define IBUFF_IFAR_WIDTH 20
`define PF_IAR_BITS 12 // number of IAR bits used by prefetch
`define FXU0_PIPE_START 1
`define FXU0_PIPE_END 8
`define FXU1_PIPE_START 1
`define FXU1_PIPE_END 5
`define LQ_LOAD_PIPE_START 4
`define LQ_LOAD_PIPE_END 8
`define LQ_REL_PIPE_START 2
`define LQ_REL_PIPE_END 4
`define IBUFF_DEPTH 16

`define LOAD_CREDITS 8
`define STORE_CREDITS 32

`define IUQ_ENTRIES 4 // Instruction Fetch Queue Size
`define MMQ_ENTRIES 2 // MMU Queue Size

`define CR_WIDTH 4
`define BUILD_PFETCH 1 // 1=> include pfetch in the build, 0=> build without pfetch
`define PF_IFAR_WIDTH 12
`define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch
`define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries)
`define PFETCH_Q_SIZE 8 // number of entries
`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings)
`define XER_WIDTH 10

`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT
`define INIT_IUCR0 16'h00FA // BP enabled

`define INIT_MASK 2'b10
`define RELQ_INCLUDE 0 // Reload Queue Included

`define G_BRANCH_LEN `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1

`define INIT_CPCR0 32'h0C0C100C // 000a aaaa 000b bbbb 000c cccc 000d dddd watermarks: a=fx0 b=fx1 c=ls d=sq ---- um p.543 wrong!; was this in vlog: hex 0C0C100C = 202117132
//`define INIT_CPCR0 32'h01010201 // 1/1/2/1

`define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504
//`define INIT_CPCR1 32'h00010100 // 1/1

// IERAT boot config entry values
`define IERAT_BCFG_EPN_0TO15 0
`define IERAT_BCFG_EPN_16TO31 0
`define IERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G
`define IERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
`define IERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff
`define IERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8181 for 512M, 65535 for 4G
`define IERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
`define IERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page
`define IERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page
`define IERAT_BCFG_ATTR 0 // u0-u3, endian

// DERAT boot config entry values
`define DERAT_BCFG_EPN_0TO15 0
`define DERAT_BCFG_EPN_16TO31 0
`define DERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G
`define DERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
`define DERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff
`define DERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8191 for 512M, 65535 for 4G
`define DERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
`define DERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page
`define DERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page
`define DERAT_BCFG_ATTR 0 // u0-u3, endian

// Do NOT add any defines below this line
`endif //_tri_a2o_vh_

@ -0,0 +1,43 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

// *!****************************************************************
// *! FILENAME : tri_a2o.param
// *! DESCRIPTION : Constants for use throughout core
// *! CONTENTS :
// *!
// *!****************************************************************

`ifndef _tri_vh_
`define _tri_vh_

`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5x Clk
//`define EXPAND_TYPE 1

// Do NOT add any defines below this line
`endif //_tri_vh_

@ -0,0 +1,258 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_128x168_1w_0.v
// *! DESCRIPTION : 128 Entry x 168 bit x 1 way array
// *!
// *!****************************************************************

`include "tri_a2o.vh"

module tri_128x168_1w_0(
gnd,
vdd,
vcs,
nclk,
act,
ccflush_dc,
scan_dis_dc_b,
scan_diag_dc,
abst_scan_in,
repr_scan_in,
time_scan_in,
abst_scan_out,
repr_scan_out,
time_scan_out,
lcb_d_mode_dc,
lcb_clkoff_dc_b,
lcb_act_dis_dc,
lcb_mpw1_dc_b,
lcb_mpw2_dc_b,
lcb_delay_lclkr_dc,
lcb_sg_1,
lcb_time_sg_0,
lcb_repr_sg_0,
lcb_abst_sl_thold_0,
lcb_repr_sl_thold_0,
lcb_time_sl_thold_0,
lcb_ary_nsl_thold_0,
lcb_bolt_sl_thold_0,
tc_lbist_ary_wrt_thru_dc,
abist_en_1,
din_abist,
abist_cmp_en,
abist_raw_b_dc,
data_cmp_abist,
addr_abist,
r_wb_abist,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
write_enable,
addr,
data_in,
data_out
);
parameter addressable_ports = 128; // number of addressable register in this array
parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
parameter port_bitwidth = 168; // bitwidth of ports
parameter ways = 1; // number of ways

// POWER PINS
inout gnd;
inout vdd;
inout vcs;

// CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk;
input act;
input ccflush_dc;
input scan_dis_dc_b;
input scan_diag_dc;

input abst_scan_in;
input repr_scan_in;
input time_scan_in;
output abst_scan_out;
output repr_scan_out;
output time_scan_out;

input lcb_d_mode_dc;
input lcb_clkoff_dc_b;
input lcb_act_dis_dc;
input [0:4] lcb_mpw1_dc_b;
input lcb_mpw2_dc_b;
input [0:4] lcb_delay_lclkr_dc;

input lcb_sg_1;
input lcb_time_sg_0;
input lcb_repr_sg_0;

input lcb_abst_sl_thold_0;
input lcb_repr_sl_thold_0;
input lcb_time_sl_thold_0;
input lcb_ary_nsl_thold_0;
input lcb_bolt_sl_thold_0; // thold for any regs inside backend

input tc_lbist_ary_wrt_thru_dc;
input abist_en_1;
input [0:3] din_abist;
input abist_cmp_en;
input abist_raw_b_dc;
input [0:3] data_cmp_abist;
input [0:6] addr_abist;
input r_wb_abist;

// BOLT-ON
input pc_bo_enable_2; // general bolt-on enable, probably DC
input pc_bo_reset; // execute sticky bit decode
input pc_bo_unload;
input pc_bo_repair; // load repair reg
input pc_bo_shdata; // shift data for timing write
input pc_bo_select; // select for mask and hier writes
output bo_pc_failout; // fail/no-fix reg
output bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;

// PORTS
input write_enable;
input [0:addressbus_width-1] addr;
input [0:port_bitwidth-1] data_in;
output [0:port_bitwidth-1] data_out;

// tri_128x168_1w_0

parameter ramb_base_width = 36;
parameter ramb_base_addr = 9;
parameter ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1; // # of RAMB's per way


// Configuration Statement for NCsim
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;

wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_in;
wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_out[0:ways-1];
wire [0:ramb_base_addr-1] ramb_addr;

wire [0:ways-1] write;
wire tidn;
(* analysis_not_referenced="true" *)
wire unused;
wire [0:(ramb_base_width*ramb_width_mult-1)] unused_dob;


generate
begin
assign tidn = 1'b0;

if (addressbus_width < ramb_base_addr)
begin
assign ramb_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}};
assign ramb_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = addr;
end
if (addressbus_width >= ramb_base_addr)
begin
assign ramb_addr = addr[addressbus_width - ramb_base_addr:addressbus_width - 1];
end

genvar i;
for (i = 0; i < (ramb_base_width * ramb_width_mult); i = i + 1)
begin : din
if (i < port_bitwidth)
begin
assign ramb_data_in[i] = data_in[i];
end
if (i >= port_bitwidth)
begin
assign ramb_data_in[i] = 1'b0;
end
end

genvar w;
for (w = 0; w < ways; w = w + 1)
begin : aw
assign write[w] = write_enable;

genvar x;
for (x = 0; x < ramb_width_mult; x = x + 1)
begin : ax

RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
ram(
.DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]),
.DOB(unused_dob[x * ramb_base_width:x * ramb_base_width + 31]),
.DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
.DOPB(unused_dob[x * ramb_base_width + 32:x * ramb_base_width + 35]),
.ADDRA(ramb_addr),
.ADDRB(ramb_addr),
.CLKA(nclk[0]),
.CLKB(tidn),
.DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
.DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
.DIPA(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
.DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
.ENA(act),
.ENB(tidn),
.SSRA(nclk[1]),
.SSRB(tidn),
.WEA(write[w]),
.WEB(tidn)
);
end //ax
assign data_out[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1];
end //aw
end
endgenerate

assign abst_scan_out = abst_scan_in;
assign repr_scan_out = repr_scan_in;
assign time_scan_out = time_scan_in;

assign bo_pc_failout = 1'b0;
assign bo_pc_diagloop = 1'b0;

assign unused = |({ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, lcb_bolt_sl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, gnd, vdd, vcs, nclk, unused_dob});
endmodule

@ -0,0 +1,335 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

//*****************************************************************************
// Description: Tri Array Wrapper
//
//*****************************************************************************

`include "tri_a2o.vh"

module tri_128x16_1r1w_1(
vdd,
vcs,
gnd,
nclk,
rd_act,
wr_act,
lcb_d_mode_dc,
lcb_clkoff_dc_b,
lcb_mpw1_dc_b,
lcb_mpw2_dc_b,
lcb_delay_lclkr_dc,
ccflush_dc,
scan_dis_dc_b,
scan_diag_dc,
func_scan_in,
func_scan_out,
lcb_sg_0,
lcb_sl_thold_0_b,
lcb_time_sl_thold_0,
lcb_abst_sl_thold_0,
lcb_ary_nsl_thold_0,
lcb_repr_sl_thold_0,
time_scan_in,
time_scan_out,
abst_scan_in,
abst_scan_out,
repr_scan_in,
repr_scan_out,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
wr_abst_act,
abist_rd0_adr,
rd0_abst_act,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
bw,
wr_adr,
rd_adr,
di,
dout
);
parameter addressable_ports = 128; // number of addressable register in this array
parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
parameter port_bitwidth = 16; // bitwidth of ports
parameter ways = 1; // number of ways

// POWER PINS
inout vdd;
inout vcs;
inout gnd;

input [0:`NCLK_WIDTH-1] nclk;

input rd_act;
input wr_act;

// DC TEST PINS
input lcb_d_mode_dc;
input lcb_clkoff_dc_b;
input [0:4] lcb_mpw1_dc_b;
input lcb_mpw2_dc_b;
input [0:4] lcb_delay_lclkr_dc;

input ccflush_dc;
input scan_dis_dc_b;
input scan_diag_dc;
input func_scan_in;
output func_scan_out;

input lcb_sg_0;
input lcb_sl_thold_0_b;
input lcb_time_sl_thold_0;
input lcb_abst_sl_thold_0;
input lcb_ary_nsl_thold_0;
input lcb_repr_sl_thold_0;
input time_scan_in;
output time_scan_out;
input abst_scan_in;
output abst_scan_out;
input repr_scan_in;
output repr_scan_out;

input [0:3] abist_di;
input abist_bw_odd;
input abist_bw_even;
input [0:6] abist_wr_adr;
input wr_abst_act;
input [0:6] abist_rd0_adr;
input rd0_abst_act;
input tc_lbist_ary_wrt_thru_dc;
input abist_ena_1;
input abist_g8t_rd0_comp_ena;
input abist_raw_dc_b;
input [0:3] obs0_abist_cmp;

// BOLT-ON
input lcb_bolt_sl_thold_0;
input pc_bo_enable_2; // general bolt-on enable
input pc_bo_reset; // reset
input pc_bo_unload; // unload sticky bits
input pc_bo_repair; // execute sticky bit decode
input pc_bo_shdata; // shift data for timing write and diag loop
input pc_bo_select; // select for mask and hier writes
output bo_pc_failout; // fail/no-fix reg
output bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;

input [0:15] bw;
input [0:6] wr_adr;
input [0:6] rd_adr;
input [0:15] di;

output [0:15] dout;

// tri_128x16_1r1w_1

// Configuration Statement for NCsim
//for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36;

wire clk;
wire clk2x;
wire [0:8] b0addra;
wire [0:8] b0addrb;
wire wea;
wire web;
wire wren_a;
// Latches
reg reset_q;
reg gate_fq;
wire gate_d;
wire [0:35] r_data_out_1_d;
reg [0:35] r_data_out_1_fq;
wire [0:35] w_data_in_0;

wire [0:35] r_data_out_0_bram;
wire [0:35] r_data_out_1_bram;

wire toggle_d;
reg toggle_q;
wire toggle2x_d;
reg toggle2x_q;

(* analysis_not_referenced="true" *)
wire unused;

assign clk = nclk[0];
assign clk2x = nclk[2];


always @(posedge clk)
begin: rlatch
reset_q <= nclk[1];
end

//
// NEW clk2x gate logic start
//

always @(posedge nclk[0])
begin: tlatch
if (reset_q == 1'b1)
toggle_q <= 1'b1;
else
toggle_q <= toggle_d;
end


always @(posedge nclk[2])
begin: flatch
toggle2x_q <= toggle2x_d;
gate_fq <= gate_d;
r_data_out_1_fq <= r_data_out_1_d;
end

assign toggle_d = (~toggle_q);
assign toggle2x_d = toggle_q;

// should force gate_fq to be on during odd 2x clock (second half of 1x clock).
//gate_d <= toggle_q xor toggle2x_q;
// if you want the first half do the following
assign gate_d = (~(toggle_q ^ toggle2x_q));

assign b0addra[2:8] = wr_adr;
assign b0addrb[2:8] = rd_adr;

// Unused Address Bits
assign b0addra[0:1] = 2'b00;
assign b0addrb[0:1] = 2'b00;

// port a is a read-modify-write port
assign wren_a = ((bw != 16'b0000000000000000 & wr_act == 1'b1)) ? 1'b1 :
1'b0;
assign wea = wren_a & (~(gate_fq)); // write in 2nd half of nclk
assign web = 1'b0;
assign w_data_in_0[0] = (bw[0] == 1'b1) ? di[0] :
r_data_out_0_bram[0];
assign w_data_in_0[1] = (bw[1] == 1'b1) ? di[1] :
r_data_out_0_bram[1];
assign w_data_in_0[2] = (bw[2] == 1'b1) ? di[2] :
r_data_out_0_bram[2];
assign w_data_in_0[3] = (bw[3] == 1'b1) ? di[3] :
r_data_out_0_bram[3];
assign w_data_in_0[4] = (bw[4] == 1'b1) ? di[4] :
r_data_out_0_bram[4];
assign w_data_in_0[5] = (bw[5] == 1'b1) ? di[5] :
r_data_out_0_bram[5];
assign w_data_in_0[6] = (bw[6] == 1'b1) ? di[6] :
r_data_out_0_bram[6];
assign w_data_in_0[7] = (bw[7] == 1'b1) ? di[7] :
r_data_out_0_bram[7];
assign w_data_in_0[8] = (bw[8] == 1'b1) ? di[8] :
r_data_out_0_bram[8];
assign w_data_in_0[9] = (bw[9] == 1'b1) ? di[9] :
r_data_out_0_bram[9];
assign w_data_in_0[10] = (bw[10] == 1'b1) ? di[10] :
r_data_out_0_bram[10];
assign w_data_in_0[11] = (bw[11] == 1'b1) ? di[11] :
r_data_out_0_bram[11];
assign w_data_in_0[12] = (bw[12] == 1'b1) ? di[12] :
r_data_out_0_bram[12];
assign w_data_in_0[13] = (bw[13] == 1'b1) ? di[13] :
r_data_out_0_bram[13];
assign w_data_in_0[14] = (bw[14] == 1'b1) ? di[14] :
r_data_out_0_bram[14];
assign w_data_in_0[15] = (bw[15] == 1'b1) ? di[15] :
r_data_out_0_bram[15];
assign w_data_in_0[16:35] = {20{1'b0}};

assign r_data_out_1_d = r_data_out_1_bram;



RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
bram0a(
.CLKA(clk2x),
.CLKB(clk2x),
.SSRA(reset_q),
.SSRB(reset_q),
.ADDRA(b0addra),
.ADDRB(b0addrb),
.DIA(w_data_in_0[0:31]),
.DIB({32{1'b0}}),
.DOA(r_data_out_0_bram[0:31]),
.DOB(r_data_out_1_bram[0:31]),
.DOPA(r_data_out_0_bram[32:35]),
.DOPB(r_data_out_1_bram[32:35]),
.DIPA(w_data_in_0[32:35]),
.DIPB(4'b0000),
.ENA(1'b1),
.ENB(1'b1),
.WEA(wea),
.WEB(web)
);

assign dout = r_data_out_1_fq[0:15];

assign func_scan_out = func_scan_in;
assign time_scan_out = time_scan_in;
assign abst_scan_out = abst_scan_in;
assign repr_scan_out = repr_scan_in;

assign bo_pc_failout = 1'b0;
assign bo_pc_diagloop = 1'b0;

assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc, rd_act, r_data_out_0_bram[16:35], r_data_out_1_bram[16:35], r_data_out_1_fq[16:35]};
endmodule

@ -0,0 +1,324 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_128x34_4w_1r1w.v
// *! DESCRIPTION : 128 entry x 34 bit x 4 way array,
// *! 1 read & 1 write port
// *!
// *!****************************************************************

`include "tri_a2o.vh"

module tri_128x34_4w_1r1w(
gnd,
vdd,
vcs,
nclk,
rd_act,
wr_act,
sg_0,
abst_sl_thold_0,
ary_nsl_thold_0,
time_sl_thold_0,
repr_sl_thold_0,
func_sl_thold_0_b,
func_force,
clkoff_dc_b,
ccflush_dc,
scan_dis_dc_b,
scan_diag_dc,
d_mode_dc,
mpw1_dc_b,
mpw2_dc_b,
delay_lclkr_dc,
wr_abst_act,
rd0_abst_act,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
abist_rd0_adr,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp,
abst_scan_in,
time_scan_in,
repr_scan_in,
func_scan_in,
abst_scan_out,
time_scan_out,
repr_scan_out,
func_scan_out,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
wr_way,
wr_addr,
data_in,
rd_addr,
data_out
);
parameter addressable_ports = 128; // number of addressable register in this array
parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
parameter port_bitwidth = 34; // bitwidth of ports
parameter ways = 4; // number of ways

// POWER PINS
inout gnd;
inout vdd;
(* analysis_not_referenced="true" *)
inout vcs;
// CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk;
input rd_act;
input wr_act;
input sg_0;
input abst_sl_thold_0;
input ary_nsl_thold_0;
input time_sl_thold_0;
input repr_sl_thold_0;
input func_sl_thold_0_b;
input func_force;
input clkoff_dc_b;
input ccflush_dc;
input scan_dis_dc_b;
input scan_diag_dc;
input d_mode_dc;
input [0:4] mpw1_dc_b;
input mpw2_dc_b;
input [0:4] delay_lclkr_dc;
// ABIST
input wr_abst_act;
input rd0_abst_act;
input [0:3] abist_di;
input abist_bw_odd;
input abist_bw_even;
input [0:addressbus_width-1] abist_wr_adr;
input [0:addressbus_width-1] abist_rd0_adr;
input tc_lbist_ary_wrt_thru_dc;
input abist_ena_1;
input abist_g8t_rd0_comp_ena;
input abist_raw_dc_b;
input [0:3] obs0_abist_cmp;
// Scan
input [0:1] abst_scan_in;
input time_scan_in;
input repr_scan_in;
input func_scan_in;
output [0:1] abst_scan_out;
output time_scan_out;
output repr_scan_out;
output func_scan_out;
// BOLT-ON
input lcb_bolt_sl_thold_0;
input pc_bo_enable_2; // general bolt-on enable
input pc_bo_reset; // reset
input pc_bo_unload; // unload sticky bits
input pc_bo_repair; // execute sticky bit decode
input pc_bo_shdata; // shift data for timing write and diag loop
input [0:1] pc_bo_select; // select for mask and hier writes
output [0:1] bo_pc_failout; // fail/no-fix reg
output [0:1] bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;
// Write Ports
input [0:ways-1] wr_way;
input [0:addressbus_width-1] wr_addr;
input [0:port_bitwidth*ways-1] data_in;
// Read Ports
input [0:addressbus_width-1] rd_addr;
output [0:port_bitwidth*ways-1] data_out;

// tri_128x34_4w_1r1w

parameter ramb_base_width = 36;
parameter ramb_base_addr = 9;
parameter ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1; // # of RAMB's per way


// Configuration Statement for NCsim
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;

localparam rd_act_offset = 0;
localparam data_out_offset = rd_act_offset + 1;
localparam scan_right = data_out_offset + port_bitwidth*ways - 1;

wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_in[0:ways-1];
wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_out[0:ways-1];
wire [0:ramb_base_addr-1] ramb_rd_addr;
wire [0:ramb_base_addr-1] ramb_wr_addr;

wire rd_act_l2;
wire [0:port_bitwidth*ways-1] data_out_d;
wire [0:port_bitwidth*ways-1] data_out_l2;

wire tidn;
(* analysis_not_referenced="true" *)
wire unused;
wire [31:0] dob;
wire [3:0] dopb;
wire [0:scan_right] func_sov;

generate
begin
assign tidn = 1'b0;

if (addressbus_width < ramb_base_addr)
begin
assign ramb_rd_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}};
assign ramb_rd_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = rd_addr;

assign ramb_wr_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}};
assign ramb_wr_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = wr_addr;
end
if (addressbus_width >= ramb_base_addr)
begin
assign ramb_rd_addr = rd_addr[addressbus_width - ramb_base_addr:addressbus_width - 1];
assign ramb_wr_addr = wr_addr[addressbus_width - ramb_base_addr:addressbus_width - 1];
end

genvar w;
for (w = 0; w < ways; w = w + 1)
begin : dw
genvar i;
for (i = 0; i < (ramb_base_width * ramb_width_mult); i = i + 1)
begin : din
if (i < port_bitwidth)
begin
assign ramb_data_in[w][i] = data_in[w * port_bitwidth + i];
end
if (i >= port_bitwidth)
begin
assign ramb_data_in[w][i] = 1'b0;
end
end
end

//genvar w;
for (w = 0; w < ways; w = w + 1)
begin : aw
genvar x;
for (x = 0; x < ramb_width_mult; x = x + 1)
begin : ax

RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
arr(
.DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]),
.DOB(dob),
.DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
.DOPB(dopb),
.ADDRA(ramb_rd_addr),
.ADDRB(ramb_wr_addr),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]),
.DIB(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]),
.DIPA(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
.DIPB(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
.ENA(rd_act),
.ENB(wr_act),
.SSRA(nclk[1]),
.SSRB(nclk[1]),
.WEA(tidn),
.WEB(wr_way[w])
);
end //ax
assign data_out_d[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1];
end //aw
end
endgenerate

assign data_out = data_out_l2;

tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(1'b1),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(func_force),
.delay_lclkr(delay_lclkr_dc[0]),
.mpw1_b(mpw1_dc_b[0]),
.mpw2_b(mpw2_dc_b),
.d_mode(d_mode_dc),
.scin(1'b0),
.scout(func_sov[rd_act_offset]),
.din(rd_act),
.dout(rd_act_l2)
);

tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rd_act_l2),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(func_force),
.delay_lclkr(delay_lclkr_dc[0]),
.mpw1_b(mpw1_dc_b[0]),
.mpw2_b(mpw2_dc_b),
.d_mode(d_mode_dc),
.scin({port_bitwidth*ways{1'b0}}),
.scout(func_sov[data_out_offset:data_out_offset + (port_bitwidth*ways) - 1]),
.din(data_out_d),
.dout(data_out_l2)
);

assign abst_scan_out = {tidn, tidn};
assign time_scan_out = tidn;
assign repr_scan_out = tidn;
assign func_scan_out = tidn;

assign bo_pc_failout = {tidn, tidn};
assign bo_pc_diagloop = {tidn, tidn};

assign unused = | ({nclk[2:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, dob, dopb, func_sov, ramb_data_out[0][34:35], ramb_data_out[1][34:35], ramb_data_out[2][34:35], ramb_data_out[3][34:35]});

endmodule

@ -0,0 +1,637 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ps / 1 ps

//*****************************************************************************
// Description: Tri-Lam Array Wrapper
//
//*****************************************************************************

`include "tri_a2o.vh"

module tri_144x78_2r4w(
// Inputs
// Power
inout vdd,
inout gnd,
// Clock & Scan
input [0:`NCLK_WIDTH-1] nclk,

//-------------------------------------------------------------------
// Pervasive
//-------------------------------------------------------------------
input delay_lclkr_dc,
input mpw1_dc_b,
input mpw2_dc_b,
input func_sl_force,
input func_sl_thold_0_b,
input func_slp_sl_force,
input func_slp_sl_thold_0_b,
input sg_0,
input scan_in,
output scan_out,

//-------------------------------------------------------------------
// Read Port
//-------------------------------------------------------------------
input r_late_en_1,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_1,
output [64-`GPR_WIDTH:77] r_data_out_1,
input r_late_en_2,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_2,
output [64-`GPR_WIDTH:77] r_data_out_2,

//-------------------------------------------------------------------
// Write Port
//-------------------------------------------------------------------
input w_late_en_1,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_1,
input [64-`GPR_WIDTH:77] w_data_in_1,
input w_late_en_2,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_2,
input [64-`GPR_WIDTH:77] w_data_in_2,
input w_late_en_3,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_3,
input [64-`GPR_WIDTH:77] w_data_in_3,
input w_late_en_4,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_4,
input [64-`GPR_WIDTH:77] w_data_in_4
);

// Configuration Statement for NCsim
//for all:RAM64X1D use entity unisim.RAM64X1D;

parameter tiup = 1'b1;
parameter tidn = 1'b0;

//-------------------------------------------------------------------
// Signals
//-------------------------------------------------------------------
//reg write_en;
//reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] write_addr;
//reg [64-`GPR_WIDTH:77] write_data;
wire write_en;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] write_addr;
wire [64-`GPR_WIDTH:77] write_data;

wire [0:(`GPR_POOL*`THREADS-1)/64] write_en_arr;
wire [0:5] write_addr_arr;
wire [0:1] wr_mux_ctrl;

//-------------------------------------------------------------------
// Latch Signals
//-------------------------------------------------------------------
wire w1e_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w1a_q;
wire [64-`GPR_WIDTH:77] w1d_q;
wire w2e_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w2a_q;
wire [64-`GPR_WIDTH:77] w2d_q;
wire w3e_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w3a_q;
wire [64-`GPR_WIDTH:77] w3d_q;
wire w4e_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w4a_q;
wire [64-`GPR_WIDTH:77] w4d_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q;
wire [0:5] read1_addr_arr;
wire [0:5] read2_addr_arr;
wire [0:(`GPR_POOL*`THREADS-1)/64] read1_en_arr;
wire [0:(`GPR_POOL*`THREADS-1)/64] read2_en_arr;
reg [64-`GPR_WIDTH:77] read1_data;
reg [64-`GPR_WIDTH:77] read2_data;
wire [64-`GPR_WIDTH:77] r1d_array[0:(`GPR_POOL*`THREADS-1)/64];
wire [64-`GPR_WIDTH:77] r2d_array[0:(`GPR_POOL*`THREADS-1)/64];
wire [64-`GPR_WIDTH:77] r1d_d;
wire [64-`GPR_WIDTH:77] r2d_d;
wire [64-`GPR_WIDTH:77] r1d_q;
wire [64-`GPR_WIDTH:77] r2d_q;

(* analysis_not_referenced="true" *)
wire unused;
wire [64-`GPR_WIDTH:77] unused_port;
wire [64-`GPR_WIDTH:77] unused_port2;

//-------------------------------------------------------------------
// Scanchain
//-------------------------------------------------------------------
parameter w1e_offset = 0;
parameter w1a_offset = w1e_offset + 1;
parameter w1d_offset = w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
parameter w2e_offset = w1d_offset + (`GPR_WIDTH+14);
parameter w2a_offset = w2e_offset + 1;
parameter w2d_offset = w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
parameter w3e_offset = w2d_offset + (`GPR_WIDTH+14);
parameter w3a_offset = w3e_offset + 1;
parameter w3d_offset = w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
parameter w4e_offset = w3d_offset + (`GPR_WIDTH+14);
parameter w4a_offset = w4e_offset + 1;
parameter w4d_offset = w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
parameter r1a_offset = w4d_offset + (`GPR_WIDTH+14);
parameter r2a_offset = r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
parameter r1d_offset = r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
parameter r2d_offset = r1d_offset + (`GPR_WIDTH+14);
parameter scan_right = r2d_offset + (`GPR_WIDTH+14);
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;

generate
begin

// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// Read Control
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// BYPASS

assign r1d_d = read1_data;

assign r2d_d = read2_data;

assign r_data_out_1 = r1d_q;
assign r_data_out_2 = r2d_q;

// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// Write Control
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
assign wr_mux_ctrl = {nclk[0], nclk[2]};

//wtf moved these here to try to get them to work in icarus - they seem to now
assign write_en = ((wr_mux_ctrl == 2'b00) ? w_late_en_1 :
(wr_mux_ctrl == 2'b01) ? w_late_en_2 :
(wr_mux_ctrl == 2'b10) ? w_late_en_3 :
w_late_en_4);

assign write_addr = ((wr_mux_ctrl == 2'b00) ? w_addr_in_1 :
(wr_mux_ctrl == 2'b01) ? w_addr_in_2 :
(wr_mux_ctrl == 2'b10) ? w_addr_in_3 :
w_addr_in_4);

assign write_data = ((wr_mux_ctrl == 2'b00) ? w_data_in_1 :
(wr_mux_ctrl == 2'b01) ? w_data_in_2 :
(wr_mux_ctrl == 2'b10) ? w_data_in_3 :
w_data_in_4);


//always @ ( * )
//begin
//write_addr = #10 ((wr_mux_ctrl == 2'b00) ? w_addr_in_1 :
// (wr_mux_ctrl == 2'b01) ? w_addr_in_2 :
// (wr_mux_ctrl == 2'b10) ? w_addr_in_3 :
// w_addr_in_4);

//write_en = #10 ((wr_mux_ctrl == 2'b00) ? w_late_en_1 :
// (wr_mux_ctrl == 2'b01) ? w_late_en_2 :
// (wr_mux_ctrl == 2'b10) ? w_late_en_3 :
// w_late_en_4);

// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// Depth Control
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

//write_data = #10 ((wr_mux_ctrl == 2'b00) ? w_data_in_1 :
// (wr_mux_ctrl == 2'b01) ? w_data_in_2 :
// (wr_mux_ctrl == 2'b10) ? w_data_in_3 :
// w_data_in_4);
//end

if (((`GPR_POOL*`THREADS - 1)/64) == 0)
begin : depth1
if (`GPR_POOL_ENC+`THREADS_POOL_ENC < 6)
begin
assign write_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}};
assign read1_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}};
assign read2_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}};
end

assign write_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = write_addr;
assign read1_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r1a_q;
assign read2_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r2a_q;
assign write_en_arr[0] = write_en;
assign read1_en_arr[0] = 1'b1;
assign read2_en_arr[0] = 1'b1;
end

if (((`GPR_POOL*`THREADS - 1)/64) != 0)
begin : depthMulti
assign write_addr_arr = write_addr[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1];
assign read1_addr_arr = r1a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1];
assign read2_addr_arr = r2a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1];

genvar wen;
for (wen = 0; wen <= ((`GPR_POOL*`THREADS - 1)/64); wen = wen + 1)
begin : wrenGen
wire wen_match = wen;
assign write_en_arr[wen] = write_en & (write_addr[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match);
assign read1_en_arr[wen] = r1a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match;
assign read2_en_arr[wen] = r2a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match;
end
end

always @( * )
begin: rdDataMux
reg [64-`GPR_WIDTH:77] rd1_data;
reg [64-`GPR_WIDTH:77] rd2_data;
//(* analysis_not_referenced="true" *)
integer rdArr;
rd1_data = {`GPR_WIDTH+14{1'b0}};
rd2_data = {`GPR_WIDTH+14{1'b0}};

for (rdArr = 0; rdArr <= ((`GPR_POOL*`THREADS - 1)/64); rdArr = rdArr + 1)
begin
rd1_data = (r1d_array[rdArr] & {`GPR_WIDTH+14{read1_en_arr[rdArr]}}) | rd1_data;
rd2_data = (r2d_array[rdArr] & {`GPR_WIDTH+14{read2_en_arr[rdArr]}}) | rd2_data;
end
read1_data = rd1_data;
read2_data = rd2_data;
end

genvar depth;
for (depth = 0; depth <= ((`GPR_POOL*`THREADS - 1)/64); depth = depth + 1)
begin : depth_loop
genvar i;
for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1)
begin : r1
RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_1(
.SPO(unused_port[i]),
.DPO(r1d_array[depth][i]), // Port A 1-bit data output

.A0(write_addr_arr[5]), // Port A - Write Address (A0-A5)
.A1(write_addr_arr[4]),
.A2(write_addr_arr[3]),
.A3(write_addr_arr[2]),
.A4(write_addr_arr[1]),
.A5(write_addr_arr[0]),

//.A(write_addr_arr),
.D(write_data[i]), // Port A 1-bit data input

.DPRA0(read1_addr_arr[5]), // Port B - Read Address (DPRA0-DPRA5)
.DPRA1(read1_addr_arr[4]),
.DPRA2(read1_addr_arr[3]),
.DPRA3(read1_addr_arr[2]),
.DPRA4(read1_addr_arr[1]),
.DPRA5(read1_addr_arr[0]),

//.DPRA(read1_addr_arr),
.WCLK(nclk[3]), // Port A write clock input : clk4x
.WE(write_en_arr[depth]) // Port A write enable input
);
end

//genvar i;
for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1)
begin : r2
RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_2(
.SPO(unused_port2[i]),
.DPO(r2d_array[depth][i]), // Port A 1-bit data output

.A0(write_addr_arr[5]), // Port A - Write Address (A0-A5)
.A1(write_addr_arr[4]),
.A2(write_addr_arr[3]),
.A3(write_addr_arr[2]),
.A4(write_addr_arr[1]),
.A5(write_addr_arr[0]),

//.A(write_addr_arr),
.D(write_data[i]), // Port A 1-bit data input

.DPRA0(read2_addr_arr[5]), // Port B - Read Address (DPRA0-DPRA5)
.DPRA1(read2_addr_arr[4]),
.DPRA2(read2_addr_arr[3]),
.DPRA3(read2_addr_arr[2]),
.DPRA4(read2_addr_arr[1]),
.DPRA5(read2_addr_arr[0]),

//.DPRA(read2_addr_arr),
.WCLK(nclk[3]), // Port A write clock input : clk4x
.WE(write_en_arr[depth]) // Port A write enable input
);
end
end
end
endgenerate

//----------------------------------------------------------------------------------------------------------------------------------------
// Latches
//----------------------------------------------------------------------------------------------------------------------------------------

tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w1e_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w1e_offset]),
.scout(sov[w1e_offset]),
.din(w_late_en_1),
.dout(w1e_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w1a_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.scout(sov[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.din(w_addr_in_1),
.dout(w1a_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w1d_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]),
.scout(sov[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]),
.din(w_data_in_1[64 - `GPR_WIDTH:77]),
.dout(w1d_q)
);

tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w2e_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w2e_offset]),
.scout(sov[w2e_offset]),
.din(w_late_en_2),
.dout(w2e_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w2a_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.scout(sov[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.din(w_addr_in_2),
.dout(w2a_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w2d_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]),
.scout(sov[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]),
.din(w_data_in_2[64 - `GPR_WIDTH:77]),
.dout(w2d_q)
);

tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w3e_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w3e_offset]),
.scout(sov[w3e_offset]),
.din(w_late_en_3),
.dout(w3e_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w3a_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.scout(sov[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.din(w_addr_in_3),
.dout(w3a_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w3d_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]),
.scout(sov[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]),
.din(w_data_in_3[64 - `GPR_WIDTH:77]),
.dout(w3d_q)
);

tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w4e_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w4e_offset]),
.scout(sov[w4e_offset]),
.din(w_late_en_4),
.dout(w4e_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w4a_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.scout(sov[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.din(w_addr_in_4),
.dout(w4a_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w4d_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]),
.scout(sov[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]),
.din(w_data_in_4[64 - `GPR_WIDTH:77]),
.dout(w4d_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r1a_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.scout(sov[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.din(r_addr_in_1),
.dout(r1a_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r2a_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.scout(sov[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.din(r_addr_in_2),
.dout(r2a_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r1d_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]),
.scout(sov[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]),
.din(r1d_d),
.dout(r1d_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r2d_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]),
.scout(sov[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]),
.din(r2d_d),
.dout(r2d_q)
);

assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
assign scan_out = sov[0];

assign unused = | {unused_port, unused_port2, func_slp_sl_force, func_slp_sl_thold_0_b};
endmodule

@ -0,0 +1,513 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_256x144_8w_1r1w.v
// *! DESCRIPTION : 256 Entry x 144 bit x 8 way array, 9 bit writeable
// *!
// *!****************************************************************

`include "tri_a2o.vh"

module tri_256x144_8w_1r1w(
gnd,
vdd,
vcs,
nclk,
rd_act,
wr_act,
sg_0,
abst_sl_thold_0,
ary_nsl_thold_0,
time_sl_thold_0,
repr_sl_thold_0,
func_sl_force,
func_sl_thold_0_b,
g8t_clkoff_dc_b,
ccflush_dc,
scan_dis_dc_b,
scan_diag_dc,
g8t_d_mode_dc,
g8t_mpw1_dc_b,
g8t_mpw2_dc_b,
g8t_delay_lclkr_dc,
d_mode_dc,
mpw1_dc_b,
mpw2_dc_b,
delay_lclkr_dc,
wr_abst_act,
rd0_abst_act,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
abist_rd0_adr,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp,
abst_scan_in,
time_scan_in,
repr_scan_in,
func_scan_in,
abst_scan_out,
time_scan_out,
repr_scan_out,
func_scan_out,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
wr_way,
wr_addr,
data_in0,
data_in1,
rd_addr,
data_out
);
parameter addressable_ports = 256; // number of addressable register in this array
parameter addressbus_width = 8; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
parameter port_bitwidth = 144; // bitwidth of ports (per way)
parameter bit_write_type = 9; // gives the number of bits that shares one write-enable; must divide evenly into array
parameter ways = 8; // number of ways

// POWER PINS
inout gnd;
inout vdd;
inout vcs;

// CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk;
input [0:7] rd_act;
input [0:7] wr_act;
input sg_0;
input abst_sl_thold_0;
input ary_nsl_thold_0;
input time_sl_thold_0;
input repr_sl_thold_0;
input func_sl_force;
input func_sl_thold_0_b;
input g8t_clkoff_dc_b;
input ccflush_dc;
input scan_dis_dc_b;
input scan_diag_dc;
input g8t_d_mode_dc;
input [0:4] g8t_mpw1_dc_b;
input g8t_mpw2_dc_b;
input [0:4] g8t_delay_lclkr_dc;
input d_mode_dc;
input mpw1_dc_b;
input mpw2_dc_b;
input delay_lclkr_dc;

// ABIST
input wr_abst_act;
input rd0_abst_act;
input [0:3] abist_di;
input abist_bw_odd;
input abist_bw_even;
input [0:addressbus_width-1] abist_wr_adr;
input [0:addressbus_width-1] abist_rd0_adr;
input tc_lbist_ary_wrt_thru_dc;
input abist_ena_1;
input abist_g8t_rd0_comp_ena;
input abist_raw_dc_b;
input [0:3] obs0_abist_cmp;

// SCAN
input [0:3] abst_scan_in;
input time_scan_in;
input repr_scan_in;
input [0:3] func_scan_in;
output [0:3] abst_scan_out;
output time_scan_out;
output repr_scan_out;
output [0:3] func_scan_out;

// BOLT-ON
input lcb_bolt_sl_thold_0;
input pc_bo_enable_2; // general bolt-on enable
input pc_bo_reset; // reset
input pc_bo_unload; // unload sticky bits
input pc_bo_repair; // execute sticky bit decode
input pc_bo_shdata; // shift data for timing write and diag loop
input [0:3] pc_bo_select; // select for mask and hier writes
output [0:3] bo_pc_failout; // fail/no-fix reg
output [0:3] bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;

// FUNCTIONAL PORTS
input [0:ways-1] wr_way;
input [0:(addressbus_width-1)] wr_addr;
input [0:(port_bitwidth-1)] data_in0;
input [0:(port_bitwidth-1)] data_in1;
input [0:(addressbus_width-1)] rd_addr;
output [0:(port_bitwidth*ways-1)] data_out;

parameter ramb_base_addr = 16;
parameter dataWidth = ((((port_bitwidth - 1)/36) + 1) * 36) - 1;
parameter numBytes = (dataWidth/9);
parameter addresswidth = addressbus_width;
parameter rd_act_offset = 0;
parameter data_out_offset = rd_act_offset + ways;
parameter scan_right = data_out_offset + (port_bitwidth*ways) - 1;

wire [0:dataWidth] data_in0_pad;
wire [0:dataWidth] data_in1_pad;
wire [0:dataWidth] data_in_swzl[0:ways-1];
wire [0:dataWidth] p0_data_out_pad[0:ways-1];
wire [0:dataWidth] p1_data_out_pad[0:ways-1];
wire [0:(dataWidth-(dataWidth)/9)-1] p0_arr_data_in[0:ways-1];
wire [0:(dataWidth)/9] p0_arr_par_in[0:ways-1];
wire [0:(dataWidth-(dataWidth)/9)-1] p1_arr_data_in[0:ways-1];
wire [0:(dataWidth)/9] p1_arr_par_in[0:ways-1];
wire [0:(dataWidth-(dataWidth)/9)-1] p0_arr_data_out[0:ways-1];
wire [0:(dataWidth)/9] p0_arr_par_out[0:ways-1];
wire [0:(dataWidth-(dataWidth)/9)-1] p1_arr_data_out[0:ways-1];
wire [0:(dataWidth)/9] p1_arr_par_out[0:ways-1];
wire [0:ramb_base_addr-1] ramb_rd_addr;
wire [0:ramb_base_addr-1] ramb_wr_addr;
wire [0:((((port_bitwidth-1)/36)+1)*4)-1] p0_wayEn[0:ways-1];
wire [0:((((port_bitwidth-1)/36)+1)*4)-1] p1_wayEn[0:ways-1];
wire [0:(port_bitwidth*ways-1)] p0_data_out_swzl;
wire [0:(port_bitwidth*ways-1)] p1_data_out_swzl;
wire [0:(port_bitwidth*ways-1)] data_out_fix;
wire [0:((port_bitwidth-1)/36)] cascadeoutlata;
wire [0:((port_bitwidth-1)/36)] cascadeoutlatb;
wire [0:((port_bitwidth-1)/36)] cascadeoutrega;
wire [0:((port_bitwidth-1)/36)] cascadeoutregb;
wire [0:ways-1] rd_act_d;
wire [0:ways-1] rd_act_q;
wire [0:(port_bitwidth*ways)-1] data_out_d;
wire [0:(port_bitwidth*ways)-1] data_out_b_q;

wire [0:ways-1] my_d1clk;
wire [0:ways-1] my_d2clk;
wire [0:`NCLK_WIDTH-1] my_lclk[0:ways-1];
wire tiup;
wire [0:scan_right] siv;
wire [0:scan_right] sov;

(* analysis_not_referenced="true" *)
wire unused;

generate begin
// Read/Write Port Address Generate
assign ramb_rd_addr[11:15] = 5'b0;
assign ramb_wr_addr[11:15] = 5'b0;
assign rd_act_d = rd_act;
assign tiup = 1'b1;

genvar bb;
genvar way;
genvar b;
for (bb = 0; bb <= numBytes; bb = bb + 1) begin : swzl
for (way = 0; way < ways; way = way + 1) begin : perWay
if (way < (ways/2)) begin : fhalf
assign data_in_swzl[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)] = {data_in0_pad[bb + (0 * (numBytes + 1))], data_in0_pad[bb + (1 * (numBytes + 1))],
data_in0_pad[bb + (2 * (numBytes + 1))], data_in0_pad[bb + (3 * (numBytes + 1))],
data_in0_pad[bb + (4 * (numBytes + 1))], data_in0_pad[bb + (5 * (numBytes + 1))],
data_in0_pad[bb + (6 * (numBytes + 1))], data_in0_pad[bb + (7 * (numBytes + 1))]};
assign data_in_swzl[way][(((bb * 8) + bb) + 8)] = data_in0_pad[bb + (8 * (numBytes + 1))];
end
if (way >= (ways/2)) begin : shalf
assign data_in_swzl[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)] = {data_in1_pad[bb + (0 * (numBytes + 1))], data_in1_pad[bb + (1 * (numBytes + 1))],
data_in1_pad[bb + (2 * (numBytes + 1))], data_in1_pad[bb + (3 * (numBytes + 1))],
data_in1_pad[bb + (4 * (numBytes + 1))], data_in1_pad[bb + (5 * (numBytes + 1))],
data_in1_pad[bb + (6 * (numBytes + 1))], data_in1_pad[bb + (7 * (numBytes + 1))]};
assign data_in_swzl[way][(((bb * 8) + bb) + 8)] = data_in1_pad[bb + (8 * (numBytes + 1))];
end
end
end

genvar t;
for (t = 0; t < 11; t = t + 1) begin : rambAddrCalc
if (t < (11-addresswidth)) begin
assign ramb_rd_addr[t] = 1'b0;
assign ramb_wr_addr[t] = 1'b0;
end
if (t >= (11-addresswidth)) begin
assign ramb_rd_addr[t] = rd_addr[t - (11 - addresswidth)];
assign ramb_wr_addr[t] = wr_addr[t - (11 - addresswidth)];
end
end

for (b = 0; b <= dataWidth; b = b + 1) begin : dFixUp
if (b < port_bitwidth) begin
assign data_in0_pad[b] = data_in0[b];
assign data_in1_pad[b] = data_in1[b];
end
if (b >= port_bitwidth) begin
assign data_in0_pad[b] = 1'b0;
assign data_in1_pad[b] = 1'b0;
end
end

//genvar way;
for (way = 0; way < ways; way = way + 1) begin : NwayDatInFix
//genvar bb;
for (bb = 0; bb <= (dataWidth)/9; bb = bb + 1) begin : dFixUp
assign p0_arr_data_in[way][bb * 8:(bb * 8) + 7] = 8'h00;
assign p0_arr_par_in[way][bb] = 1'b0;
assign p1_arr_data_in[way][bb * 8:(bb * 8) + 7] = data_in_swzl[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)];
assign p1_arr_par_in[way][bb] = data_in_swzl[way][(((bb * 8) + bb) + 8)];
end
end

//genvar way;
for (way = 0; way < ways; way = way + 1) begin : NwayDatOutFix
//genvar bb;
for (bb = 0; bb <= (dataWidth)/9; bb = bb + 1) begin : dFixUp
assign p0_data_out_pad[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)] = p0_arr_data_out[way][bb * 8:(bb * 8) + 7];
assign p0_data_out_pad[way][(((bb * 8) + bb) + 8)] = p0_arr_par_out[way][bb];
assign p1_data_out_pad[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)] = p1_arr_data_out[way][bb * 8:(bb * 8) + 7];
assign p1_data_out_pad[way][(((bb * 8) + bb) + 8)] = p1_arr_par_out[way][bb];
end
end

//genvar way;
for (way = 0; way < ways; way = way + 1) begin : NwayDatOut
assign p0_data_out_swzl[way * port_bitwidth:(way * port_bitwidth) + port_bitwidth - 1] = p0_data_out_pad[way][0:port_bitwidth - 1];
assign p1_data_out_swzl[way * port_bitwidth:(way * port_bitwidth) + port_bitwidth - 1] = p1_data_out_pad[way][0:port_bitwidth - 1];

//genvar bb;
for (bb = 0; bb <= numBytes; bb = bb + 1) begin : swzl
assign data_out_fix[(way * port_bitwidth) + (0 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 0];
assign data_out_fix[(way * port_bitwidth) + (1 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 1];
assign data_out_fix[(way * port_bitwidth) + (2 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 2];
assign data_out_fix[(way * port_bitwidth) + (3 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 3];
assign data_out_fix[(way * port_bitwidth) + (4 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 4];
assign data_out_fix[(way * port_bitwidth) + (5 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 5];
assign data_out_fix[(way * port_bitwidth) + (6 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 6];
assign data_out_fix[(way * port_bitwidth) + (7 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 7];
assign data_out_fix[(way * port_bitwidth) + (8 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 8];
end
end
assign data_out_d = data_out_fix;

assign data_out = ~data_out_b_q;

//genvar way;
for (way = 0; way < ways; way = way + 1) begin : Nways
//genvar bb;
for (bb = 0; bb < ((((port_bitwidth - 1)/36) + 1) * 4); bb = bb + 1) begin : BEn
if (bb <= (port_bitwidth - 1)/9) begin
assign p0_wayEn[way][bb] = 1'b0;
assign p1_wayEn[way][bb] = wr_way[way];
end
if (bb > (port_bitwidth - 1)/9) begin
assign p0_wayEn[way][bb] = 1'b0;
assign p1_wayEn[way][bb] = 1'b0;
end
end

// Port A => Read Port
// Port B => Write Port
genvar arr;
for (arr = 0; arr <= ((port_bitwidth - 1)/36); arr = arr + 1) begin : Narrs
RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) wayArr(
.CASCADEOUTLATA(cascadeoutlata[arr]),
.CASCADEOUTLATB(cascadeoutlatb[arr]),
.CASCADEOUTREGA(cascadeoutrega[arr]),
.CASCADEOUTREGB(cascadeoutregb[arr]),
.DOA(p0_arr_data_out[way][(arr * 32) + 0:(arr * 32) + 31]),
.DOB(p1_arr_data_out[way][(arr * 32) + 0:(arr * 32) + 31]),
.DOPA(p0_arr_par_out[way][(arr * 4) + 0:(arr * 4) + 3]),
.DOPB(p1_arr_par_out[way][(arr * 4) + 0:(arr * 4) + 3]),
.ADDRA(ramb_rd_addr),
.ADDRB(ramb_wr_addr),
.CASCADEINLATA(1'b0),
.CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(p0_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]),
.DIB(p1_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]),
.DIPA(p0_arr_par_in[way][(arr * 4) + 0:(arr * 4) + 3]),
.DIPB(p1_arr_par_in[way][(arr * 4) + 0:(arr * 4) + 3]),
.ENA(rd_act[way]),
.ENB(wr_act[way]),
.REGCEA(1'b0),
.REGCEB(1'b0),
.SSRA(nclk[1]), //sreset
.SSRB(nclk[1]), //sreset
.WEA(p0_wayEn[way][(arr * 4) + 0:(arr * 4) + 3]),
.WEB(p1_wayEn[way][(arr * 4) + 0:(arr * 4) + 3])
);
end
end //Nways

assign abst_scan_out = 4'b0;
assign time_scan_out = 1'b0;
assign repr_scan_out = 1'b0;
assign bo_pc_failout = 4'h0;
assign bo_pc_diagloop = 4'h0;
end
endgenerate

assign unused = |({
cascadeoutlata ,
cascadeoutlatb ,
cascadeoutrega ,
cascadeoutregb ,
nclk[0:`NCLK_WIDTH-1] ,
gnd ,
vdd ,
vcs ,
sg_0 ,
ary_nsl_thold_0 ,
abst_sl_thold_0 ,
time_sl_thold_0 ,
repr_sl_thold_0 ,
g8t_clkoff_dc_b,
ccflush_dc,
scan_dis_dc_b,
scan_diag_dc,
g8t_d_mode_dc,
g8t_mpw1_dc_b,
g8t_mpw2_dc_b,
g8t_delay_lclkr_dc,
wr_abst_act,
rd0_abst_act,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
abist_rd0_adr,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp,
abst_scan_in,
time_scan_in,
repr_scan_in,
func_scan_in,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
p1_data_out_swzl});

// ###############################################################
// ## Latches
// ###############################################################
tri_rlmreg_p #(.WIDTH(ways), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[rd_act_offset:rd_act_offset + ways - 1]),
.scout(sov[rd_act_offset:rd_act_offset + ways - 1]),
.din(rd_act_d),
.dout(rd_act_q)
);

generate begin : wayReg
genvar way;
for (way=0; way<ways; way=way+1) begin : wayReg
// ###############################################################
// ## LCB
// ###############################################################
tri_lcbnd my_lcb(
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.force_t(func_sl_force),
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(rd_act_q[way]),
.sg(sg_0),
.thold_b(func_sl_thold_0_b),
.d1clk(my_d1clk[way]),
.d2clk(my_d2clk[way]),
.lclk(my_lclk[way])
);

// ###############################################################
// ## Placed Latch
// ###############################################################
tri_inv_nlats #(.WIDTH(port_bitwidth), .INIT(0), .BTR("NLI0001_X4_A12TH"), .NEEDS_SRESET(0)) data_out_reg(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk[way]),
.d1clk(my_d1clk[way]),
.d2clk(my_d2clk[way]),
.scanin(siv[data_out_offset + (port_bitwidth*way):data_out_offset + (port_bitwidth*(way+1)) - 1]),
.scanout(sov[data_out_offset + (port_bitwidth*way):data_out_offset + (port_bitwidth*(way+1)) - 1]),
.d(data_out_d[(way*port_bitwidth):((way+1)*port_bitwidth)-1]),
.qb(data_out_b_q[(way*port_bitwidth):((way+1)*port_bitwidth)-1])
);
end
end
endgenerate

assign siv[0:(2*port_bitwidth)-1] = {sov[1:(2*port_bitwidth)-1], func_scan_in[0]};
assign func_scan_out[0] = sov[0];
assign siv[(2*port_bitwidth):(4*port_bitwidth)-1] = {sov[(2*port_bitwidth)+1:(4*port_bitwidth)-1], func_scan_in[1]};
assign func_scan_out[1] = sov[(2*port_bitwidth)];
assign siv[(4*port_bitwidth):(6*port_bitwidth)-1] = {sov[(4*port_bitwidth)+1:(6*port_bitwidth)-1], func_scan_in[3]};
assign func_scan_out[2] = sov[(4*port_bitwidth)];
assign siv[(6*port_bitwidth):scan_right] = {sov[(6*port_bitwidth)+1:scan_right], func_scan_in[3]};
assign func_scan_out[3] = sov[(6*port_bitwidth)];

endmodule

@ -0,0 +1,564 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_32x70_2w_1r1w.v
// *! DESCRIPTION : 32 entry x 70 bit x 2 way array,
// *! 1 read & 1 write port
// *!
// *!****************************************************************

`include "tri_a2o.vh"

module tri_32x70_2w_1r1w(
gnd,
vdd,
vcs,
nclk,
rd_act,
wr_act,
sg_0,
abst_sl_thold_0,
ary_nsl_thold_0,
time_sl_thold_0,
repr_sl_thold_0,
func_sl_force,
func_sl_thold_0_b,
g8t_clkoff_dc_b,
ccflush_dc,
scan_dis_dc_b,
scan_diag_dc,
g8t_d_mode_dc,
g8t_mpw1_dc_b,
g8t_mpw2_dc_b,
g8t_delay_lclkr_dc,
d_mode_dc,
mpw1_dc_b,
mpw2_dc_b,
delay_lclkr_dc,
wr_abst_act,
rd0_abst_act,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
abist_rd0_adr,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp,
abst_scan_in,
time_scan_in,
repr_scan_in,
func_scan_in,
abst_scan_out,
time_scan_out,
repr_scan_out,
func_scan_out,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
wr_way,
wr_addr,
data_in,
rd_addr,
data_out
);
parameter addressable_ports = 32; // number of addressable register in this array
parameter addressbus_width = 5; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
parameter port_bitwidth = 70; // bitwidth of ports
parameter ways = 2; // number of ways

// POWER PINS
inout gnd;
inout vdd;
inout vcs;
// CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk;
input [0:1] rd_act;
input [0:1] wr_act;
input sg_0;
input abst_sl_thold_0;
input ary_nsl_thold_0;
input time_sl_thold_0;
input repr_sl_thold_0;
input func_sl_force;
input func_sl_thold_0_b;
input g8t_clkoff_dc_b;
input ccflush_dc;
input scan_dis_dc_b;
input scan_diag_dc;
input g8t_d_mode_dc;
input [0:4] g8t_mpw1_dc_b;
input g8t_mpw2_dc_b;
input [0:4] g8t_delay_lclkr_dc;
input d_mode_dc;
input mpw1_dc_b;
input mpw2_dc_b;
input delay_lclkr_dc;

// ABIST
input wr_abst_act;
input rd0_abst_act;
input [0:3] abist_di;
input abist_bw_odd;
input abist_bw_even;
input [0:addressbus_width-1] abist_wr_adr;
input [0:addressbus_width-1] abist_rd0_adr;
input tc_lbist_ary_wrt_thru_dc;
input abist_ena_1;
input abist_g8t_rd0_comp_ena;
input abist_raw_dc_b;
input [0:3] obs0_abist_cmp;

// Scan
input [0:1] abst_scan_in;
input time_scan_in;
input repr_scan_in;
input func_scan_in;
output [0:1] abst_scan_out;
output time_scan_out;
output repr_scan_out;
output func_scan_out;

// BOLT-ON
input lcb_bolt_sl_thold_0;
input pc_bo_enable_2; // general bolt-on enable
input pc_bo_reset; // reset
input pc_bo_unload; // unload sticky bits
input pc_bo_repair; // execute sticky bit decode
input pc_bo_shdata; // shift data for timing write and diag loop
input [0:1] pc_bo_select; // select for mask and hier writes
output [0:1] bo_pc_failout; // fail/no-fix reg
output [0:1] bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;

// Write Ports
input [0:ways-1] wr_way;
input [0:addressbus_width-1] wr_addr;
input [0:port_bitwidth-1] data_in;

// Read Ports
input [0:addressbus_width-1] rd_addr;
output [0:port_bitwidth*ways-1] data_out;

// tri_32x70_2w_1r1w

parameter ramb_base_width = 36;
parameter ramb_base_addr = 9;

// Configuration Statement for NCsim
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
parameter rd_act_offset = 0;
parameter data_out0_offset = rd_act_offset + 2;
parameter data_out1_offset = data_out0_offset + port_bitwidth - 1;
parameter scan_right = data_out1_offset + port_bitwidth - 1;

wire [0:port_bitwidth-1] array_wr_data;
wire [0:35] ramb_data_in_l;
wire [0:35] ramb_data_in_r;
wire [0:35] ramb_data_p0_outA;
wire [0:35] ramb_data_p0_outB;
wire [0:35] ramb_data_p0_outC;
wire [0:35] ramb_data_p0_outD;
wire [0:35] ramb_data_p1_outA;
wire [0:35] ramb_data_p1_outB;
wire [0:35] ramb_data_p1_outC;
wire [0:35] ramb_data_p1_outD;
wire [0:ramb_base_addr-1] ramb_addr_rd1;
wire [0:ramb_base_addr-1] ramb_addr_wr_rd0;

wire [0:ramb_base_addr-1] rd_addr0;
wire [0:ramb_base_addr-1] wr_addr1;
wire write_enable_AB;
wire write_enable_CD;
wire tiup;
wire [0:35] tidn;
wire [0:1] act;
wire ary_nsl_thold_0_b;
wire [0:addressable_ports-1] arrA_bit0_scanout;
wire [0:addressable_ports-1] arrC_bit0_scanout;
wire [0:addressable_ports-1] arrA_bit0_d;
wire [0:addressable_ports-1] arrA_bit0_q;
wire [0:addressable_ports-1] arrC_bit0_d;
wire [0:addressable_ports-1] arrC_bit0_q;
wire [0:addressable_ports-1] arrA_bit0_wen;
wire [0:addressable_ports-1] arrC_bit0_wen;
reg arrA_bit0_out_d;
reg arrC_bit0_out_d;
wire arrA_bit0_out_q;
wire arrC_bit0_out_q;
wire arrA_bit0_out_scanout;
wire arrC_bit0_out_scanout;
wire [0:port_bitwidth*ways-1] data_out_d;
wire [0:port_bitwidth*ways-1] data_out_q;
wire [0:1] rd_act_d;
wire [0:1] rd_act_q;
wire [0:scan_right] siv;
wire [0:scan_right] sov;

(* analysis_not_referenced="true" *)
wire unused;

assign unused = | {ramb_data_p1_outA[0], ramb_data_p1_outA[35], ramb_data_p1_outB[35], ramb_data_p1_outC[0], ramb_data_p1_outC[35], ramb_data_p1_outD[35],
ramb_data_p0_outA, ramb_data_p0_outB, ramb_data_p0_outC, ramb_data_p0_outD, gnd, vdd, vcs,
sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, g8t_clkoff_dc_b, ccflush_dc, scan_dis_dc_b,
scan_diag_dc, g8t_d_mode_dc, g8t_mpw1_dc_b, g8t_mpw2_dc_b, g8t_delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd,
abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b,
obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload,
pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc, arrA_bit0_scanout, arrC_bit0_scanout, arrA_bit0_out_scanout, arrC_bit0_out_scanout};

assign tiup = 1'b1;
assign tidn = 36'b0;
assign act = rd_act | wr_act;
assign rd_act_d = rd_act;

// Data Generate
assign array_wr_data = data_in;

assign ramb_data_in_l = {array_wr_data[0:34], 1'b0};
assign ramb_data_in_r = {array_wr_data[35:69], 1'b0};

assign write_enable_AB = wr_act[0] & wr_way[0];
assign write_enable_CD = wr_act[1] & wr_way[1];

// Read/Write Port Address Generate
generate
begin
genvar t;
for (t = 0; t < ramb_base_addr; t = t + 1)
begin : rambAddrCalc
if (t < ramb_base_addr - addressbus_width)
begin
assign rd_addr0[t] = 1'b0;
assign wr_addr1[t] = 1'b0;
end
if (t >= ramb_base_addr - addressbus_width)
begin
assign rd_addr0[t] = rd_addr[t - (ramb_base_addr - addressbus_width)];
assign wr_addr1[t] = wr_addr[t - (ramb_base_addr - addressbus_width)];
end
end
end
endgenerate

// Writing on PortA
// Reading on PortB
assign ramb_addr_rd1 = rd_addr0;
assign ramb_addr_wr_rd0 = wr_addr1;

assign data_out_d = {arrA_bit0_out_q, ramb_data_p1_outA[1:34], ramb_data_p1_outB[0:34], arrC_bit0_out_q, ramb_data_p1_outC[1:34], ramb_data_p1_outD[0:34]};
assign data_out = data_out_q;

generate
begin : arr_bit0
genvar i;
for (i = 0; i <= addressable_ports - 1; i = i + 1)
begin : arr_bit0
wire [0:addressbus_width-1] iDummy=i;
assign arrA_bit0_wen[i] = write_enable_AB & (wr_addr == iDummy);
assign arrC_bit0_wen[i] = write_enable_CD & (wr_addr == iDummy);
assign arrA_bit0_d[i] = (arrA_bit0_wen[i] == 1'b1) ? array_wr_data[0] :
arrA_bit0_q[i];
assign arrC_bit0_d[i] = (arrC_bit0_wen[i] == 1'b1) ? array_wr_data[0] :
arrC_bit0_q[i];
end
end
endgenerate

always @(*)
begin: bit0_read_proc
reg rd_arrA_bit0;
reg rd_arrC_bit0;
//(* analysis_not_referenced="true" *)
reg [0:31] i;
rd_arrA_bit0 = 1'b0;
rd_arrC_bit0 = 1'b0;
for (i = 0; i <= addressable_ports - 1; i = i + 1)
begin
rd_arrA_bit0 = ((rd_addr == i[32-addressbus_width:31]) & arrA_bit0_q[i]) | rd_arrA_bit0;
rd_arrC_bit0 = ((rd_addr == i[32-addressbus_width:31]) & arrC_bit0_q[i]) | rd_arrC_bit0;
end
arrA_bit0_out_d = rd_arrA_bit0;
arrC_bit0_out_d = rd_arrC_bit0;
end


assign ary_nsl_thold_0_b = ~ ary_nsl_thold_0;

tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(write_enable_AB),
.force_t(tidn[0]),
.d_mode(tidn[0]),
.delay_lclkr(tidn[0]),
.mpw1_b(tidn[0]),
.mpw2_b(tidn[0]),
.thold_b(ary_nsl_thold_0_b),
.sg(tidn[0]),
.scin({addressable_ports{tidn[0]}}),
.scout(arrA_bit0_scanout),
.din(arrA_bit0_d),
.dout(arrA_bit0_q)
);

tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(write_enable_CD),
.force_t(tidn[0]),
.d_mode(tidn[0]),
.delay_lclkr(tidn[0]),
.mpw1_b(tidn[0]),
.mpw2_b(tidn[0]),
.thold_b(ary_nsl_thold_0_b),
.sg(tidn[0]),
.scin({addressable_ports{tidn[0]}}),
.scout(arrC_bit0_scanout),
.din(arrC_bit0_d),
.dout(arrC_bit0_q)
);

tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_out_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(tidn[0]),
.d_mode(tidn[0]),
.delay_lclkr(tidn[0]),
.mpw1_b(tidn[0]),
.mpw2_b(tidn[0]),
.thold_b(ary_nsl_thold_0_b),
.sg(tidn[0]),
.scin(tidn[0]),
.scout(arrA_bit0_out_scanout),
.din(arrA_bit0_out_d),
.dout(arrA_bit0_out_q)
);

tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_out_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(tidn[0]),
.d_mode(tidn[0]),
.delay_lclkr(tidn[0]),
.mpw1_b(tidn[0]),
.mpw2_b(tidn[0]),
.thold_b(ary_nsl_thold_0_b),
.sg(tidn[0]),
.scin(tidn[0]),
.scout(arrC_bit0_out_scanout),
.din(arrC_bit0_out_d),
.dout(arrC_bit0_out_q)
);


RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
arr0_A(
.DOA(ramb_data_p0_outA[0:31]),
.DOB(ramb_data_p1_outA[0:31]),
.DOPA(ramb_data_p0_outA[32:35]),
.DOPB(ramb_data_p1_outA[32:35]),
.ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(ramb_data_in_l[0:31]),
.DIB(tidn[0:31]),
.DIPA(ramb_data_in_l[32:35]),
.DIPB(tidn[32:35]),
.ENA(act[0]),
.ENB(act[0]),
.SSRA(nclk[1]), //sreset
.SSRB(nclk[1]), //sreset
.WEA(write_enable_AB),
.WEB(tidn[0])
);

RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
arr1_B(
.DOA(ramb_data_p0_outB[0:31]),
.DOB(ramb_data_p1_outB[0:31]),
.DOPA(ramb_data_p0_outB[32:35]),
.DOPB(ramb_data_p1_outB[32:35]),
.ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(ramb_data_in_r[0:31]),
.DIB(tidn[0:31]),
.DIPA(ramb_data_in_r[32:35]),
.DIPB(tidn[32:35]),
.ENA(act[0]),
.ENB(act[0]),
.SSRA(nclk[1]),
.SSRB(nclk[1]),
.WEA(write_enable_AB),
.WEB(tidn[0])
);

RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
arr2_C(
.DOA(ramb_data_p0_outC[0:31]),
.DOB(ramb_data_p1_outC[0:31]),
.DOPA(ramb_data_p0_outC[32:35]),
.DOPB(ramb_data_p1_outC[32:35]),
.ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(ramb_data_in_l[0:31]),
.DIB(tidn[0:31]),
.DIPA(ramb_data_in_l[32:35]),
.DIPB(tidn[32:35]),
.ENA(act[1]),
.ENB(act[1]),
.SSRA(nclk[1]),
.SSRB(nclk[1]),
.WEA(write_enable_CD),
.WEB(tidn[0])
);

RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
arr3_D(
.DOA(ramb_data_p0_outD[0:31]),
.DOB(ramb_data_p1_outD[0:31]),
.DOPA(ramb_data_p0_outD[32:35]),
.DOPB(ramb_data_p1_outD[32:35]),
.ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(ramb_data_in_r[0:31]),
.DIB(tidn[0:31]),
.DIPA(ramb_data_in_r[32:35]),
.DIPB(tidn[32:35]),
.ENA(act[1]),
.ENB(act[1]),
.SSRA(nclk[1]),
.SSRB(nclk[1]),
.WEA(write_enable_CD),
.WEB(tidn[0])
);

// ####################################################
// Registers
// ####################################################

tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[rd_act_offset:rd_act_offset + 2 - 1]),
.scout(sov[rd_act_offset:rd_act_offset + 2 - 1]),
.din(rd_act_d),
.dout(rd_act_q)
);

tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rd_act_q[0]),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[data_out0_offset:data_out0_offset + port_bitwidth - 1]),
.scout(sov[data_out0_offset:data_out0_offset + port_bitwidth - 1]),
.din(data_out_d[0:port_bitwidth - 1]),
.dout(data_out_q[0:port_bitwidth - 1])
);

tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rd_act_q[1]),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[data_out1_offset:data_out1_offset + port_bitwidth - 1]),
.scout(sov[data_out1_offset:data_out1_offset + port_bitwidth - 1]),
.din(data_out_d[port_bitwidth:2 * port_bitwidth - 1]),
.dout(data_out_q[port_bitwidth:2 * port_bitwidth - 1])
);

assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in};
assign func_scan_out = sov[0];

assign abst_scan_out = tidn[0:1];
assign time_scan_out = tidn[0];
assign repr_scan_out = tidn[0];
assign bo_pc_failout = tidn[0:1];
assign bo_pc_diagloop = tidn[0:1];
endmodule

@ -0,0 +1,338 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_512x162_4w_0.v
// *! DESCRIPTION : 512 Entry x 162 bit x 4 way array
// *!
// *!****************************************************************

`include "tri_a2o.vh"

module tri_512x162_4w_0(
gnd,
vdd,
vcs,
nclk,
ccflush_dc,
lcb_clkoff_dc_b,
lcb_d_mode_dc,
lcb_act_dis_dc,
lcb_ary_nsl_thold_0,
lcb_sg_1,
lcb_abst_sl_thold_0,
lcb_func_sl_thold_0_b,
func_force,
scan_diag_dc,
scan_dis_dc_b,
func_scan_in,
func_scan_out,
abst_scan_in,
abst_scan_out,
lcb_delay_lclkr_np_dc,
ctrl_lcb_delay_lclkr_np_dc,
dibw_lcb_delay_lclkr_np_dc,
ctrl_lcb_mpw1_np_dc_b,
dibw_lcb_mpw1_np_dc_b,
lcb_mpw1_pp_dc_b,
lcb_mpw1_2_pp_dc_b,
aodo_lcb_delay_lclkr_dc,
aodo_lcb_mpw1_dc_b,
aodo_lcb_mpw2_dc_b,
lcb_time_sg_0,
lcb_time_sl_thold_0,
time_scan_in,
time_scan_out,
bitw_abist,
lcb_repr_sl_thold_0,
lcb_repr_sg_0,
repr_scan_in,
repr_scan_out,
tc_lbist_ary_wrt_thru_dc,
abist_en_1,
din_abist,
abist_cmp_en,
abist_raw_b_dc,
data_cmp_abist,
addr_abist,
r_wb_abist,
write_thru_en_dc,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
read_act,
write_act,
write_enable,
write_way,
addr,
data_in,
data_out
);
parameter addressable_ports = 512; // number of addressable register in this array
parameter addressbus_width = 9; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
parameter port_bitwidth = 162; // bitwidth of ports
parameter ways = 4; // number of ways
// POWER PINS
inout gnd;
inout vdd;
(* analysis_not_referenced="true" *)
inout vcs;
// CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk;
input ccflush_dc;
input lcb_clkoff_dc_b;
input lcb_d_mode_dc;
input lcb_act_dis_dc;
input lcb_ary_nsl_thold_0;
input lcb_sg_1;
input lcb_abst_sl_thold_0;
input lcb_func_sl_thold_0_b;
input func_force;
input scan_diag_dc;
input scan_dis_dc_b;
input func_scan_in;
output func_scan_out;
input [0:1] abst_scan_in;
output [0:1] abst_scan_out;
input lcb_delay_lclkr_np_dc;
input ctrl_lcb_delay_lclkr_np_dc;
input dibw_lcb_delay_lclkr_np_dc;
input ctrl_lcb_mpw1_np_dc_b;
input dibw_lcb_mpw1_np_dc_b;
input lcb_mpw1_pp_dc_b;
input lcb_mpw1_2_pp_dc_b;
input aodo_lcb_delay_lclkr_dc;
input aodo_lcb_mpw1_dc_b;
input aodo_lcb_mpw2_dc_b;
// Timing Scan Chain Pins
input lcb_time_sg_0;
input lcb_time_sl_thold_0;
input time_scan_in;
output time_scan_out;
input [0:1] bitw_abist;
// REDUNDANCY PINS
input lcb_repr_sl_thold_0;
input lcb_repr_sg_0;
input repr_scan_in;
output repr_scan_out;
// DATA I/O RELATED PINS:
input tc_lbist_ary_wrt_thru_dc;
input abist_en_1;
input [0:3] din_abist;
input abist_cmp_en;
input abist_raw_b_dc;
input [0:3] data_cmp_abist;
input [0:addressbus_width-1] addr_abist;
input r_wb_abist;
input write_thru_en_dc;
// BOLT-ON
input lcb_bolt_sl_thold_0; // thold for any regs inside backend
input pc_bo_enable_2; // general bolt-on enable, probably DC
input pc_bo_reset; // execute sticky bit decode
input pc_bo_unload;
input pc_bo_repair; // load repair reg
input pc_bo_shdata; // shift data for timing write
input [0:1] pc_bo_select; // select for mask and hier writes
output [0:1] bo_pc_failout; // fail/no-fix reg
output [0:1] bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;
// FUNCTIONAL PORTS
input [0:1] read_act;
input [0:3] write_act;
input write_enable;
input [0:ways-1] write_way;
input [0:addressbus_width-1] addr;
input [0:port_bitwidth-1] data_in;
output [0:port_bitwidth*ways-1] data_out;

// tri_512x162_4w_0

parameter ramb_base_width = 36;
parameter ramb_base_addr = 9;
parameter ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1; // # of RAMB's per way

// Configuration Statement for NCsim
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;

wire [0:ramb_base_width*ramb_width_mult-1] ramb_data_in;
wire [0:ramb_base_width*ramb_width_mult-1] ramb_data_out[0:ways-1];
wire [0:ramb_base_addr-1] ramb_addr;

wire rd_act_d;
wire rd_act_l2;
wire [0:port_bitwidth*ways-1] data_out_d;
wire [0:port_bitwidth*ways-1] data_out_l2;

wire lcb_sg_0;

wire [0:ways-1] act;
wire [0:ways-1] write;
wire tidn;
(* analysis_not_referenced="true" *)
wire unused;
wire [31:0] dob;
wire [3:0] dopb;
wire [0:port_bitwidth*ways-1] unused_scout;

generate
begin
assign tidn = 1'b0;

if (addressbus_width < ramb_base_addr)
begin
assign ramb_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}};
assign ramb_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = addr;
end
if (addressbus_width >= ramb_base_addr)
begin
assign ramb_addr = addr[addressbus_width - ramb_base_addr:addressbus_width - 1];
end

genvar i;
for (i = 0; i < ramb_base_width*ramb_width_mult; i = i + 1)
begin : din
if (i < port_bitwidth)
assign ramb_data_in[i] = data_in[i];
if (i >= port_bitwidth)
assign ramb_data_in[i] = 1'b0;
end

genvar w;
for (w = 0; w < ways; w = w + 1)
begin : aw
assign act[w] = (|(read_act)) | write_way[w];
assign write[w] = write_enable & write_way[w];

genvar x;
for (x = 0; x < ramb_width_mult; x = x + 1)
begin : ax
RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
arr(
.DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]),
.DOB(dob),
.DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
.DOPB(dopb),
.ADDRA(ramb_addr),
.ADDRB(ramb_addr),
.CLKA(nclk[0]),
.CLKB(tidn),
.DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
.DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
.DIPA(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
.DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
.ENA(act[w]),
.ENB(tidn),
.SSRA(nclk[1]),
.SSRB(tidn),
.WEA(write[w]),
.WEB(tidn)
);
end //ax

assign data_out_d[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1];

end //aw

assign data_out = data_out_l2;

assign rd_act_d = |(read_act); // Use for data_out latch act

tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(1'b1),
.thold_b(lcb_func_sl_thold_0_b),
.sg(lcb_sg_0),
.force_t(func_force),
.delay_lclkr(tri_lcb_delay_lclkr_dc),
.mpw1_b(tri_lcb_mpw1_dc_b),
.mpw2_b(tri_lcb_mpw2_dc_b),
.d_mode(lcb_d_mode_dc),
.scin(1'b0),
.scout(func_scan_out),
.din(rd_act_d),
.dout(rd_act_l2)
);

tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rd_act_l2),
.thold_b(lcb_func_sl_thold_0_b),
.sg(lcb_sg_0),
.force_t(func_force),
.delay_lclkr(tri_lcb_delay_lclkr_dc),
.mpw1_b(tri_lcb_mpw1_dc_b),
.mpw2_b(tri_lcb_mpw2_dc_b),
.d_mode(lcb_d_mode_dc),
.scin({port_bitwidth*ways{1'b0}}),
.scout(unused_scout),
.din(data_out_d),
.dout(data_out_l2)
);

tri_plat #(.WIDTH(1)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_dc),
.din(lcb_sg_1),
.q(lcb_sg_0)
);

assign abst_scan_out = 2'b00;
assign time_scan_out = 1'b0;
assign repr_scan_out = 1'b0;

assign bo_pc_failout = 2'b00;
assign bo_pc_diagloop = 2'b00;

assign unused = | ({nclk[2:`NCLK_WIDTH-1], ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[1][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[2][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[3][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, lcb_clkoff_dc_b, lcb_d_mode_dc, lcb_act_dis_dc, scan_dis_dc_b, scan_diag_dc, bitw_abist, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, write_thru_en_dc, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_delay_lclkr_np_dc, ctrl_lcb_delay_lclkr_np_dc, dibw_lcb_delay_lclkr_np_dc, ctrl_lcb_mpw1_np_dc_b, dibw_lcb_mpw1_np_dc_b, lcb_mpw1_pp_dc_b, lcb_mpw1_2_pp_dc_b, aodo_lcb_delay_lclkr_dc, aodo_lcb_mpw1_dc_b, aodo_lcb_mpw2_dc_b, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, write_act, dob, dopb, unused_scout});
end
endgenerate
endmodule

@ -0,0 +1,333 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

//*****************************************************************************
// Description: Tri Array Wrapper
//
//*****************************************************************************

`include "tri_a2o.vh"

module tri_512x16_1r1w_1(
vdd,
vcs,
gnd,
nclk,
rd_act,
wr_act,
lcb_d_mode_dc,
lcb_clkoff_dc_b,
lcb_mpw1_dc_b,
lcb_mpw2_dc_b,
lcb_delay_lclkr_dc,
ccflush_dc,
scan_dis_dc_b,
scan_diag_dc,
func_scan_in,
func_scan_out,
lcb_sg_0,
lcb_sl_thold_0_b,
lcb_time_sl_thold_0,
lcb_abst_sl_thold_0,
lcb_ary_nsl_thold_0,
lcb_repr_sl_thold_0,
time_scan_in,
time_scan_out,
abst_scan_in,
abst_scan_out,
repr_scan_in,
repr_scan_out,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
wr_abst_act,
abist_rd0_adr,
rd0_abst_act,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
bw,
wr_adr,
rd_adr,
di,
dout
);
parameter addressable_ports = 128; // number of addressable register in this array
parameter addressbus_width = 9; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
parameter port_bitwidth = 16; // bitwidth of ports
parameter ways = 1; // number of ways

// POWER PINS
inout vdd;
inout vcs;
inout gnd;

input [0:`NCLK_WIDTH-1] nclk;

input rd_act;
input wr_act;

// DC TEST PINS
input lcb_d_mode_dc;
input lcb_clkoff_dc_b;
input [0:4] lcb_mpw1_dc_b;
input lcb_mpw2_dc_b;
input [0:4] lcb_delay_lclkr_dc;

input ccflush_dc;
input scan_dis_dc_b;
input scan_diag_dc;
input func_scan_in;
output func_scan_out;

input lcb_sg_0;
input lcb_sl_thold_0_b;
input lcb_time_sl_thold_0;
input lcb_abst_sl_thold_0;
input lcb_ary_nsl_thold_0;
input lcb_repr_sl_thold_0;
input time_scan_in;
output time_scan_out;
input abst_scan_in;
output abst_scan_out;
input repr_scan_in;
output repr_scan_out;

input [0:3] abist_di;
input abist_bw_odd;
input abist_bw_even;
input [0:6] abist_wr_adr;
input wr_abst_act;
input [0:6] abist_rd0_adr;
input rd0_abst_act;
input tc_lbist_ary_wrt_thru_dc;
input abist_ena_1;
input abist_g8t_rd0_comp_ena;
input abist_raw_dc_b;
input [0:3] obs0_abist_cmp;

// BOLT-ON
input lcb_bolt_sl_thold_0;
input pc_bo_enable_2; // general bolt-on enable
input pc_bo_reset; // reset
input pc_bo_unload; // unload sticky bits
input pc_bo_repair; // execute sticky bit decode
input pc_bo_shdata; // shift data for timing write and diag loop
input pc_bo_select; // select for mask and hier writes
output bo_pc_failout; // fail/no-fix reg
output bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;

input [0:15] bw;
input [0:8] wr_adr;
input [0:8] rd_adr;
input [0:15] di;

output [0:15] dout;

// Configuration Statement for NCsim
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;

wire clk;
wire clk2x;
wire [0:8] b0addra;
wire [0:8] b0addrb;
wire wea;
wire web;
wire wren_a;
// Latches
reg reset_q;
reg gate_fq;
wire gate_d;
wire [0:35] r_data_out_1_d;
reg [0:35] r_data_out_1_fq;
wire [0:35] w_data_in_0;

wire [0:35] r_data_out_0_bram;
wire [0:35] r_data_out_1_bram;

wire toggle_d;
reg toggle_q;
wire toggle2x_d;
reg toggle2x_q;

(* analysis_not_referenced="true" *)
wire unused;

assign clk = nclk[0];
assign clk2x = nclk[2];

always @(posedge clk)
begin: rlatch
reset_q <= nclk[1];
end

//
// NEW clk2x gate logic start
//

always @(posedge clk)
begin: tlatch
if (reset_q == 1'b1)
toggle_q <= 1'b1;
else
toggle_q <= toggle_d;
end

always @(posedge clk2x)
begin: flatch
toggle2x_q <= toggle2x_d;
gate_fq <= gate_d;
r_data_out_1_fq <= r_data_out_1_d;
end

assign toggle_d = (~toggle_q);
assign toggle2x_d = toggle_q;

// should force gate_fq to be on during odd 2x clock (second half of 1x clock).
//gate_d <= toggle_q xor toggle2x_q;
// if you want the first half do the following
assign gate_d = (~(toggle_q ^ toggle2x_q));

//
// NEW clk2x gate logic end
//

assign b0addra[0:8] = wr_adr;
assign b0addrb[0:8] = rd_adr;

// Unused Address Bits
//b0addra(0 to 1) <= "00";
//b0addrb(0 to 1) <= "00";

// port a is a read-modify-write port
assign wren_a = ((bw != 16'b0000000000000000) & (wr_act == 1'b1)) ? 1'b1 :
1'b0;
assign wea = wren_a & (~(gate_fq)); // write in 2nd half of nclk
assign web = 1'b0;
assign w_data_in_0[0] = (bw[0] == 1'b1) ? di[0] :
r_data_out_0_bram[0];
assign w_data_in_0[1] = (bw[1] == 1'b1) ? di[1] :
r_data_out_0_bram[1];
assign w_data_in_0[2] = (bw[2] == 1'b1) ? di[2] :
r_data_out_0_bram[2];
assign w_data_in_0[3] = (bw[3] == 1'b1) ? di[3] :
r_data_out_0_bram[3];
assign w_data_in_0[4] = (bw[4] == 1'b1) ? di[4] :
r_data_out_0_bram[4];
assign w_data_in_0[5] = (bw[5] == 1'b1) ? di[5] :
r_data_out_0_bram[5];
assign w_data_in_0[6] = (bw[6] == 1'b1) ? di[6] :
r_data_out_0_bram[6];
assign w_data_in_0[7] = (bw[7] == 1'b1) ? di[7] :
r_data_out_0_bram[7];
assign w_data_in_0[8] = (bw[8] == 1'b1) ? di[8] :
r_data_out_0_bram[8];
assign w_data_in_0[9] = (bw[9] == 1'b1) ? di[9] :
r_data_out_0_bram[9];
assign w_data_in_0[10] = (bw[10] == 1'b1) ? di[10] :
r_data_out_0_bram[10];
assign w_data_in_0[11] = (bw[11] == 1'b1) ? di[11] :
r_data_out_0_bram[11];
assign w_data_in_0[12] = (bw[12] == 1'b1) ? di[12] :
r_data_out_0_bram[12];
assign w_data_in_0[13] = (bw[13] == 1'b1) ? di[13] :
r_data_out_0_bram[13];
assign w_data_in_0[14] = (bw[14] == 1'b1) ? di[14] :
r_data_out_0_bram[14];
assign w_data_in_0[15] = (bw[15] == 1'b1) ? di[15] :
r_data_out_0_bram[15];
assign w_data_in_0[16:35] = 20'b0;

assign r_data_out_1_d = r_data_out_1_bram;

RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
bram0a(
.CLKA(clk2x),
.CLKB(clk2x),
.SSRA(reset_q),
.SSRB(reset_q),
.ADDRA(b0addra),
.ADDRB(b0addrb),
.DIA(w_data_in_0[0:31]),
.DIB(32'b0),
.DOA(r_data_out_0_bram[0:31]),
.DOB(r_data_out_1_bram[0:31]),
.DOPA(r_data_out_0_bram[32:35]),
.DOPB(r_data_out_1_bram[32:35]),
.DIPA(w_data_in_0[32:35]),
.DIPB(4'h0),
.ENA(1'b1),
.ENB(1'b1),
.WEA(wea),
.WEB(web)
);

assign dout = r_data_out_1_fq[0:15];

assign func_scan_out = func_scan_in;
assign time_scan_out = time_scan_in;
assign abst_scan_out = abst_scan_in;
assign repr_scan_out = repr_scan_in;

assign bo_pc_failout = 1'b0;
assign bo_pc_diagloop = 1'b0;

assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc, rd_act, r_data_out_0_bram[16:35], r_data_out_1_fq[16:35]};
endmodule

@ -0,0 +1,426 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_64x144_1r1w.v
// *! DESCRIPTION : 64 Entry x 144 bit array, 9 bit writeable
// *!
// *!****************************************************************

`include "tri_a2o.vh"

module tri_64x144_1r1w(
gnd,
vdd,
vcs,
nclk,
rd_act,
wr_act,
sg_0,
abst_sl_thold_0,
ary_nsl_thold_0,
time_sl_thold_0,
repr_sl_thold_0,
func_sl_force,
func_sl_thold_0_b,
g8t_clkoff_dc_b,
ccflush_dc,
scan_dis_dc_b,
scan_diag_dc,
g8t_d_mode_dc,
g8t_mpw1_dc_b,
g8t_mpw2_dc_b,
g8t_delay_lclkr_dc,
d_mode_dc,
mpw1_dc_b,
mpw2_dc_b,
delay_lclkr_dc,
wr_abst_act,
rd0_abst_act,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
abist_rd0_adr,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp,
abst_scan_in,
time_scan_in,
repr_scan_in,
func_scan_in,
abst_scan_out,
time_scan_out,
repr_scan_out,
func_scan_out,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
write_enable,
addr_wr,
data_in,
addr_rd,
data_out
);
parameter addressable_ports = 64; // number of addressable register in this array
parameter addressbus_width = 6; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
parameter port_bitwidth = 144; // bitwidth of ports (per way)
parameter bit_write_type = 9; // gives the number of bits that shares one write-enable; must divide evenly into array
parameter ways = 1; // number of ways

// POWER PINS
inout gnd;
inout vdd;
inout vcs;

// CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk;
input rd_act;
input wr_act;
input sg_0;
input abst_sl_thold_0;
input ary_nsl_thold_0;
input time_sl_thold_0;
input repr_sl_thold_0;
input func_sl_force;
input func_sl_thold_0_b;
input g8t_clkoff_dc_b;
input ccflush_dc;
input scan_dis_dc_b;
input scan_diag_dc;
input g8t_d_mode_dc;
input [0:4] g8t_mpw1_dc_b;
input g8t_mpw2_dc_b;
input [0:4] g8t_delay_lclkr_dc;
input d_mode_dc;
input mpw1_dc_b;
input mpw2_dc_b;
input delay_lclkr_dc;

// ABIST
input wr_abst_act;
input rd0_abst_act;
input [0:3] abist_di;
input abist_bw_odd;
input abist_bw_even;
input [0:addressbus_width-1] abist_wr_adr;
input [0:addressbus_width-1] abist_rd0_adr;
input tc_lbist_ary_wrt_thru_dc;
input abist_ena_1;
input abist_g8t_rd0_comp_ena;
input abist_raw_dc_b;
input [0:3] obs0_abist_cmp;

// Scan
input abst_scan_in;
input time_scan_in;
input repr_scan_in;
input func_scan_in;
output abst_scan_out;
output time_scan_out;
output repr_scan_out;
output func_scan_out;

// BOLT-ON
input lcb_bolt_sl_thold_0;
input pc_bo_enable_2; // general bolt-on enable
input pc_bo_reset; // reset
input pc_bo_unload; // unload sticky bits
input pc_bo_repair; // execute sticky bit decode
input pc_bo_shdata; // shift data for timing write and diag loop
input [0:1] pc_bo_select; // select for mask and hier writes
output [0:1] bo_pc_failout; // fail/no-fix reg
output [0:1] bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;

// Write Ports
input write_enable;
input [0:addressbus_width-1] addr_wr;
input [0:port_bitwidth-1] data_in;

// Read Ports
input [0:addressbus_width-1] addr_rd;
output [0:port_bitwidth-1] data_out;

// tri_64x144_1r1w

// Configuration Statement for NCsim
//for all:RAMB36 use entity unisim.RAMB36;

parameter data_width = ((((port_bitwidth - 1)/36) + 1) * 36) - 1;
parameter rd_act_offset = 0;
parameter data_out_offset = rd_act_offset + 1;
parameter scan_right = data_out_offset + port_bitwidth - 1;

wire [0:data_width-(data_width/9)-1] ramb_data_in;
wire [0:data_width/9] ramb_par_in;
wire [0:data_width-(data_width/9)-1] ramb_data_out;
wire [0:data_width/9] ramb_par_out;
wire [0:data_width-(data_width/9)-1] ramb_data_dummy;
wire [0:data_width/9] ramb_par_dummy;
wire [0:15] ramb_wr_addr;
wire [0:15] ramb_rd_addr;
wire [0:data_width] data_in_pad;
wire [0:data_width] data_out_pad;
wire [0:((port_bitwidth-1)/36)] cascadeoutlata;
wire [0:((port_bitwidth-1)/36)] cascadeoutlatb;
wire [0:((port_bitwidth-1)/36)] cascadeoutrega;
wire [0:((port_bitwidth-1)/36)] cascadeoutregb;
wire rd_act_d;
wire rd_act_q;
wire [0:port_bitwidth-1] data_out_d;
wire [0:port_bitwidth-1] data_out_q;

wire tiup;
wire tidn;
wire [0:(((((port_bitwidth-1)/36)+1)*36)/9)-1] wrt_en;
wire act;
wire [0:scan_right] siv;
wire [0:scan_right] sov;

(* analysis_not_referenced="true" *)
wire unused;

generate begin
assign tiup = 1'b1;
assign tidn = 1'b0;
assign wrt_en = {(((((port_bitwidth-1)/36)+1)*36)/9){write_enable}};
assign act = rd_act | wr_act;
assign rd_act_d = rd_act;

assign ramb_wr_addr[0] = 1'b0;
assign ramb_wr_addr[11:15] = 5'b0;
assign ramb_rd_addr[0] = 1'b0;
assign ramb_rd_addr[11:15] = 5'b0;

genvar addr;
for (addr = 0; addr < 10; addr = addr + 1) begin : padA0
if (addr < 10 - addressbus_width)
begin
assign ramb_wr_addr[addr + 1] = 1'b0;
assign ramb_rd_addr[addr + 1] = 1'b0;
end
if (addr >= 10 - addressbus_width)
begin
assign ramb_wr_addr[addr + 1] = addr_wr[addr - (10 - addressbus_width)];
assign ramb_rd_addr[addr + 1] = addr_rd[addr - (10 - addressbus_width)];
end
end

// PORTA => Used for Writing
// PORTB => Used for Reading
genvar arr;
for (arr = 0; arr <= (port_bitwidth - 1)/36; arr = arr + 1)
begin : padD0
genvar b;
for (b = 0; b < 36; b = b + 1)
begin : numBit
if ((arr * 36) + b < port_bitwidth)
begin
assign data_in_pad[(arr * 36) + b] = data_in[(arr * 36) + b];
end
if ((arr * 36) + b >= port_bitwidth)
begin
assign data_in_pad[(arr * 36) + b] = 1'b0;
end
end
end

genvar bb;
for (bb = 0; bb <= (data_width)/9; bb = bb + 1)
begin : dInFixUp
assign ramb_data_in[bb * 8:(bb * 8) + 7] = data_in_pad[(bb * 8) + bb:(bb * 8) + 7 + bb];
assign ramb_par_in[bb] = data_in_pad[(bb * 8) + bb + 8];
end

for (bb = 0; bb <= (data_width)/9; bb = bb + 1)
begin : dOutFixUp
assign data_out_pad[(bb * 8) + bb:(bb * 8) + 7 + bb] = ramb_data_out[bb * 8:(bb * 8) + 7];
assign data_out_pad[(bb * 8) + bb + 8] = ramb_par_out[bb];
end

genvar anum;
for (anum = 0; anum <= (port_bitwidth - 1)/36; anum = anum + 1)
begin : arrNum

RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) ARR(
.CASCADEOUTLATA(cascadeoutlata[anum]),
.CASCADEOUTLATB(cascadeoutlatb[anum]),
.CASCADEOUTREGA(cascadeoutrega[anum]),
.CASCADEOUTREGB(cascadeoutregb[anum]),
.DOA(ramb_data_dummy[(32 * anum):31 + (32 * anum)]),
.DOB(ramb_data_out[(32 * anum):31 + (32 * anum)]),
.DOPA(ramb_par_dummy[(4 * anum):3 + (4 * anum)]),
.DOPB(ramb_par_out[(4 * anum):3 + (4 * anum)]),
.ADDRA(ramb_wr_addr),
.ADDRB(ramb_rd_addr),
.CASCADEINLATA(1'b0),
.CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(ramb_data_in[(32 * anum):31 + (32 * anum)]),
.DIB(32'b0),
.DIPA(ramb_par_in[(4 * anum):3 + (4 * anum)]),
.DIPB(4'b0),
.ENA(act),
.ENB(act),
.REGCEA(1'b0),
.REGCEB(1'b0),
.SSRA(nclk[1]), //sreset
.SSRB(nclk[1]),
.WEA(wrt_en[anum * 4:anum * 4 + 3]),
.WEB(4'b0) //'
);
end
assign data_out_d = data_out_pad[0:port_bitwidth - 1];
assign data_out = data_out_q;

assign abst_scan_out = tidn;
assign time_scan_out = tidn;
assign repr_scan_out = tidn;
assign bo_pc_failout = 2'b00;
assign bo_pc_diagloop = 2'b00;
end
endgenerate

assign unused = | {
cascadeoutlata ,
cascadeoutlatb ,
cascadeoutrega ,
cascadeoutregb ,
ramb_data_dummy ,
ramb_par_dummy ,
nclk[2:`NCLK_WIDTH-1] ,
gnd ,
vdd ,
vcs ,
sg_0 ,
abst_sl_thold_0 ,
ary_nsl_thold_0 ,
time_sl_thold_0 ,
repr_sl_thold_0 ,
g8t_clkoff_dc_b ,
ccflush_dc ,
scan_dis_dc_b ,
scan_diag_dc ,
g8t_d_mode_dc ,
g8t_mpw1_dc_b ,
g8t_mpw2_dc_b ,
g8t_delay_lclkr_dc ,
wr_abst_act ,
rd0_abst_act ,
abist_di ,
abist_bw_odd ,
abist_bw_even ,
abist_wr_adr ,
abist_rd0_adr ,
tc_lbist_ary_wrt_thru_dc ,
abist_ena_1 ,
abist_g8t_rd0_comp_ena ,
abist_raw_dc_b ,
obs0_abist_cmp ,
abst_scan_in ,
time_scan_in ,
repr_scan_in ,
lcb_bolt_sl_thold_0 ,
pc_bo_enable_2 ,
pc_bo_reset ,
pc_bo_unload ,
pc_bo_repair ,
pc_bo_shdata ,
pc_bo_select ,
tri_lcb_mpw1_dc_b ,
tri_lcb_mpw2_dc_b ,
tri_lcb_delay_lclkr_dc ,
tri_lcb_clkoff_dc_b ,
tri_lcb_act_dis_dc };

// ####################################################
// Registers
// ####################################################
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[rd_act_offset]),
.scout(sov[rd_act_offset]),
.din(rd_act_d),
.dout(rd_act_q)
);

tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rd_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[data_out_offset:data_out_offset + port_bitwidth - 1]),
.scout(sov[data_out_offset:data_out_offset + port_bitwidth - 1]),
.din(data_out_d),
.dout(data_out_q)
);

assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in};
assign func_scan_out = sov[0];

endmodule

@ -0,0 +1,621 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_64x34_8w_1r1w.vhdl
// *! DESCRIPTION : 32 entry x 35 bit x 8 way array
// *!
// *!****************************************************************

`include "tri_a2o.vh"

module tri_64x34_8w_1r1w(
gnd,
vdd,
vcs,
nclk,
rd_act,
wr_act,
sg_0,
abst_sl_thold_0,
ary_nsl_thold_0,
time_sl_thold_0,
repr_sl_thold_0,
func_sl_force,
func_sl_thold_0_b,
g8t_clkoff_dc_b,
ccflush_dc,
scan_dis_dc_b,
scan_diag_dc,
g8t_d_mode_dc,
g8t_mpw1_dc_b,
g8t_mpw2_dc_b,
g8t_delay_lclkr_dc,
d_mode_dc,
mpw1_dc_b,
mpw2_dc_b,
delay_lclkr_dc,
wr_abst_act,
rd0_abst_act,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
abist_rd0_adr,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp,
abst_scan_in,
time_scan_in,
repr_scan_in,
func_scan_in,
abst_scan_out,
time_scan_out,
repr_scan_out,
func_scan_out,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
write_enable,
way,
addr_wr,
data_in,
addr_rd_01,
addr_rd_23,
addr_rd_45,
addr_rd_67,
data_out
);
parameter addressable_ports = 64; // number of addressable register in this array
parameter addressbus_width = 6; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
parameter port_bitwidth = 34; // bitwidth of ports
parameter ways = 8; // number of ways
// POWER PINS
inout gnd;
inout vdd;
inout vcs;

// CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk;
input rd_act;
input wr_act;
input sg_0;
input abst_sl_thold_0;
input ary_nsl_thold_0;
input time_sl_thold_0;
input repr_sl_thold_0;
input func_sl_force;
input func_sl_thold_0_b;
input g8t_clkoff_dc_b;
input ccflush_dc;
input scan_dis_dc_b;
input scan_diag_dc;
input g8t_d_mode_dc;
input [0:4] g8t_mpw1_dc_b;
input g8t_mpw2_dc_b;
input [0:4] g8t_delay_lclkr_dc;
input d_mode_dc;
input mpw1_dc_b;
input mpw2_dc_b;
input delay_lclkr_dc;

// ABIST
input wr_abst_act;
input rd0_abst_act;
input [0:3] abist_di;
input abist_bw_odd;
input abist_bw_even;
input [0:addressbus_width-1] abist_wr_adr;
input [0:addressbus_width-1] abist_rd0_adr;
input tc_lbist_ary_wrt_thru_dc;
input abist_ena_1;
input abist_g8t_rd0_comp_ena;
input abist_raw_dc_b;
input [0:3] obs0_abist_cmp;

// SCAN
input abst_scan_in;
input time_scan_in;
input repr_scan_in;
input func_scan_in;
output abst_scan_out;
output time_scan_out;
output repr_scan_out;
output func_scan_out;

// BOLT-ON
input lcb_bolt_sl_thold_0;
input pc_bo_enable_2; // general bolt-on enable
input pc_bo_reset; // reset
input pc_bo_unload; // unload sticky bits
input pc_bo_repair; // execute sticky bit decode
input pc_bo_shdata; // shift data for timing write and diag loop
input [0:3] pc_bo_select; // select for mask and hier writes
output [0:3] bo_pc_failout; // fail/no-fix reg
output [0:3] bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;

// Write Ports
input [0:3] write_enable;
input [0:ways-1] way;
input [0:addressbus_width-1] addr_wr;
input [0:port_bitwidth-1] data_in;

// Read Ports
input [0:addressbus_width-1] addr_rd_01;
input [0:addressbus_width-1] addr_rd_23;
input [0:addressbus_width-1] addr_rd_45;
input [0:addressbus_width-1] addr_rd_67;
output [0:port_bitwidth*ways-1] data_out;

// tri_64x34_8w_1r1w
parameter ramb_base_addr = 16;
parameter dataWidth = ((((port_bitwidth - 1)/36) + 1) * 36) - 1;
parameter numBytes = (dataWidth/9);

// Configuration Statement for NCsim
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
parameter rd_act_offset = 0;
parameter data_out_offset = rd_act_offset + 1;
parameter scan_right = data_out_offset + (ways*port_bitwidth) - 1;

wire [0:35] ramb_data_in;
wire [0:35] ramb_data_p0_out[0:ways-1];
wire [0:(dataWidth+1)*ways-1] ramb_data_p0_concat;
wire [0:ramb_base_addr-1] ramb_addr_rd1;
wire [0:ramb_base_addr-1] ramb_addr_wr_rd0;

wire [0:ramb_base_addr-1] rd_addr0;
wire [0:ramb_base_addr-1] wr_addr;
wire write_en;
wire [0:3] write_enable_way[0:ways-1];
wire [0:(dataWidth-numBytes)-1] arr_data_in;
wire [0:numBytes] arr_par_in;
wire [0:(dataWidth-numBytes)-1] arr_data_out[0:ways-1];
wire [0:numBytes] arr_par_out[0:ways-1];
wire [0:dataWidth] arr_data_out_pad[0:ways-1];
wire [0:(dataWidth+1)*ways-1] arr_data_concat;
wire [0:port_bitwidth*ways-1] data_out_d;
wire [0:port_bitwidth*ways-1] data_out_q;
wire [0:ways-1] cascadeoutlata;
wire [0:ways-1] cascadeoutlatb;
wire [0:ways-1] cascadeoutrega;
wire [0:ways-1] cascadeoutregb;
wire rd_act_d;
wire rd_act_q;

(* analysis_not_referenced="true" *)
wire unused;
wire tiup;
wire [0:35] tidn;
wire [0:scan_right] siv;
wire [0:scan_right] sov;

generate begin

assign tiup = 1'b1;
assign tidn = 36'b0;

// Data Generate
genvar t;
for (t = 0; t < 36; t = t + 1)
begin : addr_calc
if (t < 35 - (port_bitwidth - 1))
begin
assign ramb_data_in[t] = 1'b0;
end
if (t >= 35 - (port_bitwidth - 1))
begin
assign ramb_data_in[t] = data_in[t - (35 - (port_bitwidth - 1))];
end
end

genvar bb;
for (bb = 0; bb <= numBytes; bb = bb + 1) begin : dFixUp
assign arr_data_in[bb*8:(bb*8)+7] = ramb_data_in[(bb * 8)+bb:(((bb*8)+7)+bb)];
assign arr_par_in[bb] = ramb_data_in[(((bb*8)+bb)+8)];
genvar numWays;
for (numWays=0; numWays<ways; numWays=numWays+1) begin : wayRd
assign arr_data_out_pad[numWays][(bb * 8) + bb:(((bb * 8) + 7) + bb)] = arr_data_out[numWays][bb * 8:(bb * 8) + 7];
assign arr_data_out_pad[numWays][(((bb * 8) + bb) + 8)] = arr_par_out[numWays][bb];
end
end

// Read/Write Port Address Generate
assign rd_addr0[1] = 1'b0;
assign rd_addr0[0] = 1'b0;
assign rd_addr0[11:15] = 5'b0;
assign wr_addr[1] = 1'b0;
assign wr_addr[0] = 1'b0;
assign wr_addr[11:15] = 5'b0;

for (t = 0; t < 9; t = t + 1) begin : rambAddrCalc
if (t < 9 - addressbus_width) begin
assign rd_addr0[t+2] = 1'b0;
assign wr_addr[t+2] = 1'b0;
end
if (t >= 9 - addressbus_width) begin
assign rd_addr0[t+2] = addr_rd_01[t - (9 - addressbus_width)];
assign wr_addr[t+2] = addr_wr[t - (9 - addressbus_width)];
end
end

genvar numWays;
for (numWays=0; numWays<ways; numWays=numWays+1) begin : dOut
assign data_out_d[(numWays*port_bitwidth):(numWays*port_bitwidth)+port_bitwidth-1] = arr_data_out_pad[numWays][(35 - (port_bitwidth - 1)):35];
assign arr_data_concat[(numWays*(dataWidth+1)):(numWays*(dataWidth+1))+(dataWidth+1)-1] = arr_data_out_pad[numWays];
assign ramb_data_p0_concat[(numWays*(dataWidth+1)):(numWays*(dataWidth+1))+(dataWidth+1)-1] = ramb_data_p0_out[numWays];
assign write_enable_way[numWays] = {4{write_enable[numWays/2] & way[numWays]}};
end

end
endgenerate

// Writing on PortA
// Reading on PortB
assign ramb_addr_rd1 = rd_addr0;
assign write_en = |(write_enable);
assign ramb_addr_wr_rd0 = wr_addr;
assign rd_act_d = rd_act;
assign data_out = data_out_q;

// all, none, warning_only, generate_x_only
RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr0_A(
.CASCADEOUTLATA(cascadeoutlata[0]),
.CASCADEOUTLATB(cascadeoutlatb[0]),
.CASCADEOUTREGA(cascadeoutrega[0]),
.CASCADEOUTREGB(cascadeoutregb[0]),
.DOA(ramb_data_p0_out[0][0:31]),
.DOB(arr_data_out[0]),
.DOPA(ramb_data_p0_out[0][32:35]),
.DOPB(arr_par_out[0]),
.ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1),
.CASCADEINLATA(1'b0),
.CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(arr_data_in),
.DIB(tidn[0:31]),
.DIPA(arr_par_in),
.DIPB(tidn[32:35]),
.ENA(write_en),
.ENB(rd_act),
.REGCEA(1'b0),
.REGCEB(1'b0),
.SSRA(nclk[1]), //sreset
.SSRB(nclk[1]), //sreset
.WEA(write_enable_way[0]),
.WEB(tidn[0:3])
);

// all, none, warning_only, generate_x_only
RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr1_B(
.CASCADEOUTLATA(cascadeoutlata[1]),
.CASCADEOUTLATB(cascadeoutlatb[1]),
.CASCADEOUTREGA(cascadeoutrega[1]),
.CASCADEOUTREGB(cascadeoutregb[1]),
.DOA(ramb_data_p0_out[1][0:31]),
.DOB(arr_data_out[1]),
.DOPA(ramb_data_p0_out[1][32:35]),
.DOPB(arr_par_out[1]),
.ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1),
.CASCADEINLATA(1'b0),
.CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(arr_data_in),
.DIB(tidn[0:31]),
.DIPA(arr_par_in),
.DIPB(tidn[32:35]),
.ENA(write_en),
.ENB(rd_act),
.REGCEA(1'b0),
.REGCEB(1'b0),
.SSRA(nclk[1]),
.SSRB(nclk[1]),
.WEA(write_enable_way[1]),
.WEB(tidn[0:3])
);

// all, none, warning_only, generate_x_only
RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr2_C(
.CASCADEOUTLATA(cascadeoutlata[2]),
.CASCADEOUTLATB(cascadeoutlatb[2]),
.CASCADEOUTREGA(cascadeoutrega[2]),
.CASCADEOUTREGB(cascadeoutregb[2]),
.DOA(ramb_data_p0_out[2][0:31]),
.DOB(arr_data_out[2]),
.DOPA(ramb_data_p0_out[2][32:35]),
.DOPB(arr_par_out[2]),
.ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1),
.CASCADEINLATA(1'b0),
.CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(arr_data_in),
.DIB(tidn[0:31]),
.DIPA(arr_par_in),
.DIPB(tidn[32:35]),
.ENA(write_en),
.ENB(rd_act),
.REGCEA(1'b0),
.REGCEB(1'b0),
.SSRA(nclk[1]),
.SSRB(nclk[1]),
.WEA(write_enable_way[2]),
.WEB(tidn[0:3])
);

// all, none, warning_only, generate_x_only
RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr3_D(
.CASCADEOUTLATA(cascadeoutlata[3]),
.CASCADEOUTLATB(cascadeoutlatb[3]),
.CASCADEOUTREGA(cascadeoutrega[3]),
.CASCADEOUTREGB(cascadeoutregb[3]),
.DOA(ramb_data_p0_out[3][0:31]),
.DOB(arr_data_out[3]),
.DOPA(ramb_data_p0_out[3][32:35]),
.DOPB(arr_par_out[3]),
.ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1),
.CASCADEINLATA(1'b0),
.CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(arr_data_in),
.DIB(tidn[0:31]),
.DIPA(arr_par_in),
.DIPB(tidn[32:35]),
.ENA(write_en),
.ENB(rd_act),
.REGCEA(1'b0),
.REGCEB(1'b0),
.SSRA(nclk[1]),
.SSRB(nclk[1]),
.WEA(write_enable_way[3]),
.WEB(tidn[0:3])
);

// all, none, warning_only, generate_x_only
RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr4_E(
.CASCADEOUTLATA(cascadeoutlata[4]),
.CASCADEOUTLATB(cascadeoutlatb[4]),
.CASCADEOUTREGA(cascadeoutrega[4]),
.CASCADEOUTREGB(cascadeoutregb[4]),
.DOA(ramb_data_p0_out[4][0:31]),
.DOB(arr_data_out[4]),
.DOPA(ramb_data_p0_out[4][32:35]),
.DOPB(arr_par_out[4]),
.ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1),
.CASCADEINLATA(1'b0),
.CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(arr_data_in),
.DIB(tidn[0:31]),
.DIPA(arr_par_in),
.DIPB(tidn[32:35]),
.ENA(write_en),
.ENB(rd_act),
.REGCEA(1'b0),
.REGCEB(1'b0),
.SSRA(nclk[1]),
.SSRB(nclk[1]),
.WEA(write_enable_way[4]),
.WEB(tidn[0:3])
);

// all, none, warning_only, generate_x_only
RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr5_F(
.CASCADEOUTLATA(cascadeoutlata[5]),
.CASCADEOUTLATB(cascadeoutlatb[5]),
.CASCADEOUTREGA(cascadeoutrega[5]),
.CASCADEOUTREGB(cascadeoutregb[5]),
.DOA(ramb_data_p0_out[5][0:31]),
.DOB(arr_data_out[5]),
.DOPA(ramb_data_p0_out[5][32:35]),
.DOPB(arr_par_out[5]),
.ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1),
.CASCADEINLATA(1'b0),
.CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(arr_data_in),
.DIB(tidn[0:31]),
.DIPA(arr_par_in),
.DIPB(tidn[32:35]),
.ENA(write_en),
.ENB(rd_act),
.REGCEA(1'b0),
.REGCEB(1'b0),
.SSRA(nclk[1]),
.SSRB(nclk[1]),
.WEA(write_enable_way[5]),
.WEB(tidn[0:3])
);

// all, none, warning_only, generate_x_only
RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr6_G(
.CASCADEOUTLATA(cascadeoutlata[6]),
.CASCADEOUTLATB(cascadeoutlatb[6]),
.CASCADEOUTREGA(cascadeoutrega[6]),
.CASCADEOUTREGB(cascadeoutregb[6]),
.DOA(ramb_data_p0_out[6][0:31]),
.DOB(arr_data_out[6]),
.DOPA(ramb_data_p0_out[6][32:35]),
.DOPB(arr_par_out[6]),
.ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1),
.CASCADEINLATA(1'b0),
.CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(arr_data_in),
.DIB(tidn[0:31]),
.DIPA(arr_par_in),
.DIPB(tidn[32:35]),
.ENA(write_en),
.ENB(rd_act),
.REGCEA(1'b0),
.REGCEB(1'b0),
.SSRA(nclk[1]),
.SSRB(nclk[1]),
.WEA(write_enable_way[6]),
.WEB(tidn[0:3])
);

// all, none, warning_only, generate_x_only
RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr7_H(
.CASCADEOUTLATA(cascadeoutlata[7]),
.CASCADEOUTLATB(cascadeoutlatb[7]),
.CASCADEOUTREGA(cascadeoutrega[7]),
.CASCADEOUTREGB(cascadeoutregb[7]),
.DOA(ramb_data_p0_out[7][0:31]),
.DOB(arr_data_out[7]),
.DOPA(ramb_data_p0_out[7][32:35]),
.DOPB(arr_par_out[7]),
.ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1),
.CASCADEINLATA(1'b0),
.CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(arr_data_in),
.DIB(tidn[0:31]),
.DIPA(arr_par_in),
.DIPB(tidn[32:35]),
.ENA(write_en),
.ENB(rd_act),
.REGCEA(1'b0),
.REGCEB(1'b0),
.SSRA(nclk[1]),
.SSRB(nclk[1]),
.WEA(write_enable_way[7]),
.WEB(tidn[0:3])
);

assign abst_scan_out = tidn[0];
assign time_scan_out = tidn[0];
assign repr_scan_out = tidn[0];
assign bo_pc_failout = tidn[0:3];
assign bo_pc_diagloop = tidn[0:3];

assign unused = |({cascadeoutlata, cascadeoutlatb, cascadeoutrega, cascadeoutregb, tiup, wr_act,
ramb_data_p0_concat, nclk[2:`NCLK_WIDTH-1], gnd, vdd, vcs, sg_0, abst_sl_thold_0, ary_nsl_thold_0,
time_sl_thold_0, repr_sl_thold_0, g8t_clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc,
g8t_d_mode_dc, g8t_mpw1_dc_b, g8t_mpw2_dc_b, g8t_delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di,
abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1,
abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in,
lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc, addr_rd_23, addr_rd_45, addr_rd_67, arr_data_concat});

// ####################################################
// Registers
// ####################################################

tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[rd_act_offset]),
.scout(sov[rd_act_offset]),
.din(rd_act_d),
.dout(rd_act_q)
);

tri_rlmreg_p #(.WIDTH((ways*port_bitwidth)), .INIT(0), .NEEDS_SRESET(1)) data_out_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rd_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[data_out_offset:data_out_offset + (ways*port_bitwidth) - 1]),
.scout(sov[data_out_offset:data_out_offset + (ways*port_bitwidth) - 1]),
.din(data_out_d),
.dout(data_out_q)
);

assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in};
assign func_scan_out = sov[0];

endmodule

@ -0,0 +1,317 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ps / 1 ps

//*****************************************************************************
// Description: Tri-Lam Array Wrapper
//
//*****************************************************************************

`include "tri_a2o.vh"

module tri_64x72_1r1w(
vdd,
vcs,
gnd,
nclk,
sg_0,
abst_sl_thold_0,
ary_nsl_thold_0,
time_sl_thold_0,
repr_sl_thold_0,
rd0_act,
rd0_adr,
do0,
wr_act,
wr_adr,
di,
abst_scan_in,
abst_scan_out,
time_scan_in,
time_scan_out,
repr_scan_in,
repr_scan_out,
scan_dis_dc_b,
scan_diag_dc,
ccflush_dc,
clkoff_dc_b,
d_mode_dc,
mpw1_dc_b,
mpw2_dc_b,
delay_lclkr_dc,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
wr_abst_act,
abist_rd0_adr,
rd0_abst_act,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp
);

// Power
(* analysis_not_referenced="true" *)
inout vdd;
(* analysis_not_referenced="true" *)
inout vcs;
(* analysis_not_referenced="true" *)
inout gnd;

// Clock Pervasive
input [0:`NCLK_WIDTH-1] nclk;
input sg_0;
input abst_sl_thold_0;
input ary_nsl_thold_0;
input time_sl_thold_0;
input repr_sl_thold_0;

// Reads
input rd0_act;
input [0:5] rd0_adr;
output [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] do0;

// Writes
input wr_act;
input [0:5] wr_adr;
input [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] di;

// Scan
input abst_scan_in;
output abst_scan_out;
input time_scan_in;
output time_scan_out;
input repr_scan_in;
output repr_scan_out;

// Misc Pervasive
input scan_dis_dc_b;
input scan_diag_dc;
input ccflush_dc;
input clkoff_dc_b;
input d_mode_dc;
input [0:4] mpw1_dc_b;
input mpw2_dc_b;
input [0:4] delay_lclkr_dc;

// BOLT-ON
input lcb_bolt_sl_thold_0;
input pc_bo_enable_2; // general bolt-on enable
input pc_bo_reset; // reset
input pc_bo_unload; // unload sticky bits
input pc_bo_repair; // execute sticky bit decode
input pc_bo_shdata; // shift data for timing write and diag loop
input pc_bo_select; // select for mask and hier writes
output bo_pc_failout; // fail/no-fix reg
output bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;

// ABIST
input [0:3] abist_di;
input abist_bw_odd;
input abist_bw_even;
input [0:5] abist_wr_adr;
input wr_abst_act;
input [0:5] abist_rd0_adr;
input rd0_abst_act;
input tc_lbist_ary_wrt_thru_dc;
input abist_ena_1;
input abist_g8t_rd0_comp_ena;
input abist_raw_dc_b;
input [0:3] obs0_abist_cmp;

// Configuration Statement for NCsim
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;

wire clk;
wire clk2x;
reg [0:8] addra;
reg [0:8] addrb;
reg wea;
reg web;
wire [0:71] bdo;
wire [0:71] bdi;
wire sreset;
wire [0:71] tidn;
// Latches
reg reset_q;
reg gate_fq;
wire gate_d;
wire [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] bdo_d;
reg [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] bdo_fq;

wire toggle_d;
reg toggle_q;
wire toggle2x_d;
reg toggle2x_q;

(* analysis_not_referenced="true" *)
wire unused;

generate
begin
assign tidn = 72'b0;
assign clk = nclk[0];
assign clk2x = nclk[2];
assign sreset = nclk[1];

always @(posedge clk)
begin: rlatch
// reset_q <= #10 sreset;
reset_q <= sreset; //wtf try for icarus
end

//
// NEW clk2x gate logic start
//

always @(posedge clk)
begin: tlatch
if (reset_q == 1'b1)
toggle_q <= 1'b1;
else
toggle_q <= toggle_d;
end

always @(posedge clk2x)
begin: flatch
toggle2x_q <= toggle2x_d;
gate_fq <= gate_d;
bdo_fq <= bdo_d;
end

assign toggle_d = (~toggle_q);
assign toggle2x_d = toggle_q;

// should force gate_fq to be on during odd 2x clock (second half of 1x clock).
//gate_d <= toggle_q xor toggle2x_q;
// if you want the first half do the following
assign gate_d = (~(toggle_q ^ toggle2x_q));

//
// NEW clk2x gate logic end
//

if (`GPR_WIDTH == 32)
begin
assign bdi = {tidn[0:31], di[32:63], di[64:70], tidn[71]};
end
if (`GPR_WIDTH == 64)
begin
assign bdi = di[0:71];
end

assign bdo_d = bdo[64 - `GPR_WIDTH:72 - (64/`GPR_WIDTH)];
assign do0 = bdo_fq;


always @ (*)
begin
/*
wea = #10 (wr_act & gate_fq);
web = #10 (wr_act & gate_fq);

addra = #10 ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b0} :
{2'b00, rd0_adr, 1'b0});

addrb = #10 ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b1} :
{2'b00, rd0_adr, 1'b1});
wea = #10 (wr_act & gate_fq);
*/
wea = wr_act & gate_fq;
web = wr_act & gate_fq;

addra = ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b0} :
{2'b00, rd0_adr, 1'b0});

addrb = ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b1} :
{2'b00, rd0_adr, 1'b1});
end
/* make wires?
assign wea = wr_act & gate_fq;
assign web = wr_act & gate_fq;
assign addra = ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b0} : {2'b00, rd0_adr, 1'b0});
assign addrb = ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b1} : {2'b00, rd0_adr, 1'b1});
*/

RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
bram0a(
.CLKA(clk2x),
.CLKB(clk2x),
.SSRA(sreset),
.SSRB(sreset),
.ADDRA(addra),
.ADDRB(addrb),
.DIA(bdi[00:31]),
.DIB(bdi[32:63]),
.DIPA(bdi[64:67]),
.DIPB(bdi[68:71]),
.DOA(bdo[00:31]),
.DOB(bdo[32:63]),
.DOPA(bdo[64:67]),
.DOPB(bdo[68:71]),
.ENA(1'b1),
.ENB(1'b1),
.WEA(wea),
.WEB(web)
);

assign abst_scan_out = abst_scan_in;
assign time_scan_out = time_scan_in;
assign repr_scan_out = repr_scan_in;

assign bo_pc_failout = 1'b0;
assign bo_pc_diagloop = 1'b0;

assign unused = | ({nclk[3:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc});
end
endgenerate
endmodule

@ -0,0 +1,188 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`ifndef _tri_a2o_vh_
`define _tri_a2o_vh_

`include "tri.vh"

// Use this line for 1 thread. Comment out for 2 thread design.
`define THREADS1

`define gpr_t 3'b000
`define cr_t 3'b001
`define lr_t 3'b010
`define ctr_t 3'b011
`define xer_t 3'b100
`define spr_t 3'b101
`define axu0_t 3'b110
`define axu1_t 3'b111

`ifdef THREADS1
`define THREADS 1
`define THREAD_POOL_ENC 0
`define THREADS_POOL_ENC 0
`else
`define THREADS 2
`define THREAD_POOL_ENC 1
`define THREADS_POOL_ENC 1
`endif
`define EFF_IFAR_ARCH 62
`define EFF_IFAR_WIDTH 20
`define EFF_IFAR 20
`define FPR_POOL_ENC 6
`define REGMODE 6
`define FPR_POOL 64
`define REAL_IFAR_WIDTH 42
`define EMQ_ENTRIES 4
`define GPR_WIDTH 64
`define ITAG_SIZE_ENC 7
`define CPL_Q_DEPTH 32
`define CPL_Q_DEPTH_ENC 6
`define GPR_WIDTH_ENC 6
`define GPR_POOL_ENC 6
`define GPR_POOL 64
`define GPR_UCODE_POOL 4
`define CR_POOL_ENC 5
`define CR_POOL 24
`define CR_UCODE_POOL 1
`define BR_POOL_ENC 3
`define BR_POOL 8
`define LR_POOL_ENC 3
`define LR_POOL 8
`define LR_UCODE_POOL 0
`define CTR_POOL_ENC 3
`define CTR_POOL 8
`define CTR_UCODE_POOL 0
`define XER_POOL_ENC 4
`define XER_POOL 12
`define XER_UCODE_POOL 0
`define LDSTQ_ENTRIES 16
`define LDSTQ_ENTRIES_ENC 4
`define STQ_ENTRIES 12
`define STQ_ENTRIES_ENC 4
`define STQ_FWD_ENTRIES 4 // number of stq entries that can be forwarded from
`define STQ_DATA_SIZE 64 // 64 or 128 Bit store data sizes supported
`define DC_SIZE 15 // 14 => 16K L1D$, 15 => 32K L1D$
`define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE
`define LMQ_ENTRIES 8
`define LMQ_ENTRIES_ENC 3
`define LGQ_ENTRIES 8
`define AXU_SPARE_ENC 3
`define RV_FX0_ENTRIES 12
`define RV_FX1_ENTRIES 12
`define RV_LQ_ENTRIES 16
`define RV_AXU0_ENTRIES 12
`define RV_AXU1_ENTRIES 0
`define RV_FX0_ENTRIES_ENC 4
`define RV_FX1_ENTRIES_ENC 4
`define RV_LQ_ENTRIES_ENC 4
`define RV_AXU0_ENTRIES_ENC 4
`define RV_AXU1_ENTRIES_ENC 1
`define UCODE_ENTRIES 8
`define UCODE_ENTRIES_ENC 3
`define FXU1_ENABLE 1
`define TYPE_WIDTH 3
`define IBUFF_INSTR_WIDTH 70
`define IBUFF_IFAR_WIDTH 20
`define IBUFF_DEPTH 16
`define PF_IAR_BITS 12 // number of IAR bits used by prefetch
`define FXU0_PIPE_START 1
`define FXU0_PIPE_END 8
`define FXU1_PIPE_START 1
`define FXU1_PIPE_END 5
`define LQ_LOAD_PIPE_START 4
`define LQ_LOAD_PIPE_END 8
`define LQ_REL_PIPE_START 2
`define LQ_REL_PIPE_END 4
`define LOAD_CREDITS 8
`define STORE_CREDITS 4
`define IUQ_ENTRIES 4 // Instruction Fetch Queue Size
`define MMQ_ENTRIES 2 // MMU Queue Size
`define CR_WIDTH 4
`define BUILD_PFETCH 1 // 1=> include pfetch in the build, 0=> build without pfetch
`define PF_IFAR_WIDTH 12
`define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch
`define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries)
`define PFETCH_Q_SIZE 8 // number of entries
`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings)
`define XER_WIDTH 10

//wtf: change for verilatorsim - didnt help
//`define INIT_BHT 1 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT
//`define INIT_IUCR0 16'h00FA // BP enabled
`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT
`define INIT_IUCR0 16'h0000 // BP disabled

`define INIT_MASK 2'b10
`define RELQ_INCLUDE 0 // Reload Queue Included

`define G_BRANCH_LEN `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1

//wtf: add completion stuff
/*
assign spr_cpcr0_fx0_cnt = cpcr0_l2[35:39];
assign spr_cpcr0_fx1_cnt = cpcr0_l2[43:47];
assign spr_cpcr0_lq_cnt = cpcr0_l2[51:55];
assign spr_cpcr0_sq_cnt = cpcr0_l2[59:63];
*/
`define INIT_CPCR0 32'h0C0C100C // 000a aaaa 000b bbbb 000c cccc 000d dddd watermarks: a=fx0 b=fx1 c=ls d=sq ---- um p.543 wrong!; was this in vlog: hex 0C0C100C = 202117132
//`define INIT_CPCR0 32'h01010201 // 1/1/2/1
/*
assign spr_cpcr1_fu0_cnt = cpcr1_l2[43:47];
assign spr_cpcr1_fu1_cnt = cpcr1_l2[51:55];
*/
`define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504
//`define INIT_CPCR1 32'h00010100 // 1/1

// IERAT boot config entry values
`define IERAT_BCFG_EPN_0TO15 0
`define IERAT_BCFG_EPN_16TO31 0
`define IERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G
`define IERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
`define IERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff
`define IERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8181 for 512M, 65535 for 4G
`define IERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
`define IERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page
`define IERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page
`define IERAT_BCFG_ATTR 0 // u0-u3, endian

// DERAT boot config entry values
`define DERAT_BCFG_EPN_0TO15 0
`define DERAT_BCFG_EPN_16TO31 0
`define DERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G
`define DERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
`define DERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff
`define DERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8191 for 512M, 65535 for 4G
`define DERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
`define DERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page
`define DERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page
`define DERAT_BCFG_ATTR 0 // u0-u3, endian

// Do NOT add any defines below this line
`endif //_tri_a2o_vh_

@ -0,0 +1,101 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// Description: Address Decoder
//
//*****************************************************************************

module tri_addrcmp(
enable_lsb,
d0,
d1,
eq
);

input enable_lsb; // when "0" the LSB is disabled
input [0:35] d0;
input [0:35] d1;
output eq;

// tri_addrcmp

parameter tiup = 1'b1;
parameter tidn = 1'b0;

wire [0:35] eq01_b;
wire [0:18] eq02;
wire [0:9] eq04_b;
wire [0:4] eq08;
wire [0:1] eq24_b;

assign eq01_b[0:35] = (d0[0:35] ^ d1[0:35]);

assign eq02[0] = (~(eq01_b[0] | eq01_b[1]));
assign eq02[1] = (~(eq01_b[2] | eq01_b[3]));
assign eq02[2] = (~(eq01_b[4] | eq01_b[5]));
assign eq02[3] = (~(eq01_b[6] | eq01_b[7]));
assign eq02[4] = (~(eq01_b[8] | eq01_b[9]));
assign eq02[5] = (~(eq01_b[10] | eq01_b[11]));
assign eq02[6] = (~(eq01_b[12] | eq01_b[13]));
assign eq02[7] = (~(eq01_b[14] | eq01_b[15]));
assign eq02[8] = (~(eq01_b[16] | eq01_b[17]));
assign eq02[9] = (~(eq01_b[18] | eq01_b[19]));
assign eq02[10] = (~(eq01_b[20] | eq01_b[21]));
assign eq02[11] = (~(eq01_b[22] | eq01_b[23]));
assign eq02[12] = (~(eq01_b[24] | eq01_b[25]));
assign eq02[13] = (~(eq01_b[26] | eq01_b[27]));
assign eq02[14] = (~(eq01_b[28] | eq01_b[29]));
assign eq02[15] = (~(eq01_b[30] | eq01_b[31]));
assign eq02[16] = (~(eq01_b[32] | eq01_b[33]));
assign eq02[17] = (~(eq01_b[34]));
assign eq02[18] = (~(eq01_b[35] & enable_lsb));

assign eq04_b[0] = (~(eq02[0] & eq02[1]));
assign eq04_b[1] = (~(eq02[2] & eq02[3]));
assign eq04_b[2] = (~(eq02[4] & eq02[5]));
assign eq04_b[3] = (~(eq02[6] & eq02[7]));
assign eq04_b[4] = (~(eq02[8] & eq02[9]));
assign eq04_b[5] = (~(eq02[10] & eq02[11]));
assign eq04_b[6] = (~(eq02[12] & eq02[13]));
assign eq04_b[7] = (~(eq02[14] & eq02[15]));
assign eq04_b[8] = (~(eq02[16] & eq02[17]));
assign eq04_b[9] = (~(eq02[18]));

assign eq08[0] = (~(eq04_b[0] | eq04_b[1]));
assign eq08[1] = (~(eq04_b[2] | eq04_b[3]));
assign eq08[2] = (~(eq04_b[4] | eq04_b[5]));
assign eq08[3] = (~(eq04_b[6] | eq04_b[7]));
assign eq08[4] = (~(eq04_b[8] | eq04_b[9]));

assign eq24_b[0] = (~(eq08[0] & eq08[1] & eq08[2]));
assign eq24_b[1] = (~(eq08[3] & eq08[4]));

assign eq = (~(eq24_b[0] | eq24_b[1])); // output
endmodule

@ -0,0 +1,60 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// Description: Prioritizer
//
//*****************************************************************************

module tri_agecmp(
a,
b,
a_newer_b
);
parameter SIZE = 8;

input [0:SIZE-1] a;
input [0:SIZE-1] b;
output a_newer_b;

// tri_agecmp

wire a_lt_b;
wire a_gte_b;
wire cmp_sel;

assign a_lt_b = (a[1:SIZE - 1] < b[1:SIZE - 1]) ? 1'b1 :
1'b0;

assign a_gte_b = (~a_lt_b);

assign cmp_sel = a[0] ~^ b[0];

assign a_newer_b = (a_lt_b & (~cmp_sel)) | (a_gte_b & cmp_sel);
endmodule

@ -0,0 +1,68 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_nand2.v
// *! DESCRIPTION : Three input, AOI21 gate
// *!
// *!****************************************************************

`include "tri_a2o.vh"

module tri_aoi21(
y,
a0,
a1,
b0
);
parameter WIDTH = 1;
parameter BTR = "AOI21_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a0;
input [0:WIDTH-1] a1;
input [0:WIDTH-1] b0;

// tri_aoi21
genvar i;
wire [0:WIDTH-1] outA;

generate
begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w

and I0(outA[i], a0[i], a1[i]);
nor I2(y[i], outA[i], b0[i]);

end // block: w
end

endgenerate
endmodule

@ -0,0 +1,73 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_aoi22.v
// *! DESCRIPTION : AOI22 gate
// *!
// *!****************************************************************

`include "tri_a2o.vh"

module tri_aoi22(
y,
a0,
a1,
b0,
b1
);
parameter WIDTH = 1;
parameter BTR = "AOI22_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a0;
input [0:WIDTH-1] a1;
input [0:WIDTH-1] b0;
input [0:WIDTH-1] b1;

// tri_aoi22
genvar i;
wire [0:WIDTH-1] outA;
wire [0:WIDTH-1] outB;

generate
begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w

and I0(outA[i], a0[i], a1[i]);
and I1(outB[i], b0[i], b1[i]);
nor I2(y[i], outA[i], outB[i]);


end // block: w
end

endgenerate
endmodule

@ -0,0 +1,145 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_aoi22_nlats_wlcb.v
// *! DESCRIPTION : Multi-bit aoi22-latch, LCB included
// *!
// *!****************************************************************

`include "tri_a2o.vh"

module tri_aoi22_nlats_wlcb(
vd,
gd,
nclk,
act,
force_t,
thold_b,
d_mode,
sg,
delay_lclkr,
mpw1_b,
mpw2_b,
scin,
scout,
a1,
a2,
b1,
b2,
qb
);

parameter WIDTH = 4;
parameter OFFSET = 0; //starting bit
parameter INIT = 0; // will be converted to the least signficant
// 31 bits of init_v
parameter IBUF = 1'b0; //inverted latch IOs, if set to true.
parameter DUALSCAN = ""; // if "S", marks data ports as scan for Moebius
parameter NEEDS_SRESET = 1; // for inferred latches
parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch;
//0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
parameter SYNTHCLONEDLATCH = "";
parameter BTR = "NLL0001_X2_A12TH";

inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input act; // 1: functional, 0: no clock
input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock
input d_mode; // 1: disable pulse mode, 0: pulse mode
input sg; // 0: functional, 1: scan
input delay_lclkr; // 0: functional
input mpw1_b; // pulse width control bit
input mpw2_b; // pulse width control bit
input [OFFSET:OFFSET+WIDTH-1] scin; // scan in
output [OFFSET:OFFSET+WIDTH-1] scout;
input [OFFSET:OFFSET+WIDTH-1] a1;
input [OFFSET:OFFSET+WIDTH-1] a2;
input [OFFSET:OFFSET+WIDTH-1] b1;
input [OFFSET:OFFSET+WIDTH-1] b2;
output [OFFSET:OFFSET+WIDTH-1] qb;

// tri_aoi22_nlats_wlcb

parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};

generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
wire [0:WIDTH-1] din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *)
wire unused;

if (NEEDS_SRESET == 1)
begin : rst
assign sreset = nclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0;
end

assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};

assign din = (a1 & a2) | (b1 & b2); // Output is inverted, so just AND-OR here
assign int_din = (vsreset_b & din) | (vsreset & init_v);

assign vact = {WIDTH{act | force_t}};
assign vact_b = {WIDTH{~(act | force_t)}};

assign vthold_b = {WIDTH{thold_b}};
assign vthold = {WIDTH{~thold_b}};


always @(posedge nclk[0])
begin: l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end

assign qb = (~int_dout);

assign scout = ZEROS;

assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk) | (|scin);
end
endgenerate
endmodule

@ -0,0 +1,577 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *********************************************************************
//
// This is the ENTITY for tri_bht_1024x8_1r1w
//
// *********************************************************************

(* block_type="soft" *)
(* recursive_synthesis="2" *)
(* pin_default_power_domain="vdd" *)
(* pin_default_ground_domain ="gnd" *)

`include "tri_a2o.vh"

module tri_bht_1024x8_1r1w(
gnd,
vdd,
vcs,
nclk,
pc_iu_func_sl_thold_2,
pc_iu_sg_2,
pc_iu_time_sl_thold_2,
pc_iu_abst_sl_thold_2,
pc_iu_ary_nsl_thold_2,
pc_iu_repr_sl_thold_2,
pc_iu_bolt_sl_thold_2,
tc_ac_ccflush_dc,
tc_ac_scan_dis_dc_b,
clkoff_b,
scan_diag_dc,
act_dis,
d_mode,
delay_lclkr,
mpw1_b,
mpw2_b,
g8t_clkoff_b,
g8t_d_mode,
g8t_delay_lclkr,
g8t_mpw1_b,
g8t_mpw2_b,
func_scan_in,
time_scan_in,
abst_scan_in,
repr_scan_in,
func_scan_out,
time_scan_out,
abst_scan_out,
repr_scan_out,
pc_iu_abist_di_0,
pc_iu_abist_g8t_bw_1,
pc_iu_abist_g8t_bw_0,
pc_iu_abist_waddr_0,
pc_iu_abist_g8t_wenb,
pc_iu_abist_raddr_0,
pc_iu_abist_g8t1p_renb_0,
an_ac_lbist_ary_wrt_thru_dc,
pc_iu_abist_ena_dc,
pc_iu_abist_wl128_comp_ena,
pc_iu_abist_raw_dc_b,
pc_iu_abist_g8t_dcomp,
pc_iu_bo_enable_2,
pc_iu_bo_reset,
pc_iu_bo_unload,
pc_iu_bo_repair,
pc_iu_bo_shdata,
pc_iu_bo_select,
iu_pc_bo_fail,
iu_pc_bo_diagout,
r_act,
w_act,
r_addr,
w_addr,
data_in,
data_out0,
data_out1,
data_out2,
data_out3,
pc_iu_init_reset
);
// power pins
inout gnd;
inout vdd;
inout vcs;

// clock and clockcontrol ports
input [0:`NCLK_WIDTH-1] nclk;
input pc_iu_func_sl_thold_2;
input pc_iu_sg_2;
input pc_iu_time_sl_thold_2;
input pc_iu_abst_sl_thold_2;
input pc_iu_ary_nsl_thold_2;
input pc_iu_repr_sl_thold_2;
input pc_iu_bolt_sl_thold_2;
input tc_ac_ccflush_dc;
input tc_ac_scan_dis_dc_b;
input clkoff_b;
input scan_diag_dc;
input act_dis;
input d_mode;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
input g8t_clkoff_b;
input g8t_d_mode;
input [0:4] g8t_delay_lclkr;
input [0:4] g8t_mpw1_b;
input g8t_mpw2_b;
input func_scan_in;
input time_scan_in;
input abst_scan_in;
input repr_scan_in;
output func_scan_out;
output time_scan_out;
output abst_scan_out;
output repr_scan_out;

input [0:3] pc_iu_abist_di_0;
input pc_iu_abist_g8t_bw_1;
input pc_iu_abist_g8t_bw_0;
input [3:9] pc_iu_abist_waddr_0;
input pc_iu_abist_g8t_wenb;
input [3:9] pc_iu_abist_raddr_0;
input pc_iu_abist_g8t1p_renb_0;
input an_ac_lbist_ary_wrt_thru_dc;
input pc_iu_abist_ena_dc;
input pc_iu_abist_wl128_comp_ena;
input pc_iu_abist_raw_dc_b;
input [0:3] pc_iu_abist_g8t_dcomp;

// BOLT-ON
input pc_iu_bo_enable_2; // general bolt-on enable
input pc_iu_bo_reset; // reset
input pc_iu_bo_unload; // unload sticky bits
input pc_iu_bo_repair; // execute sticky bit decode
input pc_iu_bo_shdata; // shift data for timing write and diag loop
input pc_iu_bo_select; // select for mask and hier writes
output iu_pc_bo_fail; // fail/no-fix reg
output iu_pc_bo_diagout;

// ports
input r_act;
input [0:3] w_act;
input [0:9] r_addr;
input [0:9] w_addr;
input [0:1] data_in;
output [0:1] data_out0;
output [0:1] data_out1;
output [0:1] data_out2;

output [0:1] data_out3;

input pc_iu_init_reset;

//--------------------------
// constants
//--------------------------


parameter data_in_offset = 0;
parameter w_act_offset = data_in_offset + 2;
parameter r_act_offset = w_act_offset + 4;
parameter w_addr_offset = r_act_offset + 1;
parameter r_addr_offset = w_addr_offset + 10;
parameter data_out_offset = r_addr_offset + 10;
parameter reset_w_addr_offset = data_out_offset + 8;
parameter array_offset = reset_w_addr_offset + 9;
parameter scan_right = array_offset + 1 - 1;

//--------------------------
// signals
//--------------------------

wire pc_iu_func_sl_thold_1;
wire pc_iu_func_sl_thold_0;
wire pc_iu_func_sl_thold_0_b;
wire pc_iu_time_sl_thold_1;
wire pc_iu_time_sl_thold_0;
wire pc_iu_ary_nsl_thold_1;
wire pc_iu_ary_nsl_thold_0;
wire pc_iu_abst_sl_thold_1;
wire pc_iu_abst_sl_thold_0;
wire pc_iu_repr_sl_thold_1;
wire pc_iu_repr_sl_thold_0;
wire pc_iu_bolt_sl_thold_1;
wire pc_iu_bolt_sl_thold_0;
wire pc_iu_sg_1;
wire pc_iu_sg_0;
wire force_t;

wire [0:scan_right] siv;
wire [0:scan_right] sov;

wire tiup;

wire [0:7] data_out_d;
wire [0:7] data_out_q;

wire ary_w_en;
wire [0:8] ary_w_addr;
wire [0:15] ary_w_sel;
wire [0:15] ary_w_data;

wire ary_r_en;
wire [0:8] ary_r_addr;
wire [0:15] ary_r_data;

wire [0:7] data_out;
wire [0:3] write_thru;

wire [0:1] data_in_d;
wire [0:1] data_in_q;
wire [0:3] w_act_d;
wire [0:3] w_act_q;
wire r_act_d;
wire r_act_q;
wire [0:9] w_addr_d;
wire [0:9] w_addr_q;
wire [0:9] r_addr_d;
wire [0:9] r_addr_q;

wire lat_wi_act;
wire lat_ri_act;
wire lat_ro_act;

wire reset_act;
wire [0:8] reset_w_addr_d;
wire [0:8] reset_w_addr_q;


assign tiup = 1'b1;

assign reset_act = pc_iu_init_reset;
assign reset_w_addr_d[0:8] = reset_w_addr_q[0:8] + 9'b000000001;

assign data_out0[0:1] = data_out_q[0:1];
assign data_out1[0:1] = data_out_q[2:3];
assign data_out2[0:1] = data_out_q[4:5];
assign data_out3[0:1] = data_out_q[6:7];

assign ary_w_en = reset_act | (|(w_act[0:3]) & (~((w_addr[1:9] == r_addr[1:9]) & r_act == 1'b1)));

assign ary_w_addr[0:8] = reset_act ? reset_w_addr_q[0:8] : w_addr[1:9];

assign ary_w_sel[0] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b0;
assign ary_w_sel[1] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b0;
assign ary_w_sel[2] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b0;
assign ary_w_sel[3] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b0;
assign ary_w_sel[4] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b0;
assign ary_w_sel[5] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b0;
assign ary_w_sel[6] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b0;
assign ary_w_sel[7] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b0;
assign ary_w_sel[8] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b1;
assign ary_w_sel[9] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b1;
assign ary_w_sel[10] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b1;
assign ary_w_sel[11] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b1;
assign ary_w_sel[12] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b1;
assign ary_w_sel[13] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b1;
assign ary_w_sel[14] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b1;
assign ary_w_sel[15] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b1;

assign ary_w_data[0:15] = reset_act ? 16'b0000000000000000:
{(data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK)};

assign ary_r_en = r_act;

assign ary_r_addr[0:8] = r_addr[1:9];

assign data_out[0:7] = (r_addr_q[0] == 1'b0 ? ary_r_data[0:7] ^ ({`INIT_MASK, `INIT_MASK, `INIT_MASK, `INIT_MASK}) : 8'b00000000 ) | (r_addr_q[0] == 1'b1 ? ary_r_data[8:15] ^ ({`INIT_MASK, `INIT_MASK, `INIT_MASK, `INIT_MASK}) : 8'b00000000 );

//write through support

assign data_in_d[0:1] = data_in[0:1];
assign w_act_d[0:3] = w_act[0:3];
assign r_act_d = r_act;
assign w_addr_d[0:9] = w_addr[0:9];
assign r_addr_d[0:9] = r_addr[0:9];

assign write_thru[0:3] = ((w_addr_q[0:9] == r_addr_q[0:9]) & r_act_q == 1'b1) ? w_act_q[0:3] :
4'b0000;

assign data_out_d[0:1] = (write_thru[0] == 1'b1) ? data_in_q[0:1] :
data_out[0:1];
assign data_out_d[2:3] = (write_thru[1] == 1'b1) ? data_in_q[0:1] :
data_out[2:3];
assign data_out_d[4:5] = (write_thru[2] == 1'b1) ? data_in_q[0:1] :
data_out[4:5];
assign data_out_d[6:7] = (write_thru[3] == 1'b1) ? data_in_q[0:1] :
data_out[6:7];

//latch acts
assign lat_wi_act = |(w_act[0:3]);
assign lat_ri_act = r_act;
assign lat_ro_act = r_act_q;

//-----------------------------------------------
// array
//-----------------------------------------------



tri_512x16_1r1w_1 bht0(
.gnd(gnd),
.vdd(vdd),
.vcs(vcs),
.nclk(nclk),

.rd_act(ary_r_en),
.wr_act(ary_w_en),

.lcb_d_mode_dc(g8t_d_mode),
.lcb_clkoff_dc_b(g8t_clkoff_b),
.lcb_mpw1_dc_b(g8t_mpw1_b),
.lcb_mpw2_dc_b(g8t_mpw2_b),
.lcb_delay_lclkr_dc(g8t_delay_lclkr),
.ccflush_dc(tc_ac_ccflush_dc),
.scan_dis_dc_b(tc_ac_scan_dis_dc_b),
.scan_diag_dc(scan_diag_dc),
.func_scan_in(siv[array_offset]),
.func_scan_out(sov[array_offset]),

.lcb_sg_0(pc_iu_sg_0),
.lcb_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
.lcb_time_sl_thold_0(pc_iu_time_sl_thold_0),
.lcb_abst_sl_thold_0(pc_iu_abst_sl_thold_0),
.lcb_ary_nsl_thold_0(pc_iu_ary_nsl_thold_0),
.lcb_repr_sl_thold_0(pc_iu_repr_sl_thold_0),
.time_scan_in(time_scan_in),
.time_scan_out(time_scan_out),
.abst_scan_in(abst_scan_in),
.abst_scan_out(abst_scan_out),
.repr_scan_in(repr_scan_in),
.repr_scan_out(repr_scan_out),

.abist_di(pc_iu_abist_di_0),
.abist_bw_odd(pc_iu_abist_g8t_bw_1),
.abist_bw_even(pc_iu_abist_g8t_bw_0),
.abist_wr_adr(pc_iu_abist_waddr_0),
.wr_abst_act(pc_iu_abist_g8t_wenb),
.abist_rd0_adr(pc_iu_abist_raddr_0),
.rd0_abst_act(pc_iu_abist_g8t1p_renb_0),
.tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
.abist_ena_1(pc_iu_abist_ena_dc),
.abist_g8t_rd0_comp_ena(pc_iu_abist_wl128_comp_ena),
.abist_raw_dc_b(pc_iu_abist_raw_dc_b),
.obs0_abist_cmp(pc_iu_abist_g8t_dcomp),

.lcb_bolt_sl_thold_0(pc_iu_bolt_sl_thold_0),
.pc_bo_enable_2(pc_iu_bo_enable_2),
.pc_bo_reset(pc_iu_bo_reset),
.pc_bo_unload(pc_iu_bo_unload),
.pc_bo_repair(pc_iu_bo_repair),
.pc_bo_shdata(pc_iu_bo_shdata),
.pc_bo_select(pc_iu_bo_select),
.bo_pc_failout(iu_pc_bo_fail),
.bo_pc_diagloop(iu_pc_bo_diagout),

.tri_lcb_mpw1_dc_b(mpw1_b),
.tri_lcb_mpw2_dc_b(mpw2_b),
.tri_lcb_delay_lclkr_dc(delay_lclkr),
.tri_lcb_clkoff_dc_b(clkoff_b),
.tri_lcb_act_dis_dc(act_dis),

.bw(ary_w_sel),
.wr_adr(ary_w_addr),
.rd_adr(ary_r_addr),
.di(ary_w_data),
.dout(ary_r_data)
);

//-----------------------------------------------
// latches
//-----------------------------------------------


tri_rlmreg_p #(.WIDTH(2), .INIT(0)) data_in_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[data_in_offset:data_in_offset + 2 - 1]),
.scout(sov[data_in_offset:data_in_offset + 2 - 1]),
.din(data_in_d),
.dout(data_in_q)
);


tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[w_act_offset:w_act_offset + 4 - 1]),
.scout(sov[w_act_offset:w_act_offset + 4 - 1]),
.din(w_act_d),
.dout(w_act_q)
);


tri_rlmlatch_p #(.INIT(0)) r_act_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[r_act_offset]),
.scout(sov[r_act_offset]),
.din(r_act_d),
.dout(r_act_q)
);


tri_rlmreg_p #(.WIDTH(10), .INIT(0)) w_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[w_addr_offset:w_addr_offset + 10 - 1]),
.scout(sov[w_addr_offset:w_addr_offset + 10 - 1]),
.din(w_addr_d),
.dout(w_addr_q)
);


tri_rlmreg_p #(.WIDTH(10), .INIT(0)) r_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_ri_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[r_addr_offset:r_addr_offset + 10 - 1]),
.scout(sov[r_addr_offset:r_addr_offset + 10 - 1]),
.din(r_addr_d),
.dout(r_addr_q)
);


tri_rlmreg_p #(.WIDTH(8), .INIT(0)) data_out_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_ro_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[data_out_offset:data_out_offset + 8 - 1]),
.scout(sov[data_out_offset:data_out_offset + 8 - 1]),
.din(data_out_d),
.dout(data_out_q)
);

tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(reset_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]),
.scout(sov[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]),
.din(reset_w_addr_d),
.dout(reset_w_addr_q)
);

//-----------------------------------------------
// pervasive
//-----------------------------------------------


tri_plat #(.WIDTH(7)) perv_2to1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}),
.q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1})
);


tri_plat #(.WIDTH(7)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}),
.q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0})
);


tri_lcbor perv_lcbor(
.clkoff_b(clkoff_b),
.thold(pc_iu_func_sl_thold_0),
.sg(pc_iu_sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b)
);

//-----------------------------------------------
// scan
//-----------------------------------------------

assign siv[0:scan_right] = {func_scan_in, sov[0:scan_right - 1]};
assign func_scan_out = sov[scan_right];


endmodule

@ -0,0 +1,577 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *********************************************************************
//
// This is the ENTITY for tri_bht_512x4_1r1w
//
// *********************************************************************

(* block_type="soft" *)
(* recursive_synthesis="2" *)
(* pin_default_power_domain="vdd" *)
(* pin_default_ground_domain ="gnd" *)

`include "tri_a2o.vh"

module tri_bht_512x4_1r1w(
gnd,
vdd,
vcs,
nclk,
pc_iu_func_sl_thold_2,
pc_iu_sg_2,
pc_iu_time_sl_thold_2,
pc_iu_abst_sl_thold_2,
pc_iu_ary_nsl_thold_2,
pc_iu_repr_sl_thold_2,
pc_iu_bolt_sl_thold_2,
tc_ac_ccflush_dc,
tc_ac_scan_dis_dc_b,
clkoff_b,
scan_diag_dc,
act_dis,
d_mode,
delay_lclkr,
mpw1_b,
mpw2_b,
g8t_clkoff_b,
g8t_d_mode,
g8t_delay_lclkr,
g8t_mpw1_b,
g8t_mpw2_b,
func_scan_in,
time_scan_in,
abst_scan_in,
repr_scan_in,
func_scan_out,
time_scan_out,
abst_scan_out,
repr_scan_out,
pc_iu_abist_di_0,
pc_iu_abist_g8t_bw_1,
pc_iu_abist_g8t_bw_0,
pc_iu_abist_waddr_0,
pc_iu_abist_g8t_wenb,
pc_iu_abist_raddr_0,
pc_iu_abist_g8t1p_renb_0,
an_ac_lbist_ary_wrt_thru_dc,
pc_iu_abist_ena_dc,
pc_iu_abist_wl128_comp_ena,
pc_iu_abist_raw_dc_b,
pc_iu_abist_g8t_dcomp,
pc_iu_bo_enable_2,
pc_iu_bo_reset,
pc_iu_bo_unload,
pc_iu_bo_repair,
pc_iu_bo_shdata,
pc_iu_bo_select,
iu_pc_bo_fail,
iu_pc_bo_diagout,
r_act,
w_act,
r_addr,
w_addr,
data_in,
data_out0,
data_out1,
data_out2,
data_out3,
pc_iu_init_reset
);
// power pins
inout gnd;
inout vdd;
inout vcs;

// clock and clockcontrol ports
input [0:`NCLK_WIDTH-1] nclk;
input pc_iu_func_sl_thold_2;
input pc_iu_sg_2;
input pc_iu_time_sl_thold_2;
input pc_iu_abst_sl_thold_2;
input pc_iu_ary_nsl_thold_2;
input pc_iu_repr_sl_thold_2;
input pc_iu_bolt_sl_thold_2;
input tc_ac_ccflush_dc;
input tc_ac_scan_dis_dc_b;
input clkoff_b;
input scan_diag_dc;
input act_dis;
input d_mode;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
input g8t_clkoff_b;
input g8t_d_mode;
input [0:4] g8t_delay_lclkr;
input [0:4] g8t_mpw1_b;
input g8t_mpw2_b;
input func_scan_in;
input time_scan_in;
input abst_scan_in;
input repr_scan_in;
output func_scan_out;
output time_scan_out;
output abst_scan_out;
output repr_scan_out;

input [0:3] pc_iu_abist_di_0;
input pc_iu_abist_g8t_bw_1;
input pc_iu_abist_g8t_bw_0;
input [3:9] pc_iu_abist_waddr_0;
input pc_iu_abist_g8t_wenb;
input [3:9] pc_iu_abist_raddr_0;
input pc_iu_abist_g8t1p_renb_0;
input an_ac_lbist_ary_wrt_thru_dc;
input pc_iu_abist_ena_dc;
input pc_iu_abist_wl128_comp_ena;
input pc_iu_abist_raw_dc_b;
input [0:3] pc_iu_abist_g8t_dcomp;

// BOLT-ON
input pc_iu_bo_enable_2; // general bolt-on enable
input pc_iu_bo_reset; // reset
input pc_iu_bo_unload; // unload sticky bits
input pc_iu_bo_repair; // execute sticky bit decode
input pc_iu_bo_shdata; // shift data for timing write and diag loop
input pc_iu_bo_select; // select for mask and hier writes
output iu_pc_bo_fail; // fail/no-fix reg
output iu_pc_bo_diagout;

// ports
input r_act;
input [0:3] w_act;
input [0:8] r_addr;
input [0:8] w_addr;
input data_in;
output data_out0;
output data_out1;
output data_out2;
output data_out3;

input pc_iu_init_reset;

//--------------------------
// constants
//--------------------------


parameter data_in_offset = 0;
parameter w_act_offset = data_in_offset + 1;
parameter r_act_offset = w_act_offset + 4;
parameter w_addr_offset = r_act_offset + 1;
parameter r_addr_offset = w_addr_offset + 9;
parameter data_out_offset = r_addr_offset + 9;
parameter reset_w_addr_offset = data_out_offset + 4;
parameter array_offset = reset_w_addr_offset + 9;
parameter scan_right = array_offset + 1 - 1;

//--------------------------
// signals
//--------------------------

wire pc_iu_func_sl_thold_1;
wire pc_iu_func_sl_thold_0;
wire pc_iu_func_sl_thold_0_b;
wire pc_iu_time_sl_thold_1;
wire pc_iu_time_sl_thold_0;
wire pc_iu_ary_nsl_thold_1;
wire pc_iu_ary_nsl_thold_0;
wire pc_iu_abst_sl_thold_1;
wire pc_iu_abst_sl_thold_0;
wire pc_iu_repr_sl_thold_1;
wire pc_iu_repr_sl_thold_0;
wire pc_iu_bolt_sl_thold_1;
wire pc_iu_bolt_sl_thold_0;
wire pc_iu_sg_1;
wire pc_iu_sg_0;
wire force_t;

wire [0:scan_right] siv;
wire [0:scan_right] sov;

wire tiup;

wire [0:3] data_out_d;
wire [0:3] data_out_q;

wire ary_w_en;
wire [0:8] ary_w_addr;
wire [0:15] ary_w_sel;
wire [0:15] ary_w_data;

wire ary_r_en;
wire [0:8] ary_r_addr;
wire [0:15] ary_r_data;

wire [0:3] data_out;
wire [0:3] write_thru;

wire data_in_d;
wire data_in_q;
wire [0:3] w_act_d;
wire [0:3] w_act_q;
wire r_act_d;
wire r_act_q;
wire [0:8] w_addr_d;
wire [0:8] w_addr_q;
wire [0:8] r_addr_d;
wire [0:8] r_addr_q;

wire lat_wi_act;
wire lat_ri_act;
wire lat_ro_act;

wire reset_act;
wire [0:8] reset_w_addr_d;
wire [0:8] reset_w_addr_q;



assign tiup = 1'b1;

assign reset_act = pc_iu_init_reset;
assign reset_w_addr_d[0:8] = reset_w_addr_q[0:8] + 9'b000000001;

assign data_out0 = data_out_q[0];
assign data_out1 = data_out_q[1];
assign data_out2 = data_out_q[2];
assign data_out3 = data_out_q[3];

assign ary_w_en = reset_act | (|(w_act[0:3]) & (~((w_addr[0:8] == r_addr[0:8]) & r_act == 1'b1)));

assign ary_w_addr[0:8] = reset_act ? reset_w_addr_q[0:8] : w_addr[0:8];

assign ary_w_sel[0] = reset_act ? 1'b1 : w_act[0];
assign ary_w_sel[1] = reset_act ? 1'b1 : w_act[1];
assign ary_w_sel[2] = reset_act ? 1'b1 : w_act[2];
assign ary_w_sel[3] = reset_act ? 1'b1 : w_act[3];
assign ary_w_sel[4] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[5] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[6] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[7] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[8] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[9] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[10] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[11] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[12] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[13] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[14] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[15] = reset_act ? 1'b1 : 1'b0;

assign ary_w_data[0:15] = reset_act ? 16'b0000000000000000:
{data_in, data_in, data_in, data_in, 12'b000000000000};

assign ary_r_en = r_act;

assign ary_r_addr[0:8] = r_addr[0:8];

assign data_out[0:3] = ary_r_data[0:3];

//write through support

assign data_in_d = data_in;
assign w_act_d[0:3] = w_act[0:3];
assign r_act_d = r_act;
assign w_addr_d[0:8] = w_addr[0:8];
assign r_addr_d[0:8] = r_addr[0:8];

assign write_thru[0:3] = ((w_addr_q[0:8] == r_addr_q[0:8]) & r_act_q == 1'b1) ? w_act_q[0:3] :
4'b0000;

assign data_out_d[0] = (write_thru[0] == 1'b1) ? data_in_q :
data_out[0];
assign data_out_d[1] = (write_thru[1] == 1'b1) ? data_in_q :
data_out[1];
assign data_out_d[2] = (write_thru[2] == 1'b1) ? data_in_q :
data_out[2];
assign data_out_d[3] = (write_thru[3] == 1'b1) ? data_in_q :
data_out[3];

//latch acts
assign lat_wi_act = |(w_act[0:3]);
assign lat_ri_act = r_act;
assign lat_ro_act = r_act_q;

//-----------------------------------------------
// array
//-----------------------------------------------



tri_512x16_1r1w_1 bht0(
.gnd(gnd),
.vdd(vdd),
.vcs(vcs),
.nclk(nclk),

.rd_act(ary_r_en),
.wr_act(ary_w_en),

.lcb_d_mode_dc(g8t_d_mode),
.lcb_clkoff_dc_b(g8t_clkoff_b),
.lcb_mpw1_dc_b(g8t_mpw1_b),
.lcb_mpw2_dc_b(g8t_mpw2_b),
.lcb_delay_lclkr_dc(g8t_delay_lclkr),
.ccflush_dc(tc_ac_ccflush_dc),
.scan_dis_dc_b(tc_ac_scan_dis_dc_b),
.scan_diag_dc(scan_diag_dc),
.func_scan_in(siv[array_offset]),
.func_scan_out(sov[array_offset]),

.lcb_sg_0(pc_iu_sg_0),
.lcb_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
.lcb_time_sl_thold_0(pc_iu_time_sl_thold_0),
.lcb_abst_sl_thold_0(pc_iu_abst_sl_thold_0),
.lcb_ary_nsl_thold_0(pc_iu_ary_nsl_thold_0),
.lcb_repr_sl_thold_0(pc_iu_repr_sl_thold_0),
.time_scan_in(time_scan_in),
.time_scan_out(time_scan_out),
.abst_scan_in(abst_scan_in),
.abst_scan_out(abst_scan_out),
.repr_scan_in(repr_scan_in),
.repr_scan_out(repr_scan_out),

.abist_di(pc_iu_abist_di_0),
.abist_bw_odd(pc_iu_abist_g8t_bw_1),
.abist_bw_even(pc_iu_abist_g8t_bw_0),
.abist_wr_adr(pc_iu_abist_waddr_0),
.wr_abst_act(pc_iu_abist_g8t_wenb),
.abist_rd0_adr(pc_iu_abist_raddr_0),
.rd0_abst_act(pc_iu_abist_g8t1p_renb_0),
.tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
.abist_ena_1(pc_iu_abist_ena_dc),
.abist_g8t_rd0_comp_ena(pc_iu_abist_wl128_comp_ena),
.abist_raw_dc_b(pc_iu_abist_raw_dc_b),
.obs0_abist_cmp(pc_iu_abist_g8t_dcomp),

.lcb_bolt_sl_thold_0(pc_iu_bolt_sl_thold_0),
.pc_bo_enable_2(pc_iu_bo_enable_2),
.pc_bo_reset(pc_iu_bo_reset),
.pc_bo_unload(pc_iu_bo_unload),
.pc_bo_repair(pc_iu_bo_repair),
.pc_bo_shdata(pc_iu_bo_shdata),
.pc_bo_select(pc_iu_bo_select),
.bo_pc_failout(iu_pc_bo_fail),
.bo_pc_diagloop(iu_pc_bo_diagout),

.tri_lcb_mpw1_dc_b(mpw1_b),
.tri_lcb_mpw2_dc_b(mpw2_b),
.tri_lcb_delay_lclkr_dc(delay_lclkr),
.tri_lcb_clkoff_dc_b(clkoff_b),
.tri_lcb_act_dis_dc(act_dis),

.bw(ary_w_sel),
.wr_adr(ary_w_addr),
.rd_adr(ary_r_addr),
.di(ary_w_data),
.dout(ary_r_data)
);

//-----------------------------------------------
// latches
//-----------------------------------------------


tri_rlmlatch_p #(.INIT(0)) data_in_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[data_in_offset:data_in_offset]),
.scout(sov[data_in_offset:data_in_offset]),
.din(data_in_d),
.dout(data_in_q)
);


tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[w_act_offset:w_act_offset + 4 - 1]),
.scout(sov[w_act_offset:w_act_offset + 4 - 1]),
.din(w_act_d),
.dout(w_act_q)
);


tri_rlmlatch_p #(.INIT(0)) r_act_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[r_act_offset]),
.scout(sov[r_act_offset]),
.din(r_act_d),
.dout(r_act_q)
);


tri_rlmreg_p #(.WIDTH(9), .INIT(0)) w_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[w_addr_offset:w_addr_offset + 9 - 1]),
.scout(sov[w_addr_offset:w_addr_offset + 9 - 1]),
.din(w_addr_d),
.dout(w_addr_q)
);


tri_rlmreg_p #(.WIDTH(9), .INIT(0)) r_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_ri_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[r_addr_offset:r_addr_offset + 9 - 1]),
.scout(sov[r_addr_offset:r_addr_offset + 9 - 1]),
.din(r_addr_d),
.dout(r_addr_q)
);


tri_rlmreg_p #(.WIDTH(4), .INIT(0)) data_out_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_ro_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[data_out_offset:data_out_offset + 4 - 1]),
.scout(sov[data_out_offset:data_out_offset + 4 - 1]),
.din(data_out_d),
.dout(data_out_q)
);

tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(reset_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]),
.scout(sov[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]),
.din(reset_w_addr_d),
.dout(reset_w_addr_q)
);

//-----------------------------------------------
// pervasive
//-----------------------------------------------


tri_plat #(.WIDTH(7)) perv_2to1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}),
.q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1})
);


tri_plat #(.WIDTH(7)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}),
.q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0})
);


tri_lcbor perv_lcbor(
.clkoff_b(clkoff_b),
.thold(pc_iu_func_sl_thold_0),
.sg(pc_iu_sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b)
);

//-----------------------------------------------
// scan
//-----------------------------------------------

assign siv[0:scan_right] = {func_scan_in, sov[0:scan_right - 1]};
assign func_scan_out = sov[scan_right];


endmodule

@ -0,0 +1,67 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

// Description: XU Multiplier Top
//
//*****************************************************************************

`timescale 1 ns / 1 ns

module tri_bthmx(x, sneg, sx, sx2, right, left, q, vd, gd);

input x;
input sneg;
input sx;
input sx2;
input right;
output left;
output q;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout vd;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout gd;



wire center, xn, spos;

assign xn = ~x;
assign spos = ~sneg;

assign center = ~(( xn & spos ) |
( x & sneg ));

assign left = center; // output


assign q = ( center & sx ) |
( right & sx2 ) ;

endmodule

File diff suppressed because it is too large Load Diff

@ -0,0 +1,471 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

//********************************************************************
//*
//* TITLE: I-ERAT CAM Match Line Logic for Functional Model
//*
//* NAME: tri_cam_16x143_1r1w1c_matchline
//*
//*********************************************************************

module tri_cam_16x143_1r1w1c_matchline(
addr_in,
addr_enable,
comp_pgsize,
pgsize_enable,
entry_size,
entry_cmpmask,
entry_xbit,
entry_xbitmask,
entry_epn,
comp_class,
entry_class,
class_enable,
comp_extclass,
entry_extclass,
extclass_enable,
comp_state,
entry_hv,
entry_ds,
state_enable,
entry_thdid,
comp_thdid,
thdid_enable,
entry_pid,
comp_pid,
pid_enable,
entry_v,
comp_invalidate,
match
);
parameter HAVE_XBIT = 1;
parameter NUM_PGSIZES = 5;
parameter HAVE_CMPMASK = 1;
parameter CMPMASK_WIDTH = 4;

// @{default:nclk}@
input [0:51] addr_in;
input [0:1] addr_enable;
input [0:2] comp_pgsize;
input pgsize_enable;
input [0:2] entry_size;
input [0:CMPMASK_WIDTH-1] entry_cmpmask;
input entry_xbit;
input [0:CMPMASK_WIDTH-1] entry_xbitmask;
input [0:51] entry_epn;
input [0:1] comp_class;
input [0:1] entry_class;
input [0:2] class_enable;
input [0:1] comp_extclass;
input [0:1] entry_extclass;
input [0:1] extclass_enable;
input [0:1] comp_state;
input entry_hv;
input entry_ds;
input [0:1] state_enable;
input [0:3] entry_thdid;
input [0:3] comp_thdid;
input [0:1] thdid_enable;
input [0:7] entry_pid;
input [0:7] comp_pid;
input pid_enable;
input entry_v;
input comp_invalidate;

output match;

// tri_cam_16x143_1r1w1c_matchline

//----------------------------------------------------------------------
// Signals
//----------------------------------------------------------------------

wire [34:51] entry_epn_b;
wire function_50_51;
wire function_48_51;
wire function_46_51;
wire function_44_51;
wire function_40_51;
wire function_36_51;
wire function_34_51;
wire pgsize_eq_16K;
wire pgsize_eq_64K;
wire pgsize_eq_256K;
wire pgsize_eq_1M;
wire pgsize_eq_16M;
wire pgsize_eq_256M;
wire pgsize_eq_1G;
wire pgsize_gte_16K;
wire pgsize_gte_64K;
wire pgsize_gte_256K;
wire pgsize_gte_1M;
wire pgsize_gte_16M;
wire pgsize_gte_256M;
wire pgsize_gte_1G;
wire comp_or_34_35;
wire comp_or_34_39;
wire comp_or_36_39;
wire comp_or_40_43;
wire comp_or_44_45;
wire comp_or_44_47;
wire comp_or_46_47;
wire comp_or_48_49;
wire comp_or_48_51;
wire comp_or_50_51;
wire [0:72] match_line;
wire pgsize_match;
wire addr_match;
wire class_match;
wire extclass_match;
wire state_match;
wire thdid_match;
wire pid_match;
(* analysis_not_referenced="true" *)
wire [0:2] unused;

assign match_line[0:72] = (~({entry_epn[0:51], entry_size[0:2], entry_class[0:1], entry_extclass[0:1], entry_hv, entry_ds, entry_pid[0:7], entry_thdid[0:3]} ^
{addr_in[0:51], comp_pgsize[0:2], comp_class[0:1], comp_extclass[0:1], comp_state[0:1], comp_pid[0:7], comp_thdid[0:3]}));

generate
begin
if (NUM_PGSIZES == 8)
begin : numpgsz8
// tie off unused signals
assign comp_or_34_39 = 1'b0;
assign comp_or_44_47 = 1'b0;
assign comp_or_48_51 = 1'b0;
assign unused[0] = |{comp_or_34_39, comp_or_44_47, comp_or_48_51};

assign entry_epn_b[34:51] = (~(entry_epn[34:51]));

if (HAVE_CMPMASK == 0)
begin
assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & entry_size[2]);
assign pgsize_eq_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2])));
assign pgsize_eq_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]);
assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2])));
assign pgsize_eq_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]);
assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2])));
assign pgsize_eq_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]);

assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & entry_size[2]);
assign pgsize_gte_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_1G;
assign pgsize_gte_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_256M;
assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2]))) | pgsize_gte_16M;
assign pgsize_gte_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M;
assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_256K;
assign pgsize_gte_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_64K;

assign unused[1] = |{entry_cmpmask, entry_xbitmask};
end

if (HAVE_CMPMASK == 1)
begin
// size entry_cmpmask: 0123456
// 1GB 0000000
// 256MB 1000000
// 16MB 1100000
// 1MB 1110000
// 256KB 1111000
// 64KB 1111100
// 16KB 1111110
// 4KB 1111111
assign pgsize_gte_1G = (~entry_cmpmask[0]);
assign pgsize_gte_256M = (~entry_cmpmask[1]);
assign pgsize_gte_16M = (~entry_cmpmask[2]);
assign pgsize_gte_1M = (~entry_cmpmask[3]);
assign pgsize_gte_256K = (~entry_cmpmask[4]);
assign pgsize_gte_64K = (~entry_cmpmask[5]);
assign pgsize_gte_16K = (~entry_cmpmask[6]);

// size entry_xbitmask: 0123456
// 1GB 1000000
// 256MB 0100000
// 16MB 0010000
// 1MB 0001000
// 256KB 0000100
// 64KB 0000010
// 16KB 0000001
// 4KB 0000000
assign pgsize_eq_1G = entry_xbitmask[0];
assign pgsize_eq_256M = entry_xbitmask[1];
assign pgsize_eq_16M = entry_xbitmask[2];
assign pgsize_eq_1M = entry_xbitmask[3];
assign pgsize_eq_256K = entry_xbitmask[4];
assign pgsize_eq_64K = entry_xbitmask[5];
assign pgsize_eq_16K = entry_xbitmask[6];

assign unused[1] = 1'b0;
end

if (HAVE_XBIT == 0)
begin
assign function_34_51 = 1'b0;
assign function_36_51 = 1'b0;
assign function_40_51 = 1'b0;
assign function_44_51 = 1'b0;
assign function_46_51 = 1'b0;
assign function_48_51 = 1'b0;
assign function_50_51 = 1'b0;
assign unused[2] = |{function_34_51, function_36_51, function_40_51, function_44_51,
function_46_51, function_48_51, function_50_51, entry_xbit,
entry_epn_b, pgsize_eq_1G, pgsize_eq_256M, pgsize_eq_16M,
pgsize_eq_1M, pgsize_eq_256K, pgsize_eq_64K, pgsize_eq_16K};
end

if (HAVE_XBIT != 0)
begin
assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51]));
assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | (|(entry_epn_b[36:51] & addr_in[36:51]));
assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51]));
assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51]));
assign function_46_51 = (~(entry_xbit)) | (~(pgsize_eq_256K)) | (|(entry_epn_b[46:51] & addr_in[46:51]));
assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51]));
assign function_50_51 = (~(entry_xbit)) | (~(pgsize_eq_16K)) | (|(entry_epn_b[50:51] & addr_in[50:51]));
assign unused[2] = 1'b0;
end

assign comp_or_50_51 = (&(match_line[50:51])) | pgsize_gte_16K;
assign comp_or_48_49 = (&(match_line[48:49])) | pgsize_gte_64K;
assign comp_or_46_47 = (&(match_line[46:47])) | pgsize_gte_256K;
assign comp_or_44_45 = (&(match_line[44:45])) | pgsize_gte_1M;
assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M;
assign comp_or_36_39 = (&(match_line[36:39])) | pgsize_gte_256M;
assign comp_or_34_35 = (&(match_line[34:35])) | pgsize_gte_1G;

if (HAVE_XBIT == 0)
begin
assign addr_match = (comp_or_34_35 & // Ignore functions based on page size
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_45 &
comp_or_46_47 &
comp_or_48_49 &
comp_or_50_51 &
(&(match_line[31:33])) & // Regular compare largest page size
((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn
(~(addr_enable[0])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
end

if (HAVE_XBIT != 0)
begin
assign addr_match = (function_50_51 & // Exclusion functions
function_48_51 &
function_46_51 &
function_44_51 &
function_40_51 &
function_36_51 &
function_34_51 &
comp_or_34_35 & // Ignore functions based on page size
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_45 &
comp_or_46_47 &
comp_or_48_49 &
comp_or_50_51 &
(&(match_line[31:33])) & // Regular compare largest page size
(&(match_line[0:30]) | (~(addr_enable[1])))) | // ignored part of epn
(~(addr_enable[0])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
end
end // numpgsz8: NUM_PGSIZES = 8


if (NUM_PGSIZES == 5)
begin : numpgsz5
// tie off unused signals
assign function_50_51 = 1'b0;
assign function_46_51 = 1'b0;
assign function_36_51 = 1'b0;
assign pgsize_eq_16K = 1'b0;
assign pgsize_eq_256K = 1'b0;
assign pgsize_eq_256M = 1'b0;
assign pgsize_gte_16K = 1'b0;
assign pgsize_gte_256K = 1'b0;
assign pgsize_gte_256M = 1'b0;
assign comp_or_34_35 = 1'b0;
assign comp_or_36_39 = 1'b0;
assign comp_or_44_45 = 1'b0;
assign comp_or_46_47 = 1'b0;
assign comp_or_48_49 = 1'b0;
assign comp_or_50_51 = 1'b0;
assign unused[0] = |{function_50_51, function_46_51, function_36_51,
pgsize_eq_16K, pgsize_eq_256K, pgsize_eq_256M,
pgsize_gte_16K, pgsize_gte_256K, pgsize_gte_256M,
comp_or_34_35, comp_or_36_39, comp_or_44_45,
comp_or_46_47, comp_or_48_49, comp_or_50_51};

assign entry_epn_b[34:51] = (~(entry_epn[34:51]));

if (HAVE_CMPMASK == 0)
begin
// 110
assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2])));
// 111
assign pgsize_eq_16M = ( entry_size[0] & entry_size[1] & entry_size[2]);
// 101
assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]);
// 011
assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]);

assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2])));
assign pgsize_gte_16M = ( entry_size[0] & entry_size[1] & entry_size[2]) | pgsize_gte_1G;
assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_16M;
assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M;

assign unused[1] = |{entry_cmpmask, entry_xbitmask};
end

if (HAVE_CMPMASK == 1)
begin
// size entry_cmpmask: 0123
// 1GB 0000
// 16MB 1000
// 1MB 1100
// 64KB 1110
// 4KB 1111
assign pgsize_gte_1G = (~entry_cmpmask[0]);
assign pgsize_gte_16M = (~entry_cmpmask[1]);
assign pgsize_gte_1M = (~entry_cmpmask[2]);
assign pgsize_gte_64K = (~entry_cmpmask[3]);

// size entry_xbitmask: 0123
// 1GB 1000
// 16MB 0100
// 1MB 0010
// 64KB 0001
// 4KB 0000
assign pgsize_eq_1G = entry_xbitmask[0];
assign pgsize_eq_16M = entry_xbitmask[1];
assign pgsize_eq_1M = entry_xbitmask[2];
assign pgsize_eq_64K = entry_xbitmask[3];

assign unused[1] = 1'b0;
end

if (HAVE_XBIT == 0)
begin
assign function_34_51 = 1'b0;
assign function_40_51 = 1'b0;
assign function_44_51 = 1'b0;
assign function_48_51 = 1'b0;
assign unused[2] = |{function_34_51, function_40_51, function_44_51,
function_48_51, entry_xbit, entry_epn_b,
pgsize_eq_1G, pgsize_eq_16M, pgsize_eq_1M, pgsize_eq_64K};
end

if (HAVE_XBIT != 0)
begin
// 1G
assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51]));
// 16M
assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51]));
// 1M
assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51]));
// 64K
assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51]));
assign unused[2] = 1'b0;
end

assign comp_or_48_51 = (&(match_line[48:51])) | pgsize_gte_64K;
assign comp_or_44_47 = (&(match_line[44:47])) | pgsize_gte_1M;
assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M;
assign comp_or_34_39 = (&(match_line[34:39])) | pgsize_gte_1G;

if (HAVE_XBIT == 0)
begin
assign addr_match = (comp_or_34_39 & // Ignore functions based on page size
comp_or_40_43 &
comp_or_44_47 &
comp_or_48_51 &
(&(match_line[31:33])) & // Regular compare largest page size
((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn
(~(addr_enable[0])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
end

if (HAVE_XBIT != 0)
begin
assign addr_match = (function_48_51 &
function_44_51 &
function_40_51 &
function_34_51 &
comp_or_34_39 & // Ignore functions based on page size
comp_or_40_43 &
comp_or_44_47 &
comp_or_48_51 &
(&(match_line[31:33])) & // Regular compare largest page size
((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn
(~(addr_enable[0])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
end
end // numpgsz5: NUM_PGSIZES = 5


assign pgsize_match = (&(match_line[52:54])) | (~(pgsize_enable));

assign class_match = (match_line[55] | (~(class_enable[0]))) &
(match_line[56] | (~(class_enable[1]))) &
((&(match_line[55:56])) | (~(class_enable[2])) |
((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit

assign extclass_match = (match_line[57] | (~(extclass_enable[0]))) & // iprot bit
(match_line[58] | (~(extclass_enable[1]))); // pid_nz bit

assign state_match = (match_line[59] | (~(state_enable[0]))) &
(match_line[60] | (~(state_enable[1])));

assign thdid_match = (|(entry_thdid[0:3] & comp_thdid[0:3]) | (~(thdid_enable[0]))) &
(&(match_line[69:72]) | (~(thdid_enable[1])) |
((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit

assign pid_match = (&(match_line[61:68])) |
// entry_pid=0 ignores pid match for compares,
// but not for invalidates.
((~(entry_extclass[1])) & (~comp_invalidate)) | // pid_nz bit
(~(pid_enable));

assign match = addr_match & // Address compare
pgsize_match & // Size compare
class_match & // Class compare
extclass_match & // ExtClass compare
state_match & // State compare
thdid_match & // ThdID compare
pid_match & // PID compare
entry_v; // Valid
end
endgenerate
endmodule

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@ -0,0 +1,471 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

//********************************************************************
//*
//* TITLE: D-ERAT CAM Match Line Logic for Functional Model
//*
//* NAME: tri_cam_32x143_1r1w1c_matchline
//*
//*********************************************************************

module tri_cam_32x143_1r1w1c_matchline(
addr_in,
addr_enable,
comp_pgsize,
pgsize_enable,
entry_size,
entry_cmpmask,
entry_xbit,
entry_xbitmask,
entry_epn,
comp_class,
entry_class,
class_enable,
comp_extclass,
entry_extclass,
extclass_enable,
comp_state,
entry_hv,
entry_ds,
state_enable,
entry_thdid,
comp_thdid,
thdid_enable,
entry_pid,
comp_pid,
pid_enable,
entry_v,
comp_invalidate,
match
);
parameter HAVE_XBIT = 1;
parameter NUM_PGSIZES = 5;
parameter HAVE_CMPMASK = 1;
parameter CMPMASK_WIDTH = 4;

// @{default:nclk}@
input [0:51] addr_in;
input [0:1] addr_enable;
input [0:2] comp_pgsize;
input pgsize_enable;
input [0:2] entry_size;
input [0:CMPMASK_WIDTH-1] entry_cmpmask;
input entry_xbit;
input [0:CMPMASK_WIDTH-1] entry_xbitmask;
input [0:51] entry_epn;
input [0:1] comp_class;
input [0:1] entry_class;
input [0:2] class_enable;
input [0:1] comp_extclass;
input [0:1] entry_extclass;
input [0:1] extclass_enable;
input [0:1] comp_state;
input entry_hv;
input entry_ds;
input [0:1] state_enable;
input [0:3] entry_thdid;
input [0:3] comp_thdid;
input [0:1] thdid_enable;
input [0:7] entry_pid;
input [0:7] comp_pid;
input pid_enable;
input entry_v;
input comp_invalidate;

output match;

// tri_cam_32x143_1r1w1c_matchline

//----------------------------------------------------------------------
// Signals
//----------------------------------------------------------------------

wire [34:51] entry_epn_b;
wire function_50_51;
wire function_48_51;
wire function_46_51;
wire function_44_51;
wire function_40_51;
wire function_36_51;
wire function_34_51;
wire pgsize_eq_16K;
wire pgsize_eq_64K;
wire pgsize_eq_256K;
wire pgsize_eq_1M;
wire pgsize_eq_16M;
wire pgsize_eq_256M;
wire pgsize_eq_1G;
wire pgsize_gte_16K;
wire pgsize_gte_64K;
wire pgsize_gte_256K;
wire pgsize_gte_1M;
wire pgsize_gte_16M;
wire pgsize_gte_256M;
wire pgsize_gte_1G;
wire comp_or_34_35;
wire comp_or_34_39;
wire comp_or_36_39;
wire comp_or_40_43;
wire comp_or_44_45;
wire comp_or_44_47;
wire comp_or_46_47;
wire comp_or_48_49;
wire comp_or_48_51;
wire comp_or_50_51;
wire [0:72] match_line;
wire pgsize_match;
wire addr_match;
wire class_match;
wire extclass_match;
wire state_match;
wire thdid_match;
wire pid_match;
(* analysis_not_referenced="true" *)
wire [0:2] unused;

assign match_line[0:72] = (~({entry_epn[0:51], entry_size[0:2], entry_class[0:1], entry_extclass[0:1], entry_hv, entry_ds, entry_pid[0:7], entry_thdid[0:3]} ^
{addr_in[0:51], comp_pgsize[0:2], comp_class[0:1], comp_extclass[0:1], comp_state[0:1], comp_pid[0:7], comp_thdid[0:3]}));

generate
begin
if (NUM_PGSIZES == 8)
begin : numpgsz8
// tie off unused signals
assign comp_or_34_39 = 1'b0;
assign comp_or_44_47 = 1'b0;
assign comp_or_48_51 = 1'b0;
assign unused[0] = |{comp_or_34_39, comp_or_44_47, comp_or_48_51};

assign entry_epn_b[34:51] = (~(entry_epn[34:51]));

if (HAVE_CMPMASK == 0)
begin
assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & entry_size[2]);
assign pgsize_eq_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2])));
assign pgsize_eq_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]);
assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2])));
assign pgsize_eq_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]);
assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2])));
assign pgsize_eq_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]);

assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & entry_size[2]);
assign pgsize_gte_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_1G;
assign pgsize_gte_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_256M;
assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2]))) | pgsize_gte_16M;
assign pgsize_gte_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M;
assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_256K;
assign pgsize_gte_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_64K;

assign unused[1] = |{entry_cmpmask, entry_xbitmask};
end

if (HAVE_CMPMASK == 1)
begin
// size entry_cmpmask: 0123456
// 1GB 0000000
// 256MB 1000000
// 16MB 1100000
// 1MB 1110000
// 256KB 1111000
// 64KB 1111100
// 16KB 1111110
// 4KB 1111111
assign pgsize_gte_1G = (~entry_cmpmask[0]);
assign pgsize_gte_256M = (~entry_cmpmask[1]);
assign pgsize_gte_16M = (~entry_cmpmask[2]);
assign pgsize_gte_1M = (~entry_cmpmask[3]);
assign pgsize_gte_256K = (~entry_cmpmask[4]);
assign pgsize_gte_64K = (~entry_cmpmask[5]);
assign pgsize_gte_16K = (~entry_cmpmask[6]);

// size entry_xbitmask: 0123456
// 1GB 1000000
// 256MB 0100000
// 16MB 0010000
// 1MB 0001000
// 256KB 0000100
// 64KB 0000010
// 16KB 0000001
// 4KB 0000000
assign pgsize_eq_1G = entry_xbitmask[0];
assign pgsize_eq_256M = entry_xbitmask[1];
assign pgsize_eq_16M = entry_xbitmask[2];
assign pgsize_eq_1M = entry_xbitmask[3];
assign pgsize_eq_256K = entry_xbitmask[4];
assign pgsize_eq_64K = entry_xbitmask[5];
assign pgsize_eq_16K = entry_xbitmask[6];

assign unused[1] = 1'b0;
end

if (HAVE_XBIT == 0)
begin
assign function_34_51 = 1'b0;
assign function_36_51 = 1'b0;
assign function_40_51 = 1'b0;
assign function_44_51 = 1'b0;
assign function_46_51 = 1'b0;
assign function_48_51 = 1'b0;
assign function_50_51 = 1'b0;
assign unused[2] = |{function_34_51, function_36_51, function_40_51, function_44_51,
function_46_51, function_48_51, function_50_51, entry_xbit,
entry_epn_b, pgsize_eq_1G, pgsize_eq_256M, pgsize_eq_16M,
pgsize_eq_1M, pgsize_eq_256K, pgsize_eq_64K, pgsize_eq_16K};
end

if (HAVE_XBIT != 0)
begin
assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51]));
assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | (|(entry_epn_b[36:51] & addr_in[36:51]));
assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51]));
assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51]));
assign function_46_51 = (~(entry_xbit)) | (~(pgsize_eq_256K)) | (|(entry_epn_b[46:51] & addr_in[46:51]));
assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51]));
assign function_50_51 = (~(entry_xbit)) | (~(pgsize_eq_16K)) | (|(entry_epn_b[50:51] & addr_in[50:51]));
assign unused[2] = 1'b0;
end

assign comp_or_50_51 = (&(match_line[50:51])) | pgsize_gte_16K;
assign comp_or_48_49 = (&(match_line[48:49])) | pgsize_gte_64K;
assign comp_or_46_47 = (&(match_line[46:47])) | pgsize_gte_256K;
assign comp_or_44_45 = (&(match_line[44:45])) | pgsize_gte_1M;
assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M;
assign comp_or_36_39 = (&(match_line[36:39])) | pgsize_gte_256M;
assign comp_or_34_35 = (&(match_line[34:35])) | pgsize_gte_1G;

if (HAVE_XBIT == 0)
begin
assign addr_match = (comp_or_34_35 & // Ignore functions based on page size
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_45 &
comp_or_46_47 &
comp_or_48_49 &
comp_or_50_51 &
(&(match_line[31:33])) & // Regular compare largest page size
((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn
(~(addr_enable[0])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
end

if (HAVE_XBIT != 0)
begin
assign addr_match = (function_50_51 & // Exclusion functions
function_48_51 &
function_46_51 &
function_44_51 &
function_40_51 &
function_36_51 &
function_34_51 &
comp_or_34_35 & // Ignore functions based on page size
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_45 &
comp_or_46_47 &
comp_or_48_49 &
comp_or_50_51 &
(&(match_line[31:33])) & // Regular compare largest page size
(&(match_line[0:30]) | (~(addr_enable[1])))) | // ignored part of epn
(~(addr_enable[0])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
end
end // numpgsz8: NUM_PGSIZES = 8


if (NUM_PGSIZES == 5)
begin : numpgsz5
// tie off unused signals
assign function_50_51 = 1'b0;
assign function_46_51 = 1'b0;
assign function_36_51 = 1'b0;
assign pgsize_eq_16K = 1'b0;
assign pgsize_eq_256K = 1'b0;
assign pgsize_eq_256M = 1'b0;
assign pgsize_gte_16K = 1'b0;
assign pgsize_gte_256K = 1'b0;
assign pgsize_gte_256M = 1'b0;
assign comp_or_34_35 = 1'b0;
assign comp_or_36_39 = 1'b0;
assign comp_or_44_45 = 1'b0;
assign comp_or_46_47 = 1'b0;
assign comp_or_48_49 = 1'b0;
assign comp_or_50_51 = 1'b0;
assign unused[0] = |{function_50_51, function_46_51, function_36_51,
pgsize_eq_16K, pgsize_eq_256K, pgsize_eq_256M,
pgsize_gte_16K, pgsize_gte_256K, pgsize_gte_256M,
comp_or_34_35, comp_or_36_39, comp_or_44_45,
comp_or_46_47, comp_or_48_49, comp_or_50_51};

assign entry_epn_b[34:51] = (~(entry_epn[34:51]));

if (HAVE_CMPMASK == 0)
begin
// 110
assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2])));
// 111
assign pgsize_eq_16M = ( entry_size[0] & entry_size[1] & entry_size[2]);
// 101
assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]);
// 011
assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]);

assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2])));
assign pgsize_gte_16M = ( entry_size[0] & entry_size[1] & entry_size[2]) | pgsize_gte_1G;
assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_16M;
assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M;

assign unused[1] = |{entry_cmpmask, entry_xbitmask};
end

if (HAVE_CMPMASK == 1)
begin
// size entry_cmpmask: 0123
// 1GB 0000
// 16MB 1000
// 1MB 1100
// 64KB 1110
// 4KB 1111
assign pgsize_gte_1G = (~entry_cmpmask[0]);
assign pgsize_gte_16M = (~entry_cmpmask[1]);
assign pgsize_gte_1M = (~entry_cmpmask[2]);
assign pgsize_gte_64K = (~entry_cmpmask[3]);

// size entry_xbitmask: 0123
// 1GB 1000
// 16MB 0100
// 1MB 0010
// 64KB 0001
// 4KB 0000
assign pgsize_eq_1G = entry_xbitmask[0];
assign pgsize_eq_16M = entry_xbitmask[1];
assign pgsize_eq_1M = entry_xbitmask[2];
assign pgsize_eq_64K = entry_xbitmask[3];

assign unused[1] = 1'b0;
end

if (HAVE_XBIT == 0)
begin
assign function_34_51 = 1'b0;
assign function_40_51 = 1'b0;
assign function_44_51 = 1'b0;
assign function_48_51 = 1'b0;
assign unused[2] = |{function_34_51, function_40_51, function_44_51,
function_48_51, entry_xbit, entry_epn_b,
pgsize_eq_1G, pgsize_eq_16M, pgsize_eq_1M, pgsize_eq_64K};
end

if (HAVE_XBIT != 0)
begin
// 1G
assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51]));
// 16M
assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51]));
// 1M
assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51]));
// 64K
assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51]));
assign unused[2] = 1'b0;
end

assign comp_or_48_51 = (&(match_line[48:51])) | pgsize_gte_64K;
assign comp_or_44_47 = (&(match_line[44:47])) | pgsize_gte_1M;
assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M;
assign comp_or_34_39 = (&(match_line[34:39])) | pgsize_gte_1G;

if (HAVE_XBIT == 0)
begin
assign addr_match = (comp_or_34_39 & // Ignore functions based on page size
comp_or_40_43 &
comp_or_44_47 &
comp_or_48_51 &
(&(match_line[31:33])) & // Regular compare largest page size
((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn
(~(addr_enable[0])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
end

if (HAVE_XBIT != 0)
begin
assign addr_match = (function_48_51 &
function_44_51 &
function_40_51 &
function_34_51 &
comp_or_34_39 & // Ignore functions based on page size
comp_or_40_43 &
comp_or_44_47 &
comp_or_48_51 &
(&(match_line[31:33])) & // Regular compare largest page size
((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn
(~(addr_enable[0])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
end
end // numpgsz5: NUM_PGSIZES = 5


assign pgsize_match = (&(match_line[52:54])) | (~(pgsize_enable));

assign class_match = (match_line[55] | (~(class_enable[0]))) &
(match_line[56] | (~(class_enable[1]))) &
((&(match_line[55:56])) | (~(class_enable[2])) |
((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit

assign extclass_match = (match_line[57] | (~(extclass_enable[0]))) & // iprot bit
(match_line[58] | (~(extclass_enable[1]))); // pid_nz bit

assign state_match = (match_line[59] | (~(state_enable[0]))) &
(match_line[60] | (~(state_enable[1])));

assign thdid_match = (|(entry_thdid[0:3] & comp_thdid[0:3]) | (~(thdid_enable[0]))) &
(&(match_line[69:72]) | (~(thdid_enable[1])) |
((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit

assign pid_match = (&(match_line[61:68])) |
// entry_pid=0 ignores pid match for compares,
// but not for invalidates.
((~(entry_extclass[1])) & (~comp_invalidate)) | // pid_nz bit
(~(pid_enable));

assign match = addr_match & // Address compare
pgsize_match & // Size compare
class_match & // Class compare
extclass_match & // ExtClass compare
state_match & // State compare
thdid_match & // ThdID compare
pid_match & // PID compare
entry_v; // Valid
end
endgenerate
endmodule

@ -0,0 +1,55 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

//*****************************************************************************
// Description: XU Population Count
//
//*****************************************************************************

`timescale 1 ns / 1 ns

module tri_csa22(
a,
b,
car,
sum
);
input a;
input b;
output car;
output sum;

wire car_b;
wire sum_b;

assign car_b = (~(a & b));
assign sum_b = (~(car_b & (a | b))); // this is equiv to an xnor
assign car = (~car_b);
assign sum = (~sum_b);

endmodule

@ -0,0 +1,66 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

module tri_csa32(
a,
b,
c,
car,
sum,
vd,
gd
);
input a;
input b;
input c;
output car;
output sum;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout vd;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout gd;

wire carn1;
wire carn2;
wire carn3;

// assign sum = a ^ b ^ c;
tri_xor3 CSA42_XOR3_1(sum, a, b, c);

// assign car = (a & b) | (a & c) | (b & c);
tri_nand2 CSA42_NAND2_1(carn1, a, b);
tri_nand2 CSA42_NAND2_2(carn2, a, c);
tri_nand2 CSA42_NAND2_3(carn3, b, c);
tri_nand3 CSA42_NAND3_4(car, carn1, carn2, carn3);


endmodule

@ -0,0 +1,86 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

module tri_csa42(
a,
b,
c,
d,
ki,
ko,
car,
sum,
vd,
gd
);
input a;
input b;
input c;
input d;
input ki;
output ko;
output car;
output sum;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout vd;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout gd;

wire s1;

wire carn1;
wire carn2;
wire carn3;
wire kon1;
wire kon2;
wire kon3;

// assign s1 = b ^ c ^ d;
tri_xor3 CSA42_XOR3_1(s1,b,c,d);

// assign sum = s1 ^ a ^ ki;
tri_xor3 CSA42_XOR3_2(sum,s1,a,ki);

// assign car = (s1 & a) | (s1 & ki) | (a & ki);
tri_nand2 CSA42_NAND2_1(carn1,s1,a);
tri_nand2 CSA42_NAND2_2(carn2,s1,ki);
tri_nand2 CSA42_NAND2_3(carn3,a,ki);
tri_nand3 CSA42_NAND3_4(car,carn1,carn2,carn3);

// assign ko = (b & c) | (b & d) | (c & d);
tri_nand2 CSA42_NAND2_5(kon1,b,c);
tri_nand2 CSA42_NAND2_6(kon2,b,d);
tri_nand2 CSA42_NAND2_7(kon3,c,d);
tri_nand3 CSA42_NAND3_8(ko,kon1,kon2,kon3);


endmodule

@ -0,0 +1,159 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

//********************************************************************
//*
//* TITLE: Debug Mux Component (16:1 Debug Groups; 4:1 Trigger Groups)
//*
//* NAME: tri_debug_mux16.vhdl
//*
//********************************************************************

module tri_debug_mux16(
// vd,
// gd,
select_bits,
dbg_group0,
dbg_group1,
dbg_group2,
dbg_group3,
dbg_group4,
dbg_group5,
dbg_group6,
dbg_group7,
dbg_group8,
dbg_group9,
dbg_group10,
dbg_group11,
dbg_group12,
dbg_group13,
dbg_group14,
dbg_group15,
trace_data_in,
trace_data_out,
// Instruction Trace (HTM) Controls
coretrace_ctrls_in,
coretrace_ctrls_out
);

// Include model build parameters
parameter DBG_WIDTH = 32; // A2o=32; A2i=88

//=====================================================================
// Port Definitions
//=====================================================================

input [0:10] select_bits;
input [0:DBG_WIDTH-1] dbg_group0;
input [0:DBG_WIDTH-1] dbg_group1;
input [0:DBG_WIDTH-1] dbg_group2;
input [0:DBG_WIDTH-1] dbg_group3;
input [0:DBG_WIDTH-1] dbg_group4;
input [0:DBG_WIDTH-1] dbg_group5;
input [0:DBG_WIDTH-1] dbg_group6;
input [0:DBG_WIDTH-1] dbg_group7;
input [0:DBG_WIDTH-1] dbg_group8;
input [0:DBG_WIDTH-1] dbg_group9;
input [0:DBG_WIDTH-1] dbg_group10;
input [0:DBG_WIDTH-1] dbg_group11;
input [0:DBG_WIDTH-1] dbg_group12;
input [0:DBG_WIDTH-1] dbg_group13;
input [0:DBG_WIDTH-1] dbg_group14;
input [0:DBG_WIDTH-1] dbg_group15;
input [0:DBG_WIDTH-1] trace_data_in;
output [0:DBG_WIDTH-1] trace_data_out;

// Instruction Trace (HTM) Control Signals:
// 0 - ac_an_coretrace_first_valid
// 1 - ac_an_coretrace_valid
// 2:3 - ac_an_coretrace_type[0:1]
input [0:3] coretrace_ctrls_in;
output [0:3] coretrace_ctrls_out;

//=====================================================================
// Signal Declarations / Misc
//=====================================================================
parameter DBG_1FOURTH = DBG_WIDTH/4;
parameter DBG_2FOURTH = DBG_WIDTH/2;
parameter DBG_3FOURTH = 3 * DBG_WIDTH/4;

wire [0:DBG_WIDTH-1] debug_grp_selected;
wire [0:DBG_WIDTH-1] debug_grp_rotated;

// Don't reference unused inputs:
(* analysis_not_referenced="true" *)
wire unused;
assign unused = select_bits[4];

// Instruction Trace controls are passed-through:
assign coretrace_ctrls_out = coretrace_ctrls_in ;

//=====================================================================
// Mux Function
//=====================================================================
// Debug Mux
assign debug_grp_selected = (select_bits[0:3] == 4'b0000) ? dbg_group0 :
(select_bits[0:3] == 4'b0001) ? dbg_group1 :
(select_bits[0:3] == 4'b0010) ? dbg_group2 :
(select_bits[0:3] == 4'b0011) ? dbg_group3 :
(select_bits[0:3] == 4'b0100) ? dbg_group4 :
(select_bits[0:3] == 4'b0101) ? dbg_group5 :
(select_bits[0:3] == 4'b0110) ? dbg_group6 :
(select_bits[0:3] == 4'b0111) ? dbg_group7 :
(select_bits[0:3] == 4'b1000) ? dbg_group8 :
(select_bits[0:3] == 4'b1001) ? dbg_group9 :
(select_bits[0:3] == 4'b1010) ? dbg_group10 :
(select_bits[0:3] == 4'b1011) ? dbg_group11 :
(select_bits[0:3] == 4'b1100) ? dbg_group12 :
(select_bits[0:3] == 4'b1101) ? dbg_group13 :
(select_bits[0:3] == 4'b1110) ? dbg_group14 :
dbg_group15;

assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
(select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
(select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
debug_grp_selected[0:DBG_WIDTH - 1];


assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
debug_grp_rotated[0:DBG_1FOURTH - 1];

assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];

assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];

assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];


endmodule

@ -0,0 +1,204 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

//********************************************************************
//*
//* TITLE: Debug Mux Component (32:1 Debug Groups; 4:1 Trigger Groups)
//*
//* NAME: tri_debug_mux32.vhdl
//*
//********************************************************************


module tri_debug_mux32(
// vd,
// gd,
select_bits,
dbg_group0,
dbg_group1,
dbg_group2,
dbg_group3,
dbg_group4,
dbg_group5,
dbg_group6,
dbg_group7,
dbg_group8,
dbg_group9,
dbg_group10,
dbg_group11,
dbg_group12,
dbg_group13,
dbg_group14,
dbg_group15,
dbg_group16,
dbg_group17,
dbg_group18,
dbg_group19,
dbg_group20,
dbg_group21,
dbg_group22,
dbg_group23,
dbg_group24,
dbg_group25,
dbg_group26,
dbg_group27,
dbg_group28,
dbg_group29,
dbg_group30,
dbg_group31,
trace_data_in,
trace_data_out,

// Instruction Trace (HTM) Controls
coretrace_ctrls_in,
coretrace_ctrls_out
);

// Include model build parameters
parameter DBG_WIDTH = 32; // A2o=32; A2i=88

//=====================================================================
// Port Definitions
//=====================================================================

input [0:10] select_bits;
input [0:DBG_WIDTH-1] dbg_group0;
input [0:DBG_WIDTH-1] dbg_group1;
input [0:DBG_WIDTH-1] dbg_group2;
input [0:DBG_WIDTH-1] dbg_group3;
input [0:DBG_WIDTH-1] dbg_group4;
input [0:DBG_WIDTH-1] dbg_group5;
input [0:DBG_WIDTH-1] dbg_group6;
input [0:DBG_WIDTH-1] dbg_group7;
input [0:DBG_WIDTH-1] dbg_group8;
input [0:DBG_WIDTH-1] dbg_group9;
input [0:DBG_WIDTH-1] dbg_group10;
input [0:DBG_WIDTH-1] dbg_group11;
input [0:DBG_WIDTH-1] dbg_group12;
input [0:DBG_WIDTH-1] dbg_group13;
input [0:DBG_WIDTH-1] dbg_group14;
input [0:DBG_WIDTH-1] dbg_group15;
input [0:DBG_WIDTH-1] dbg_group16;
input [0:DBG_WIDTH-1] dbg_group17;
input [0:DBG_WIDTH-1] dbg_group18;
input [0:DBG_WIDTH-1] dbg_group19;
input [0:DBG_WIDTH-1] dbg_group20;
input [0:DBG_WIDTH-1] dbg_group21;
input [0:DBG_WIDTH-1] dbg_group22;
input [0:DBG_WIDTH-1] dbg_group23;
input [0:DBG_WIDTH-1] dbg_group24;
input [0:DBG_WIDTH-1] dbg_group25;
input [0:DBG_WIDTH-1] dbg_group26;
input [0:DBG_WIDTH-1] dbg_group27;
input [0:DBG_WIDTH-1] dbg_group28;
input [0:DBG_WIDTH-1] dbg_group29;
input [0:DBG_WIDTH-1] dbg_group30;
input [0:DBG_WIDTH-1] dbg_group31;
input [0:DBG_WIDTH-1] trace_data_in;
output [0:DBG_WIDTH-1] trace_data_out;

// Instruction Trace (HTM) Control Signals:
// 0 - ac_an_coretrace_first_valid
// 1 - ac_an_coretrace_valid
// 2:3 - ac_an_coretrace_type[0:1]
input [0:3] coretrace_ctrls_in;
output [0:3] coretrace_ctrls_out;

//=====================================================================
// Signal Declarations / Misc
//=====================================================================
parameter DBG_1FOURTH = DBG_WIDTH/4;
parameter DBG_2FOURTH = DBG_WIDTH/2;
parameter DBG_3FOURTH = 3 * DBG_WIDTH/4;

wire [0:DBG_WIDTH-1] debug_grp_selected;
wire [0:DBG_WIDTH-1] debug_grp_rotated;

// Instruction Trace controls are passed-through:
assign coretrace_ctrls_out = coretrace_ctrls_in ;

//=====================================================================
// Mux Function
//=====================================================================
// Debug Mux
assign debug_grp_selected = (select_bits[0:4] == 5'b00000) ? dbg_group0 :
(select_bits[0:4] == 5'b00001) ? dbg_group1 :
(select_bits[0:4] == 5'b00010) ? dbg_group2 :
(select_bits[0:4] == 5'b00011) ? dbg_group3 :
(select_bits[0:4] == 5'b00100) ? dbg_group4 :
(select_bits[0:4] == 5'b00101) ? dbg_group5 :
(select_bits[0:4] == 5'b00110) ? dbg_group6 :
(select_bits[0:4] == 5'b00111) ? dbg_group7 :
(select_bits[0:4] == 5'b01000) ? dbg_group8 :
(select_bits[0:4] == 5'b01001) ? dbg_group9 :
(select_bits[0:4] == 5'b01010) ? dbg_group10 :
(select_bits[0:4] == 5'b01011) ? dbg_group11 :
(select_bits[0:4] == 5'b01100) ? dbg_group12 :
(select_bits[0:4] == 5'b01101) ? dbg_group13 :
(select_bits[0:4] == 5'b01110) ? dbg_group14 :
(select_bits[0:4] == 5'b01111) ? dbg_group15 :
(select_bits[0:4] == 5'b10000) ? dbg_group16 :
(select_bits[0:4] == 5'b10001) ? dbg_group17 :
(select_bits[0:4] == 5'b10010) ? dbg_group18 :
(select_bits[0:4] == 5'b10011) ? dbg_group19 :
(select_bits[0:4] == 5'b10100) ? dbg_group20 :
(select_bits[0:4] == 5'b10101) ? dbg_group21 :
(select_bits[0:4] == 5'b10110) ? dbg_group22 :
(select_bits[0:4] == 5'b10111) ? dbg_group23 :
(select_bits[0:4] == 5'b11000) ? dbg_group24 :
(select_bits[0:4] == 5'b11001) ? dbg_group25 :
(select_bits[0:4] == 5'b11010) ? dbg_group26 :
(select_bits[0:4] == 5'b11011) ? dbg_group27 :
(select_bits[0:4] == 5'b11100) ? dbg_group28 :
(select_bits[0:4] == 5'b11101) ? dbg_group29 :
(select_bits[0:4] == 5'b11110) ? dbg_group30 :
dbg_group31;

assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
(select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
(select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
debug_grp_selected[0:DBG_WIDTH - 1];


assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
debug_grp_rotated[0:DBG_1FOURTH - 1];

assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];

assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];

assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];


endmodule

@ -0,0 +1,124 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

//********************************************************************
//*
//* TITLE: Debug Mux Component (4:1 Debug Groups; 4:1 Trigger Groups)
//*
//* NAME: tri_debug_mux4.vhdl
//*
//********************************************************************


module tri_debug_mux4(
// vd,
// gd,
select_bits,
dbg_group0,
dbg_group1,
dbg_group2,
dbg_group3,
trace_data_in,
trace_data_out,

// Instruction Trace (HTM) Controls
coretrace_ctrls_in,
coretrace_ctrls_out
);

// Include model build parameters
parameter DBG_WIDTH = 32; // A2o=32; A2i=88

//=====================================================================
// Port Definitions
//=====================================================================

input [0:10] select_bits;
input [0:DBG_WIDTH-1] dbg_group0;
input [0:DBG_WIDTH-1] dbg_group1;
input [0:DBG_WIDTH-1] dbg_group2;
input [0:DBG_WIDTH-1] dbg_group3;
input [0:DBG_WIDTH-1] trace_data_in;
output [0:DBG_WIDTH-1] trace_data_out;

// Instruction Trace (HTM) Control Signals:
// 0 - ac_an_coretrace_first_valid
// 1 - ac_an_coretrace_valid
// 2:3 - ac_an_coretrace_type[0:1]
input [0:3] coretrace_ctrls_in;
output [0:3] coretrace_ctrls_out;

//=====================================================================
// Signal Declarations / Misc
//=====================================================================
parameter DBG_1FOURTH = DBG_WIDTH/4;
parameter DBG_2FOURTH = DBG_WIDTH/2;
parameter DBG_3FOURTH = 3 * DBG_WIDTH/4;

wire [0:DBG_WIDTH-1] debug_grp_selected;
wire [0:DBG_WIDTH-1] debug_grp_rotated;

// Don't reference unused inputs:
(* analysis_not_referenced="true" *)
wire unused;
assign unused = (|select_bits[2:4]) ;

// Instruction Trace controls are passed-through:
assign coretrace_ctrls_out = coretrace_ctrls_in ;

//=====================================================================
// Mux Function
//=====================================================================
// Debug Mux
assign debug_grp_selected = (select_bits[0:1] == 2'b00) ? dbg_group0 :
(select_bits[0:1] == 2'b01) ? dbg_group1 :
(select_bits[0:1] == 2'b10) ? dbg_group2 :
dbg_group3;

assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
(select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
(select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
debug_grp_selected[0:DBG_WIDTH - 1];


assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
debug_grp_rotated[0:DBG_1FOURTH - 1];

assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];

assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];

assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];


endmodule

@ -0,0 +1,134 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

//********************************************************************
//*
//* TITLE: Debug Mux Component (8:1 Debug Groups; 4:1 Trigger Groups)
//*
//* NAME: tri_debug_mux8.vhdl
//*
//********************************************************************

module tri_debug_mux8(
// vd,
// gd,
select_bits,
dbg_group0,
dbg_group1,
dbg_group2,
dbg_group3,
dbg_group4,
dbg_group5,
dbg_group6,
dbg_group7,
trace_data_in,
trace_data_out,
// Instruction Trace (HTM) Controls
coretrace_ctrls_in,
coretrace_ctrls_out
);

// Include model build parameters
parameter DBG_WIDTH = 32; // A2o=32; A2i=88

//=====================================================================
// Port Definitions
//=====================================================================

input [0:10] select_bits;
input [0:DBG_WIDTH-1] dbg_group0;
input [0:DBG_WIDTH-1] dbg_group1;
input [0:DBG_WIDTH-1] dbg_group2;
input [0:DBG_WIDTH-1] dbg_group3;
input [0:DBG_WIDTH-1] dbg_group4;
input [0:DBG_WIDTH-1] dbg_group5;
input [0:DBG_WIDTH-1] dbg_group6;
input [0:DBG_WIDTH-1] dbg_group7;
input [0:DBG_WIDTH-1] trace_data_in;
output [0:DBG_WIDTH-1] trace_data_out;

// Instruction Trace (HTM) Control Signals:
// 0 - ac_an_coretrace_first_valid
// 1 - ac_an_coretrace_valid
// 2:3 - ac_an_coretrace_type[0:1]
input [0:3] coretrace_ctrls_in;
output [0:3] coretrace_ctrls_out;

//=====================================================================
// Signal Declarations / Misc
//=====================================================================
parameter DBG_1FOURTH = DBG_WIDTH/4;
parameter DBG_2FOURTH = DBG_WIDTH/2;
parameter DBG_3FOURTH = 3 * DBG_WIDTH/4;

wire [0:DBG_WIDTH-1] debug_grp_selected;
wire [0:DBG_WIDTH-1] debug_grp_rotated;

// Don't reference unused inputs:
(* analysis_not_referenced="true" *)
wire unused;
assign unused = (|select_bits[3:4]) ;

// Instruction Trace controls are passed-through:
assign coretrace_ctrls_out = coretrace_ctrls_in ;

//=====================================================================
// Mux Function
//=====================================================================
// Debug Mux

assign debug_grp_selected = (select_bits[0:2] == 3'b000) ? dbg_group0 :
(select_bits[0:2] == 3'b001) ? dbg_group1 :
(select_bits[0:2] == 3'b010) ? dbg_group2 :
(select_bits[0:2] == 3'b011) ? dbg_group3 :
(select_bits[0:2] == 3'b100) ? dbg_group4 :
(select_bits[0:2] == 3'b101) ? dbg_group5 :
(select_bits[0:2] == 3'b110) ? dbg_group6 :
dbg_group7;

assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
(select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
(select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
debug_grp_selected[0:DBG_WIDTH - 1];


assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
debug_grp_rotated[0:DBG_1FOURTH - 1];

assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];

assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];

assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];

endmodule

@ -0,0 +1,57 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_direct_err_rpt.v
// *! DESCRIPTION : Error Reporting Component
// *!****************************************************************

module tri_direct_err_rpt(
vd,
gd,
err_in,
err_out
);
parameter WIDTH = 1; // use to bundle error reporting checkers of the same exact type
inout vd;
inout gd;

input [0:WIDTH-1] err_in;
output [0:WIDTH-1] err_out;

// tri_direct_err_rpt

(* analysis_not_referenced="true" *)
wire unused;

assign unused = vd | gd;

assign err_out = err_in;
endmodule

@ -0,0 +1,284 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// Description: XU ECC Check Macro
//
//*****************************************************************************

module tri_eccchk(
din,
encorr,
nsyn,
corrd,
sbe,
ue
);

parameter REGSIZE = 64;

input [0:REGSIZE-1] din;
input encorr;
input [0:8-(64/REGSIZE)] nsyn;
output [0:REGSIZE-1] corrd;
output sbe;
output ue;

generate // syndrome bits inverted
if (REGSIZE == 64)
begin : ecc64
wire [0:7] syn;
wire [0:71] DcdD; // decode data bits
wire synzero;
wire sbe_int;
wire [0:3] A0to1;
wire [0:3] A2to3;
wire [0:3] A4to5;
wire [0:2] A6to7;

// ====================================================================
// 64 Data Bits, 8 Check bits
// Single bit error correction, Double bit error detection
// ====================================================================
// ECC Matrix Description
// ====================================================================
// Syn 0 111011010011101001100101101101001100101101001011001101001110100110000000
// Syn 1 110110101011010101010101011010101010101010101010101010101101010101000000
// Syn 2 101101100110110011001100110110011001100110011001100110011011001100100000
// Syn 3 011100011110001111000011110001111000011110000111100001111000111100010000
// Syn 4 000011111110000000111111110000000111111110000000011111111000000000001000
// Syn 5 000000000001111111111111110000000000000001111111111111111000000000000100
// Syn 6 000000000000000000000000001111111111111111111111111111111000000000000010
// Syn 7 000000000000000000000000000000000000000000000000000000000111111100000001

assign syn = (~nsyn[0:7]);

assign A0to1[0] = (~(nsyn[0] & nsyn[1] & encorr));
assign A0to1[1] = (~(nsyn[0] & syn[1] & encorr));
assign A0to1[2] = (~( syn[0] & nsyn[1] & encorr));
assign A0to1[3] = (~( syn[0] & syn[1] & encorr));

assign A2to3[0] = (~(nsyn[2] & nsyn[3]));
assign A2to3[1] = (~(nsyn[2] & syn[3]));
assign A2to3[2] = (~( syn[2] & nsyn[3]));
assign A2to3[3] = (~( syn[2] & syn[3]));

assign A4to5[0] = (~(nsyn[4] & nsyn[5]));
assign A4to5[1] = (~(nsyn[4] & syn[5]));
assign A4to5[2] = (~( syn[4] & nsyn[5]));
assign A4to5[3] = (~( syn[4] & syn[5]));

assign A6to7[0] = (~(nsyn[6] & nsyn[7]));
assign A6to7[1] = (~(nsyn[6] & syn[7]));
assign A6to7[2] = (~( syn[6] & nsyn[7]));
//assign A6to7[3] = (~( syn[6] & syn[7]));

assign DcdD[0] = (~(A0to1[3] | A2to3[2] | A4to5[0] | A6to7[0])); // 11 10 00 00
assign DcdD[1] = (~(A0to1[3] | A2to3[1] | A4to5[0] | A6to7[0])); // 11 01 00 00
assign DcdD[2] = (~(A0to1[2] | A2to3[3] | A4to5[0] | A6to7[0])); // 10 11 00 00
assign DcdD[3] = (~(A0to1[1] | A2to3[3] | A4to5[0] | A6to7[0])); // 01 11 00 00
assign DcdD[4] = (~(A0to1[3] | A2to3[0] | A4to5[2] | A6to7[0])); // 11 00 10 00
assign DcdD[5] = (~(A0to1[2] | A2to3[2] | A4to5[2] | A6to7[0])); // 10 10 10 00
assign DcdD[6] = (~(A0to1[1] | A2to3[2] | A4to5[2] | A6to7[0])); // 01 10 10 00
assign DcdD[7] = (~(A0to1[2] | A2to3[1] | A4to5[2] | A6to7[0])); // 10 01 10 00
assign DcdD[8] = (~(A0to1[1] | A2to3[1] | A4to5[2] | A6to7[0])); // 01 01 10 00
assign DcdD[9] = (~(A0to1[0] | A2to3[3] | A4to5[2] | A6to7[0])); // 00 11 10 00
assign DcdD[10] = (~(A0to1[3] | A2to3[3] | A4to5[2] | A6to7[0])); // 11 11 10 00
assign DcdD[11] = (~(A0to1[3] | A2to3[0] | A4to5[1] | A6to7[0])); // 11 00 01 00
assign DcdD[12] = (~(A0to1[2] | A2to3[2] | A4to5[1] | A6to7[0])); // 10 10 01 00
assign DcdD[13] = (~(A0to1[1] | A2to3[2] | A4to5[1] | A6to7[0])); // 01 10 01 00
assign DcdD[14] = (~(A0to1[2] | A2to3[1] | A4to5[1] | A6to7[0])); // 10 01 01 00
assign DcdD[15] = (~(A0to1[1] | A2to3[1] | A4to5[1] | A6to7[0])); // 01 01 01 00
assign DcdD[16] = (~(A0to1[0] | A2to3[3] | A4to5[1] | A6to7[0])); // 00 11 01 00
assign DcdD[17] = (~(A0to1[3] | A2to3[3] | A4to5[1] | A6to7[0])); // 11 11 01 00
assign DcdD[18] = (~(A0to1[2] | A2to3[0] | A4to5[3] | A6to7[0])); // 10 00 11 00
assign DcdD[19] = (~(A0to1[1] | A2to3[0] | A4to5[3] | A6to7[0])); // 01 00 11 00
assign DcdD[20] = (~(A0to1[0] | A2to3[2] | A4to5[3] | A6to7[0])); // 00 10 11 00
assign DcdD[21] = (~(A0to1[3] | A2to3[2] | A4to5[3] | A6to7[0])); // 11 10 11 00
assign DcdD[22] = (~(A0to1[0] | A2to3[1] | A4to5[3] | A6to7[0])); // 00 01 11 00
assign DcdD[23] = (~(A0to1[3] | A2to3[1] | A4to5[3] | A6to7[0])); // 11 01 11 00
assign DcdD[24] = (~(A0to1[2] | A2to3[3] | A4to5[3] | A6to7[0])); // 10 11 11 00
assign DcdD[25] = (~(A0to1[1] | A2to3[3] | A4to5[3] | A6to7[0])); // 01 11 11 00
assign DcdD[26] = (~(A0to1[3] | A2to3[0] | A4to5[0] | A6to7[2])); // 11 00 00 10
assign DcdD[27] = (~(A0to1[2] | A2to3[2] | A4to5[0] | A6to7[2])); // 10 10 00 10
assign DcdD[28] = (~(A0to1[1] | A2to3[2] | A4to5[0] | A6to7[2])); // 01 10 00 10
assign DcdD[29] = (~(A0to1[2] | A2to3[1] | A4to5[0] | A6to7[2])); // 10 01 00 10
assign DcdD[30] = (~(A0to1[1] | A2to3[1] | A4to5[0] | A6to7[2])); // 01 01 00 10
assign DcdD[31] = (~(A0to1[0] | A2to3[3] | A4to5[0] | A6to7[2])); // 00 11 00 10
assign DcdD[32] = (~(A0to1[3] | A2to3[3] | A4to5[0] | A6to7[2])); // 11 11 00 10
assign DcdD[33] = (~(A0to1[2] | A2to3[0] | A4to5[2] | A6to7[2])); // 10 00 10 10
assign DcdD[34] = (~(A0to1[1] | A2to3[0] | A4to5[2] | A6to7[2])); // 01 00 10 10
assign DcdD[35] = (~(A0to1[0] | A2to3[2] | A4to5[2] | A6to7[2])); // 00 10 10 10
assign DcdD[36] = (~(A0to1[3] | A2to3[2] | A4to5[2] | A6to7[2])); // 11 10 10 10
assign DcdD[37] = (~(A0to1[0] | A2to3[1] | A4to5[2] | A6to7[2])); // 00 01 10 10
assign DcdD[38] = (~(A0to1[3] | A2to3[1] | A4to5[2] | A6to7[2])); // 11 01 10 10
assign DcdD[39] = (~(A0to1[2] | A2to3[3] | A4to5[2] | A6to7[2])); // 10 11 10 10
assign DcdD[40] = (~(A0to1[1] | A2to3[3] | A4to5[2] | A6to7[2])); // 01 11 10 10
assign DcdD[41] = (~(A0to1[2] | A2to3[0] | A4to5[1] | A6to7[2])); // 10 00 01 10
assign DcdD[42] = (~(A0to1[1] | A2to3[0] | A4to5[1] | A6to7[2])); // 01 00 01 10
assign DcdD[43] = (~(A0to1[0] | A2to3[2] | A4to5[1] | A6to7[2])); // 00 10 01 10
assign DcdD[44] = (~(A0to1[3] | A2to3[2] | A4to5[1] | A6to7[2])); // 11 10 01 10
assign DcdD[45] = (~(A0to1[0] | A2to3[1] | A4to5[1] | A6to7[2])); // 00 01 01 10
assign DcdD[46] = (~(A0to1[3] | A2to3[1] | A4to5[1] | A6to7[2])); // 11 01 01 10
assign DcdD[47] = (~(A0to1[2] | A2to3[3] | A4to5[1] | A6to7[2])); // 10 11 01 10
assign DcdD[48] = (~(A0to1[1] | A2to3[3] | A4to5[1] | A6to7[2])); // 01 11 01 10
assign DcdD[49] = (~(A0to1[0] | A2to3[0] | A4to5[3] | A6to7[2])); // 00 00 11 10
assign DcdD[50] = (~(A0to1[3] | A2to3[0] | A4to5[3] | A6to7[2])); // 11 00 11 10
assign DcdD[51] = (~(A0to1[2] | A2to3[2] | A4to5[3] | A6to7[2])); // 10 10 11 10
assign DcdD[52] = (~(A0to1[1] | A2to3[2] | A4to5[3] | A6to7[2])); // 01 10 11 10
assign DcdD[53] = (~(A0to1[2] | A2to3[1] | A4to5[3] | A6to7[2])); // 10 01 11 10
assign DcdD[54] = (~(A0to1[1] | A2to3[1] | A4to5[3] | A6to7[2])); // 01 01 11 10
assign DcdD[55] = (~(A0to1[0] | A2to3[3] | A4to5[3] | A6to7[2])); // 00 11 11 10
assign DcdD[56] = (~(A0to1[3] | A2to3[3] | A4to5[3] | A6to7[2])); // 11 11 11 10
assign DcdD[57] = (~(A0to1[3] | A2to3[0] | A4to5[0] | A6to7[1])); // 11 00 00 01
assign DcdD[58] = (~(A0to1[2] | A2to3[2] | A4to5[0] | A6to7[1])); // 10 10 00 01
assign DcdD[59] = (~(A0to1[1] | A2to3[2] | A4to5[0] | A6to7[1])); // 01 10 00 01
assign DcdD[60] = (~(A0to1[2] | A2to3[1] | A4to5[0] | A6to7[1])); // 10 01 00 01
assign DcdD[61] = (~(A0to1[1] | A2to3[1] | A4to5[0] | A6to7[1])); // 01 01 00 01
assign DcdD[62] = (~(A0to1[0] | A2to3[3] | A4to5[0] | A6to7[1])); // 00 11 00 01
assign DcdD[63] = (~(A0to1[3] | A2to3[3] | A4to5[0] | A6to7[1])); // 11 11 00 01
assign DcdD[64] = (~(A0to1[2] | A2to3[0] | A4to5[0] | A6to7[0])); // 10 00 00 00
assign DcdD[65] = (~(A0to1[1] | A2to3[0] | A4to5[0] | A6to7[0])); // 01 00 00 00
assign DcdD[66] = (~(A0to1[0] | A2to3[2] | A4to5[0] | A6to7[0])); // 00 10 00 00
assign DcdD[67] = (~(A0to1[0] | A2to3[1] | A4to5[0] | A6to7[0])); // 00 01 00 00
assign DcdD[68] = (~(A0to1[0] | A2to3[0] | A4to5[2] | A6to7[0])); // 00 00 10 00
assign DcdD[69] = (~(A0to1[0] | A2to3[0] | A4to5[1] | A6to7[0])); // 00 00 01 00
assign DcdD[70] = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[2])); // 00 00 00 10
assign DcdD[71] = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[1])); // 00 00 00 01
assign synzero = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[0])); // 00 00 00 00

assign corrd[0:63] = din[0:63] ^ DcdD[0:63];

assign sbe_int = (DcdD[0:71] != {72{1'b0}}) ? 1'b1 :
1'b0;
assign sbe = sbe_int;
assign ue = (~sbe_int) & (~synzero) & encorr;
end
endgenerate

generate // syndrome bits inverted
if (REGSIZE == 32)
begin : ecc32
wire [0:6] syn;
wire [0:38] DcdD; // decode data bits
wire synzero;
wire sbe_int;
wire [0:3] A0to1;
wire [0:3] A2to3;
wire [0:7] A4to6;

// ====================================================================
// 32 Data Bits, 7 Check bits
// Single bit error correction, Double bit error detection
// ====================================================================
// ECC Matrix Description
// ====================================================================
// Syn 0 111011010011101001100101101101001000000
// Syn 1 110110101011010101010101011010100100000
// Syn 2 101101100110110011001100110110010010000
// Syn 3 011100011110001111000011110001110001000
// Syn 4 000011111110000000111111110000000000100
// Syn 5 000000000001111111111111110000000000010
// Syn 6 000000000000000000000000001111110000001

assign syn = (~nsyn[0:6]);

assign A0to1[0] = (~(nsyn[0] & nsyn[1] & encorr));
assign A0to1[1] = (~(nsyn[0] & syn[1] & encorr));
assign A0to1[2] = (~( syn[0] & nsyn[1] & encorr));
assign A0to1[3] = (~( syn[0] & syn[1] & encorr));

assign A2to3[0] = (~(nsyn[2] & nsyn[3]));
assign A2to3[1] = (~(nsyn[2] & syn[3]));
assign A2to3[2] = (~( syn[2] & nsyn[3]));
assign A2to3[3] = (~( syn[2] & syn[3]));

assign A4to6[0] = (~(nsyn[4] & nsyn[5] & nsyn[6]));
assign A4to6[1] = (~(nsyn[4] & nsyn[5] & syn[6]));
assign A4to6[2] = (~(nsyn[4] & syn[5] & nsyn[6]));
assign A4to6[3] = (~(nsyn[4] & syn[5] & syn[6]));
assign A4to6[4] = (~( syn[4] & nsyn[5] & nsyn[6]));
assign A4to6[5] = (~( syn[4] & nsyn[5] & syn[6]));
assign A4to6[6] = (~( syn[4] & syn[5] & nsyn[6]));
assign A4to6[7] = (~( syn[4] & syn[5] & syn[6]));

assign DcdD[0] = (~(A0to1[3] | A2to3[2] | A4to6[0])); // 11 10 000
assign DcdD[1] = (~(A0to1[3] | A2to3[1] | A4to6[0])); // 11 01 000
assign DcdD[2] = (~(A0to1[2] | A2to3[3] | A4to6[0])); // 10 11 000
assign DcdD[3] = (~(A0to1[1] | A2to3[3] | A4to6[0])); // 01 11 000
assign DcdD[4] = (~(A0to1[3] | A2to3[0] | A4to6[4])); // 11 00 100
assign DcdD[5] = (~(A0to1[2] | A2to3[2] | A4to6[4])); // 10 10 100
assign DcdD[6] = (~(A0to1[1] | A2to3[2] | A4to6[4])); // 01 10 100
assign DcdD[7] = (~(A0to1[2] | A2to3[1] | A4to6[4])); // 10 01 100
assign DcdD[8] = (~(A0to1[1] | A2to3[1] | A4to6[4])); // 01 01 100
assign DcdD[9] = (~(A0to1[0] | A2to3[3] | A4to6[4])); // 00 11 100
assign DcdD[10] = (~(A0to1[3] | A2to3[3] | A4to6[4])); // 11 11 100
assign DcdD[11] = (~(A0to1[3] | A2to3[0] | A4to6[2])); // 11 00 010
assign DcdD[12] = (~(A0to1[2] | A2to3[2] | A4to6[2])); // 10 10 010
assign DcdD[13] = (~(A0to1[1] | A2to3[2] | A4to6[2])); // 01 10 010
assign DcdD[14] = (~(A0to1[2] | A2to3[1] | A4to6[2])); // 10 01 010
assign DcdD[15] = (~(A0to1[1] | A2to3[1] | A4to6[2])); // 01 01 010
assign DcdD[16] = (~(A0to1[0] | A2to3[3] | A4to6[2])); // 00 11 010
assign DcdD[17] = (~(A0to1[3] | A2to3[3] | A4to6[2])); // 11 11 010
assign DcdD[18] = (~(A0to1[2] | A2to3[0] | A4to6[6])); // 10 00 110
assign DcdD[19] = (~(A0to1[1] | A2to3[0] | A4to6[6])); // 01 00 110
assign DcdD[20] = (~(A0to1[0] | A2to3[2] | A4to6[6])); // 00 10 110
assign DcdD[21] = (~(A0to1[3] | A2to3[2] | A4to6[6])); // 11 10 110
assign DcdD[22] = (~(A0to1[0] | A2to3[1] | A4to6[6])); // 00 01 110
assign DcdD[23] = (~(A0to1[3] | A2to3[1] | A4to6[6])); // 11 01 110
assign DcdD[24] = (~(A0to1[2] | A2to3[3] | A4to6[6])); // 10 11 110
assign DcdD[25] = (~(A0to1[1] | A2to3[3] | A4to6[6])); // 01 11 110
assign DcdD[26] = (~(A0to1[3] | A2to3[0] | A4to6[1])); // 11 00 001
assign DcdD[27] = (~(A0to1[2] | A2to3[2] | A4to6[1])); // 10 10 001
assign DcdD[28] = (~(A0to1[1] | A2to3[2] | A4to6[1])); // 01 10 001
assign DcdD[29] = (~(A0to1[2] | A2to3[1] | A4to6[1])); // 10 01 001
assign DcdD[30] = (~(A0to1[1] | A2to3[1] | A4to6[1])); // 01 01 001
assign DcdD[31] = (~(A0to1[0] | A2to3[3] | A4to6[1])); // 00 11 001
assign DcdD[32] = (~(A0to1[2] | A2to3[0] | A4to6[0])); // 10 00 000
assign DcdD[33] = (~(A0to1[1] | A2to3[0] | A4to6[0])); // 01 00 000
assign DcdD[34] = (~(A0to1[0] | A2to3[2] | A4to6[0])); // 00 10 000
assign DcdD[35] = (~(A0to1[0] | A2to3[1] | A4to6[0])); // 00 01 000
assign DcdD[36] = (~(A0to1[0] | A2to3[0] | A4to6[4])); // 00 00 100
assign DcdD[37] = (~(A0to1[0] | A2to3[0] | A4to6[2])); // 00 00 010
assign DcdD[38] = (~(A0to1[0] | A2to3[0] | A4to6[1])); // 00 00 001
assign synzero = (~(A0to1[0] | A2to3[0] | A4to6[0])); // 00 00 000

assign corrd[0:31] = din[0:31] ^ DcdD[0:31];

assign sbe_int = (DcdD[0:38] != {39{1'b0}}) ? 1'b1 :
1'b0;
assign sbe = sbe_int;
assign ue = (~sbe_int) & (~synzero) & encorr;

//mark_unused(A4to6(3));
//mark_unused(A4to6(5));
//mark_unused(A4to6(7));
end
endgenerate
endmodule

@ -0,0 +1,145 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// Description: XU ECC Generation Macro
//
//*****************************************************************************

module tri_eccgen(
din,
syn
);
parameter REGSIZE = 64;
input [0:REGSIZE+8-(64/REGSIZE)] din;
output [0:8-(64/REGSIZE)] syn;

generate // syndrome bits inverted
if (REGSIZE == 64)
begin : ecc64
wire [0:71] e;
wire [0:22] l1term;

// ====================================================================
// 64 data bits, 8 check bits
// single bit error correction, double bit error detection
// ====================================================================
// ecc matrix description
// ====================================================================
// syn 0 111011010011101001100101101101001100101101001011001101001110100110000000
// syn 1 110110101011010101010101011010101010101010101010101010101101010101000000
// syn 2 101101100110110011001100110110011001100110011001100110011011001100100000
// syn 3 011100011110001111000011110001111000011110000111100001111000111100010000
// syn 4 000011111110000000111111110000000111111110000000011111111000000000001000
// syn 5 000000000001111111111111110000000000000001111111111111111000000000000100
// syn 6 000000000000000000000000001111111111111111111111111111111000000000000010
// syn 7 000000000000000000000000000000000000000000000000000000000111111100000001

assign e[0:71] = din[0:71];

assign l1term[0] = e[0] ^ e[10] ^ e[17] ^ e[21] ^ e[32] ^ e[36] ^ e[44] ^ e[56];
assign l1term[1] = e[22] ^ e[23] ^ e[24] ^ e[25] ^ e[53] ^ e[54] ^ e[55] ^ e[56];
assign l1term[2] = e[1] ^ e[4] ^ e[11] ^ e[23] ^ e[26] ^ e[38] ^ e[46] ^ e[50];
assign l1term[3] = e[2] ^ e[5] ^ e[12] ^ e[24] ^ e[27] ^ e[39] ^ e[47] ^ e[51];
assign l1term[4] = e[3] ^ e[6] ^ e[13] ^ e[25] ^ e[28] ^ e[40] ^ e[48] ^ e[52];
assign l1term[5] = e[7] ^ e[8] ^ e[9] ^ e[10] ^ e[37] ^ e[38] ^ e[39] ^ e[40];
assign l1term[6] = e[14] ^ e[15] ^ e[16] ^ e[17] ^ e[45] ^ e[46] ^ e[47] ^ e[48];
assign l1term[7] = e[18] ^ e[19] ^ e[20] ^ e[21] ^ e[49] ^ e[50] ^ e[51] ^ e[52];
assign l1term[8] = e[7] ^ e[14] ^ e[18] ^ e[29] ^ e[33] ^ e[41] ^ e[53] ^ e[57];
assign l1term[9] = e[58] ^ e[60] ^ e[63] ^ e[64];
assign l1term[10] = e[8] ^ e[15] ^ e[19] ^ e[30] ^ e[34] ^ e[42] ^ e[54] ^ e[57];
assign l1term[11] = e[59] ^ e[61] ^ e[63] ^ e[65];
assign l1term[12] = e[9] ^ e[16] ^ e[20] ^ e[31] ^ e[35] ^ e[43] ^ e[55] ^ e[58];
assign l1term[13] = e[59] ^ e[62] ^ e[63] ^ e[66];
assign l1term[14] = e[1] ^ e[2] ^ e[3] ^ e[29] ^ e[30] ^ e[31] ^ e[32] ^ e[60];
assign l1term[15] = e[61] ^ e[62] ^ e[63] ^ e[67];
assign l1term[16] = e[4] ^ e[5] ^ e[6] ^ e[33] ^ e[34] ^ e[35] ^ e[36] ^ e[68];
assign l1term[17] = e[11] ^ e[12] ^ e[13] ^ e[41] ^ e[42] ^ e[43] ^ e[44] ^ e[69];
assign l1term[18] = e[26] ^ e[27] ^ e[28] ^ e[29] ^ e[30] ^ e[31] ^ e[32] ^ e[33];
assign l1term[19] = e[34] ^ e[35] ^ e[36] ^ e[37] ^ e[38] ^ e[39] ^ e[40] ^ e[41];
assign l1term[20] = e[42] ^ e[43] ^ e[44] ^ e[45] ^ e[46] ^ e[47] ^ e[48] ^ e[49];
assign l1term[21] = e[50] ^ e[51] ^ e[52] ^ e[53] ^ e[54] ^ e[55] ^ e[56] ^ e[70];
assign l1term[22] = e[57] ^ e[58] ^ e[59] ^ e[60] ^ e[61] ^ e[62] ^ e[63] ^ e[71];
assign syn[0] = l1term[0] ^ l1term[2] ^ l1term[3] ^ l1term[8] ^ l1term[9];
assign syn[1] = l1term[0] ^ l1term[2] ^ l1term[4] ^ l1term[10] ^ l1term[11];
assign syn[2] = l1term[0] ^ l1term[3] ^ l1term[4] ^ l1term[12] ^ l1term[13];
assign syn[3] = l1term[1] ^ l1term[5] ^ l1term[6] ^ l1term[14] ^ l1term[15];
assign syn[4] = l1term[1] ^ l1term[5] ^ l1term[7] ^ l1term[16];
assign syn[5] = l1term[1] ^ l1term[6] ^ l1term[7] ^ l1term[17];
assign syn[6] = l1term[18] ^ l1term[19] ^ l1term[20] ^ l1term[21];
assign syn[7] = l1term[22];
end
endgenerate

generate // syndrome bits inverted
if (REGSIZE == 32)
begin : ecc32
wire [0:38] e;
wire [0:13] l1term;

// ====================================================================
// 32 Data Bits, 7 Check bits
// Single bit error correction, Double bit error detection
// ====================================================================
// ECC Matrix Description
// ====================================================================
// Syn 0 111011010011101001100101101101001000000
// Syn 1 110110101011010101010101011010100100000
// Syn 2 101101100110110011001100110110010010000
// Syn 3 011100011110001111000011110001110001000
// Syn 4 000011111110000000111111110000000000100
// Syn 5 000000000001111111111111110000000000010
// Syn 6 000000000000000000000000001111110000001

assign e[0:38] = din[0:38];

assign l1term[0] = e[0] ^ e[1] ^ e[4] ^ e[10] ^ e[11] ^ e[17] ^ e[21] ^ e[23];
assign l1term[1] = e[2] ^ e[3] ^ e[9] ^ e[10] ^ e[16] ^ e[17] ^ e[24] ^ e[25];
assign l1term[2] = e[18] ^ e[19] ^ e[20] ^ e[21] ^ e[22] ^ e[23] ^ e[24] ^ e[25];
assign l1term[3] = e[2] ^ e[5] ^ e[7] ^ e[12] ^ e[14] ^ e[18] ^ e[24] ^ e[26];
assign l1term[4] = e[27] ^ e[29] ^ e[32];
assign l1term[5] = e[3] ^ e[6] ^ e[8] ^ e[13] ^ e[15] ^ e[19] ^ e[25] ^ e[26];
assign l1term[6] = e[28] ^ e[30] ^ e[33];
assign l1term[7] = e[0] ^ e[5] ^ e[6] ^ e[12] ^ e[13] ^ e[20] ^ e[21] ^ e[27];
assign l1term[8] = e[28] ^ e[31] ^ e[34];
assign l1term[9] = e[1] ^ e[7] ^ e[8] ^ e[14] ^ e[15] ^ e[22] ^ e[23] ^ e[29];
assign l1term[10] = e[30] ^ e[31] ^ e[35];
assign l1term[11] = e[4] ^ e[5] ^ e[6] ^ e[7] ^ e[8] ^ e[9] ^ e[10] ^ e[36];
assign l1term[12] = e[11] ^ e[12] ^ e[13] ^ e[14] ^ e[15] ^ e[16] ^ e[17] ^ e[37];
assign l1term[13] = e[26] ^ e[27] ^ e[28] ^ e[29] ^ e[30] ^ e[31] ^ e[38];
assign syn[0] = l1term[0] ^ l1term[3] ^ l1term[4];
assign syn[1] = l1term[0] ^ l1term[5] ^ l1term[6];
assign syn[2] = l1term[1] ^ l1term[7] ^ l1term[8];
assign syn[3] = l1term[1] ^ l1term[9] ^ l1term[10];
assign syn[4] = l1term[2] ^ l1term[11];
assign syn[5] = l1term[2] ^ l1term[12];
assign syn[6] = l1term[13];
end
endgenerate
endmodule

@ -0,0 +1,142 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_err_rpt.v
// *! DESCRIPTION : Error Reporting Component
// *!****************************************************************

`include "tri.vh"

module tri_err_rpt(
vd,
gd,
err_d1clk,
err_d2clk,
err_lclk,
err_scan_in,
err_scan_out,
mode_dclk,
mode_lclk,
mode_scan_in,
mode_scan_out,
err_in,
err_out,
hold_out,
mask_out
);
parameter WIDTH = 1; // number of errors of the same type
parameter MASK_RESET_VALUE = 1'b0; // use to set default/flush value for mask bits
parameter INLINE = 1'b0; // make hold latch be inline; err_out is sticky -- default to shadow
parameter SHARE_MASK = 1'b0; // PERMISSION NEEDED for true
// used for WIDTH >1 to reduce area of mask (common error disable)
parameter USE_NLATS = 1'b0; // only necessary in standby area to be able to reset to init value
parameter NEEDS_SRESET = 1; // for inferred latches

inout vd;
inout gd;
input err_d1clk; // caution1: if lcb uses powersavings, errors must always get reported
input err_d2clk; // caution2: if use_nlats is used these are also the clocks for the mask latches
input [0:`NCLK_WIDTH-1] err_lclk; // caution2: hence these have to be the mode clocks
// caution2: and all bits in the "func" chain have to be connected to the mode chain
// error scan chain (func or mode)
input [0:WIDTH-1] err_scan_in; // NOTE: connected to mode or func ring
output [0:WIDTH-1] err_scan_out;
// clock gateable mode clocks
input mode_dclk;
input [0:`NCLK_WIDTH-1] mode_lclk;
// mode scan chain
input [0:WIDTH-1] mode_scan_in;
output [0:WIDTH-1] mode_scan_out;

input [0:WIDTH-1] err_in;
output [0:WIDTH-1] err_out;

output [0:WIDTH-1] hold_out; // sticky error hold latch for trap usage
output [0:WIDTH-1] mask_out;

// tri_err_rpt

parameter [0:WIDTH-1] mask_initv = MASK_RESET_VALUE;
wire [0:WIDTH-1] hold_in;
wire [0:WIDTH-1] hold_lt;
wire [0:WIDTH-1] mask_lt;
(* analysis_not_referenced="true" *)
wire unused;
wire [0:WIDTH-1] unused_q_b;
// hold latches
assign hold_in = err_in | hold_lt;

tri_nlat_scan #(.WIDTH(WIDTH), .NEEDS_SRESET(NEEDS_SRESET))
hold(
.vd(vd),
.gd(gd),
.d1clk(err_d1clk),
.d2clk(err_d2clk),
.lclk(err_lclk),
.scan_in(err_scan_in[0:WIDTH - 1]),
.scan_out(err_scan_out[0:WIDTH - 1]),
.din(hold_in),
.q(hold_lt),
.q_b(unused_q_b)
);

generate
begin
// mask
if (SHARE_MASK == 1'b0)
begin : m
assign mask_lt = mask_initv;
end
if (SHARE_MASK == 1'b1)
begin : sm
assign mask_lt = {WIDTH{MASK_RESET_VALUE[0]}};
end

assign mode_scan_out = {WIDTH{1'b0}};

// assign outputs
assign hold_out = hold_lt;
assign mask_out = mask_lt;

if (INLINE == 1'b1)
begin : inline_hold
assign err_out = hold_lt & (~mask_lt);
end

if (INLINE == 1'b0)
begin : side_hold
assign err_out = err_in & (~mask_lt);
end

assign unused = | {mode_dclk, mode_lclk, mode_scan_in, unused_q_b};
end
endgenerate
endmodule

@ -0,0 +1,166 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

//********************************************************************
//*
//* TITLE: Performance Event Mux Component - 1 Thread; 4 bits
//*
//* NAME: tri_event_mux1t.v
//*
//********************************************************************

module tri_event_mux1t(
vd,
gd,
select_bits,
unit_events_in,
event_bus_in,
event_bus_out
);
parameter EVENTS_IN = 32; // Valid Settings: 16; 32; 64
parameter EVENTS_OUT = 4; // Valid Settings: 4 outputs per event mux
// Select bit size depends on total events: 16 events=16, 32 events=20; 64 events=24
input [0:((EVENTS_IN/32+4)*EVENTS_OUT)-1] select_bits;

input [1:EVENTS_IN-1] unit_events_in;

input [0:EVENTS_OUT-1] event_bus_in;

output [0:EVENTS_OUT-1] event_bus_out;

inout vd;

inout gd;


//=====================================================================
// Signal and Function Declarations
//=====================================================================
// Constants used to split up select_bits for the decoder
// Mux Size: 16 32 64
parameter INCR = EVENTS_IN/32 + 4; // INCR: 4 5 6

// For each output bit decode select bits to select an input mux to use.
wire [0:EVENTS_OUT*EVENTS_IN-1] inMuxDec;
wire [0:EVENTS_OUT*EVENTS_IN-1] inMuxOut;

// Paramaterized decoder function - decode mux value based on input select_bits
// Input size based on EVENTS_IN parameter: 16=4, 32=5, 64=6
function [0:EVENTS_IN-1] decode_a;
input [0:INCR-1] decode_input;
//(* analysis_not_referenced="true" *)
integer i;

for(i=0; i<EVENTS_IN; i=i+1)
begin
if({{32-INCR{1'b0}},decode_input} == i)
decode_a[i] = 1'b1;
else
decode_a[i] = 1'b0;
end
endfunction


//=====================================================================
// Start of event mux
//=====================================================================
// For each output bit, decode its select_bits to select the input mux it's using
generate
begin : xhdl0
genvar X;
for (X = 0; X <= EVENTS_OUT - 1; X = X + 1)
begin : decode
if (EVENTS_IN == 16)
begin : Mux16 // 4to16 decode; select_bits(0:3, 4:7, 8:11, 12:15 ) per output bit
assign inMuxDec[X * EVENTS_IN:X * EVENTS_IN + 15] = decode_a(select_bits[X * INCR:X * INCR + 3]);
end

if (EVENTS_IN == 32)
begin : Mux32 // 5to32 decode; select_bits(0:4, 5:9, 10:14, 15:19 ) per output bit
assign inMuxDec[X * EVENTS_IN:X * EVENTS_IN + 31] = decode_a(select_bits[X * INCR:X * INCR + 4]);
end

if (EVENTS_IN == 64)
begin : Mux64 // 6to64 decode; select_bits(0:5, 6:11, 12:17, 18:23 ) per output bit
assign inMuxDec[X * EVENTS_IN:X * EVENTS_IN + 63] = decode_a(select_bits[X * INCR:X * INCR + 5]);
end
end
end
endgenerate

// For each output bit, inMux decodes gate the selected unit event input; or event_bus_in when decode=0
generate
begin : xhdl2
genvar X;
for (X = 0; X <= EVENTS_OUT - 1; X = X + 1)
begin : inpMux

assign inMuxOut[X * EVENTS_IN + 0] = (inMuxDec[X * EVENTS_IN + 0] & event_bus_in[X]) ;

begin : xhdl1
genvar I;
for (I = 1; I <= EVENTS_IN - 1; I = I + 1)
begin : eventSel

assign inMuxOut[X * EVENTS_IN + I] = (inMuxDec[X * EVENTS_IN + I] & unit_events_in[I]) ;

end
end
end
end
endgenerate


// ORing the input mux outputs to drive each event output bit.
// Only one selected at a time by each output bit's inMux decode value.
generate
begin : xhdl5
genvar X;
for (X = 0; X <= EVENTS_OUT - 1; X = X + 1)
begin : bitOutHi
if (EVENTS_IN == 16)
begin : Mux16
assign event_bus_out[X] = (|inMuxOut[X * EVENTS_IN:X * EVENTS_IN + 15]);
end

if (EVENTS_IN == 32)
begin : Mux32
assign event_bus_out[X] = (|inMuxOut[X * EVENTS_IN:X * EVENTS_IN + 31]);
end

if (EVENTS_IN == 64)
begin : Mux64
assign event_bus_out[X] = (|inMuxOut[X * EVENTS_IN:X * EVENTS_IN + 63]);
end
end
end
endgenerate

endmodule

@ -0,0 +1,53 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

`include "tri_a2o.vh"


module tri_fu_csa22_h2(
a,
b,
car,
sum
);
input a;
input b;
output car;
output sum;

wire car_b;
wire sum_b;

assign car_b = (~(a & b));
assign sum_b = (~(car_b & (a | b))); // this is equiv to an xnor
assign car = (~car_b);
assign sum = (~sum_b);

endmodule

@ -0,0 +1,322 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

`include "tri_a2o.vh"

module tri_fu_mul(
vdd,
gnd,
clkoff_b,
act_dis,
flush,
delay_lclkr,
mpw1_b,
mpw2_b,
sg_1,
thold_1,
fpu_enable,
nclk,
f_mul_si,
f_mul_so,
ex2_act,
f_fmt_ex2_a_frac,
f_fmt_ex2_a_frac_17,
f_fmt_ex2_a_frac_35,
f_fmt_ex2_c_frac,
f_mul_ex3_sum,
f_mul_ex3_car
);

inout vdd;
inout gnd;
input clkoff_b; // tiup
input act_dis; // ??tidn??
input flush; // ??tidn??
input delay_lclkr; // tidn,
input mpw1_b; // tidn,
input mpw2_b; // tidn,
input sg_1;
input thold_1;
input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;

input f_mul_si; //perv
output f_mul_so; //perv
input ex2_act; //act

input [0:52] f_fmt_ex2_a_frac; // implicit bit already generated
input f_fmt_ex2_a_frac_17; // new port for replicated bit
input f_fmt_ex2_a_frac_35; // new port for replicated bit
input [0:53] f_fmt_ex2_c_frac; // implicit bit already generated

output [1:108] f_mul_ex3_sum;
output [1:108] f_mul_ex3_car;

// ENTITY


parameter tiup = 1'b1;
parameter tidn = 1'b0;

wire thold_0_b;
wire thold_0;
wire force_t;
wire sg_0;
wire [0:3] spare_unused;
//--------------------------------------
wire [0:3] act_so; //SCAN
wire [0:3] act_si;
wire m92_0_so;
wire m92_1_so;
wire m92_2_so;
//--------------------------------------
wire [36:108] pp3_05;
wire [35:108] pp3_04;
wire [18:90] pp3_03;
wire [17:90] pp3_02;
wire [0:72] pp3_01;
wire [0:72] pp3_00;

wire hot_one_msb_unused;
wire hot_one_74;
wire hot_one_92;
wire xtd_unused;

wire [1:108] pp5_00;
wire [1:108] pp5_01;

////################################################################
////# pervasive
////################################################################


tri_plat thold_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(thold_1),
.q(thold_0)
);


tri_plat sg_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(sg_1),
.q(sg_0)
);


tri_lcbor lcbor_0(
.clkoff_b(clkoff_b),
.thold(thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(thold_0_b)
);

////################################################################
////# act
////################################################################


tri_rlmreg_p #(.WIDTH(4), .NEEDS_SRESET(0)) act_lat(
.force_t(force_t), //i-- tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr), //i-- tidn,
.mpw1_b(mpw1_b), //i-- tidn,
.mpw2_b(mpw2_b), //i-- tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(fpu_enable),
.thold_b(thold_0_b),
.sg(sg_0),
.scout(act_so),
.scin(act_si),
//-----------------
.din({ spare_unused[0],
spare_unused[1],
spare_unused[2],
spare_unused[3]}),
//-----------------
.dout({spare_unused[0],
spare_unused[1],
spare_unused[2],
spare_unused[3]})
);

assign act_si[0:3] = {act_so[1:3], m92_2_so};

assign f_mul_so = act_so[0];

////################################################################
////# ex2 logic
////################################################################

////# NUMBERING SYSTEM RELATIVE TO COMPRESSOR TREE
////#
////# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111
////# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000
////# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678
////# 0 ..DdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..................................................
////# 1 ..1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................................................
////# 2 ....1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..............................................
////# 3 ......1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............................................
////# 4 ........1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..........................................
////# 5 ..........1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........................................
////# 6 ............1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s......................................
////# 7 ..............1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s....................................
////# 8 ................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..................................

////# 9 ..................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................................
////# 10 ....................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..............................
////# 11 ......................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............................
////# 12 ........................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..........................
////# 13 ..........................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........................
////# 14 ............................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s......................
////# 15 ..............................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s....................
////# 16 ................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..................
////# 17 ..................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................

////# 18 ....................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..............
////# 19 ......................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............
////# 20 ........................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..........
////# 21 ..........................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........
////# 22 ............................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s......
////# 23 ..............................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s....
////# 24 ................................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..
////# 25 ..................................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s
////# 26 ...................................................assDdddddddddddddddddddddddddddddddddddddddddddddddddddddD


tri_fu_mul_92 #(.inst(2)) m92_2(
.vdd(vdd), //i--
.gnd(gnd), //i--
.nclk(nclk), //i--
.force_t(force_t), //i--
.lcb_delay_lclkr(delay_lclkr), //i-- tidn
.lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0
.lcb_mpw2_b(mpw2_b), //i-- mpw2_b others=0
.thold_b(thold_0_b), //i--
.lcb_sg(sg_0), //i--
.si(f_mul_si), //i--
.so(m92_0_so), //o--
.ex2_act(ex2_act), //i--
//--------------------
.c_frac(f_fmt_ex2_c_frac[0:53]), //i-- Multiplicand (shift me)
.a_frac({f_fmt_ex2_a_frac[35:52], //i-- Multiplier (recode me)
tidn}), //i-- Multiplier (recode me)
.hot_one_out(hot_one_92), //o--
.sum92(pp3_05[36:108]), //o--
.car92(pp3_04[35:108]) //o--
);


tri_fu_mul_92 #(.inst(1)) m92_1(
.vdd(vdd), //i--
.gnd(gnd), //i--
.nclk(nclk), //i--
.force_t(force_t), //i--
.lcb_delay_lclkr(delay_lclkr), //i-- tidn
.lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0
.lcb_mpw2_b(mpw2_b), //i-- mpw2_b others=0
.thold_b(thold_0_b), //i--
.lcb_sg(sg_0), //i--
.si(m92_0_so), //i--
.so(m92_1_so), //o-- v
.ex2_act(ex2_act), //i--
//-------------------
.c_frac(f_fmt_ex2_c_frac[0:53]), //i-- Multiplicand (shift me)
.a_frac({f_fmt_ex2_a_frac[17:34], //i-- Multiplier (recode me)
f_fmt_ex2_a_frac_35}), //i-- Multiplier (recode me)
.hot_one_out(hot_one_74), //o--
.sum92(pp3_03[18:90]), //o--
.car92(pp3_02[17:90]) //o--
);


tri_fu_mul_92 #(.inst(0)) m92_0(
.vdd(vdd), //i--
.gnd(gnd), //i--
.nclk(nclk), //i--
.force_t(force_t), //i--
.lcb_delay_lclkr(delay_lclkr), //i-- tidn
.lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0
.lcb_mpw2_b(mpw2_b), //i-- mpw2_b others=0
.thold_b(thold_0_b), //i--
.lcb_sg(sg_0), //i--
.si(m92_1_so), //i--
.so(m92_2_so), //o--
.ex2_act(ex2_act), //i--
//-------------------
.c_frac(f_fmt_ex2_c_frac[0:53]), //i-- Multiplicand (shift me)
.a_frac({tidn, //i-- Multiplier (recode me)
f_fmt_ex2_a_frac[0:16], //i-- Multiplier (recode me)
f_fmt_ex2_a_frac_17}), //i-- Multiplier (recode me)
.hot_one_out(hot_one_msb_unused), //o--
.sum92(pp3_01[0:72]), //o--
.car92({xtd_unused, //o--
pp3_00[0:72]}) //o--
);

////##################################################
////# Compressor Level 4 , 5
////##################################################


tri_fu_mul_62 m62(
.vdd(vdd),
.gnd(gnd),
.hot_one_92(hot_one_92), //i--
.hot_one_74(hot_one_74), //i--
.pp3_05(pp3_05[36:108]), //i--
.pp3_04(pp3_04[35:108]), //i--
.pp3_03(pp3_03[18:90]), //i--
.pp3_02(pp3_02[17:90]), //i--
.pp3_01(pp3_01[0:72]), //i--
.pp3_00(pp3_00[0:72]), //i--

.sum62(pp5_01[1:108]), //o--
.car62(pp5_00[1:108]) //o--
);

////################################################################
////# ex3 logic
////################################################################

assign f_mul_ex3_sum[1:108] = pp5_01[1:108]; //output
assign f_mul_ex3_car[1:108] = pp5_00[1:108]; //output

endmodule

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -0,0 +1,104 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILE NAME : tri_fu_mul_bthdcd.vhdl
// *! DESCRIPTION : Booth Decode
// *!****************************************************************

`include "tri_a2o.vh"

module tri_fu_mul_bthdcd(
i0,
i1,
i2,
s_neg,
s_x,
s_x2
);
input i0;
input i1;
input i2;
output s_neg;
output s_x;
output s_x2;

// ATTRIBUTE btr_name OF tri_fu_mul_bthdcd : ENTITY IS "tri_fu_mul_bthdcd";

wire s_add;
wire sx1_a0_b;
wire sx1_a1_b;
wire sx1_t;
wire sx1_i;
wire sx2_a0_b;
wire sx2_a1_b;
wire sx2_t;
wire sx2_i;
wire i0_b;
wire i1_b;
wire i2_b;

// i0:2 booth recode table
//--------------------------------
// 000 add sh1=0 sh2=0 sub_adj=0
// 001 add sh1=1 sh2=0 sub_adj=0
// 010 add sh1=1 sh2=0 sub_adj=0
// 011 add sh1=0 sh2=1 sub_adj=0
// 100 sub sh1=0 sh2=1 sub_adj=1
// 101 sub sh1=1 sh2=0 sub_adj=1
// 110 sub sh1=1 sh2=0 sub_adj=1
// 111 sub sh1=0 sh2=0 sub_adj=0

// logically correct
//----------------------------------
// s_neg <= (i0);
// s_x <= ( not i1 and i2) or ( i1 and not i2);
// s_x2 <= (i0 and not i1 and not i2) or (not i0 and i1 and i2);

assign i0_b = (~(i0));
assign i1_b = (~(i1));
assign i2_b = (~(i2));

assign s_add = (~(i0));
assign s_neg = (~(s_add));

assign sx1_a0_b = (~(i1_b & i2));
assign sx1_a1_b = (~(i1 & i2_b));
assign sx1_t = (~(sx1_a0_b & sx1_a1_b));
assign sx1_i = (~(sx1_t));
assign s_x = (~(sx1_i));

assign sx2_a0_b = (~(i0 & i1_b & i2_b));
assign sx2_a1_b = (~(i0_b & i1 & i2));
assign sx2_t = (~(sx2_a0_b & sx2_a1_b));
assign sx2_i = (~(sx2_t));
assign s_x2 = (~(sx2_i));

endmodule

@ -0,0 +1,66 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILE NAME : tri_fu_mul_bthdcd.vhdl
// *! DESCRIPTION : Booth Decode
// *!****************************************************************

`include "tri_a2o.vh"

module tri_fu_mul_bthmux(
x,
sneg,
sx,
sx2,
right,
left,
q
);
input x;
input sneg; // do not flip the input (add)
input sx; // shift by 1
input sx2; // shift by 2
input right; // bit from the right (lsb)
output left; // bit from the left
output q; // final output

wire center;
wire q_b;

assign center = x ^ sneg;

assign left = center; //output-- rename, no gate

assign q_b = (~((sx & center) | (sx2 & right)));

assign q = (~q_b); // output--

endmodule

@ -0,0 +1,675 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILE NAME : tri_fu_mul_bthrow.vhdl
// *! DESCRIPTION : Booth Decode
// *!****************************************************************

module tri_fu_mul_bthrow(
x,
s_neg,
s_x,
s_x2,
hot_one,
q
);
input [0:53] x;
input s_neg; // negate the row
input s_x; // shift by 1
input s_x2; // shift by 2
output hot_one; // lsb term for row below
output [0:54] q; // final output

// ENTITY


parameter tiup = 1'b1;
parameter tidn = 1'b0;

wire [0:54] left;
wire unused;

assign unused = left[0]; // dangling pin from edge bit

////###############################################################
//# A row of the repeated part of the booth_mux row
////###############################################################

tri_fu_mul_bthmux u00(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(tidn), //i-- ********
.right(left[1]), //i-- [n+1]
.left(left[0]), //o-- [n]
.q(q[0]) //o--
);


tri_fu_mul_bthmux u01(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[0]), //i-- [n-1]
.right(left[2]), //i-- [n+1]
.left(left[1]), //o-- [n]
.q(q[1]) //o--
);


tri_fu_mul_bthmux u02(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[1]), //i--
.right(left[3]), //i--
.left(left[2]), //o--
.q(q[2]) //o--
);


tri_fu_mul_bthmux u03(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[2]), //i--
.right(left[4]), //i--
.left(left[3]), //o--
.q(q[3]) //o--
);


tri_fu_mul_bthmux u04(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[3]), //i--
.right(left[5]), //i--
.left(left[4]), //o--
.q(q[4]) //o--
);


tri_fu_mul_bthmux u05(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[4]), //i--
.right(left[6]), //i--
.left(left[5]), //o--
.q(q[5]) //o--
);


tri_fu_mul_bthmux u06(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[5]), //i--
.right(left[7]), //i--
.left(left[6]), //o--
.q(q[6]) //o--
);


tri_fu_mul_bthmux u07(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[6]), //i--
.right(left[8]), //i--
.left(left[7]), //o--
.q(q[7]) //o--
);


tri_fu_mul_bthmux u08(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[7]), //i--
.right(left[9]), //i--
.left(left[8]), //o--
.q(q[8]) //o--
);


tri_fu_mul_bthmux u09(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[8]), //i--
.right(left[10]), //i--
.left(left[9]), //o--
.q(q[9]) //o--
);


tri_fu_mul_bthmux u10(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[9]), //i--
.right(left[11]), //i--
.left(left[10]), //o--
.q(q[10]) //o--
);


tri_fu_mul_bthmux u11(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[10]), //i--
.right(left[12]), //i--
.left(left[11]), //o--
.q(q[11]) //o--
);


tri_fu_mul_bthmux u12(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[11]), //i--
.right(left[13]), //i--
.left(left[12]), //o--
.q(q[12]) //o--
);


tri_fu_mul_bthmux u13(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[12]), //i--
.right(left[14]), //i--
.left(left[13]), //o--
.q(q[13]) //o--
);


tri_fu_mul_bthmux u14(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[13]), //i--
.right(left[15]), //i--
.left(left[14]), //o--
.q(q[14]) //o--
);


tri_fu_mul_bthmux u15(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[14]), //i--
.right(left[16]), //i--
.left(left[15]), //o--
.q(q[15]) //o--
);


tri_fu_mul_bthmux u16(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[15]), //i--
.right(left[17]), //i--
.left(left[16]), //o--
.q(q[16]) //o--
);


tri_fu_mul_bthmux u17(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[16]), //i--
.right(left[18]), //i--
.left(left[17]), //o--
.q(q[17]) //o--
);


tri_fu_mul_bthmux u18(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[17]), //i--
.right(left[19]), //i--
.left(left[18]), //o--
.q(q[18]) //o--
);


tri_fu_mul_bthmux u19(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[18]), //i--
.right(left[20]), //i--
.left(left[19]), //o--
.q(q[19]) //o--
);


tri_fu_mul_bthmux u20(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[19]), //i--
.right(left[21]), //i--
.left(left[20]), //o--
.q(q[20]) //o--
);


tri_fu_mul_bthmux u21(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[20]), //i--
.right(left[22]), //i--
.left(left[21]), //o--
.q(q[21]) //o--
);


tri_fu_mul_bthmux u22(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[21]), //i--
.right(left[23]), //i--
.left(left[22]), //o--
.q(q[22]) //o--
);


tri_fu_mul_bthmux u23(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[22]), //i--
.right(left[24]), //i--
.left(left[23]), //o--
.q(q[23]) //o--
);


tri_fu_mul_bthmux u24(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[23]), //i--
.right(left[25]), //i--
.left(left[24]), //o--
.q(q[24]) //o--
);


tri_fu_mul_bthmux u25(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[24]), //i--
.right(left[26]), //i--
.left(left[25]), //o--
.q(q[25]) //o--
);


tri_fu_mul_bthmux u26(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[25]), //i--
.right(left[27]), //i--
.left(left[26]), //o--
.q(q[26]) //o--
);


tri_fu_mul_bthmux u27(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[26]), //i--
.right(left[28]), //i--
.left(left[27]), //o--
.q(q[27]) //o--
);


tri_fu_mul_bthmux u28(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[27]), //i--
.right(left[29]), //i--
.left(left[28]), //o--
.q(q[28]) //o--
);


tri_fu_mul_bthmux u29(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[28]), //i--
.right(left[30]), //i--
.left(left[29]), //o--
.q(q[29]) //o--
);


tri_fu_mul_bthmux u30(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[29]), //i--
.right(left[31]), //i--
.left(left[30]), //o--
.q(q[30]) //o--
);


tri_fu_mul_bthmux u31(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[30]), //i--
.right(left[32]), //i--
.left(left[31]), //o--
.q(q[31]) //o--
);


tri_fu_mul_bthmux u32(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[31]), //i--
.right(left[33]), //i--
.left(left[32]), //o--
.q(q[32]) //o--
);


tri_fu_mul_bthmux u33(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[32]), //i--
.right(left[34]), //i--
.left(left[33]), //o--
.q(q[33]) //o--
);


tri_fu_mul_bthmux u34(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[33]), //i--
.right(left[35]), //i--
.left(left[34]), //o--
.q(q[34]) //o--
);


tri_fu_mul_bthmux u35(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[34]), //i--
.right(left[36]), //i--
.left(left[35]), //o--
.q(q[35]) //o--
);


tri_fu_mul_bthmux u36(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[35]), //i--
.right(left[37]), //i--
.left(left[36]), //o--
.q(q[36]) //o--
);


tri_fu_mul_bthmux u37(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[36]), //i--
.right(left[38]), //i--
.left(left[37]), //o--
.q(q[37]) //o--
);


tri_fu_mul_bthmux u38(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[37]), //i--
.right(left[39]), //i--
.left(left[38]), //o--
.q(q[38]) //o--
);


tri_fu_mul_bthmux u39(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[38]), //i--
.right(left[40]), //i--
.left(left[39]), //o--
.q(q[39]) //o--
);


tri_fu_mul_bthmux u40(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[39]), //i--
.right(left[41]), //i--
.left(left[40]), //o--
.q(q[40]) //o--
);


tri_fu_mul_bthmux u41(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[40]), //i--
.right(left[42]), //i--
.left(left[41]), //o--
.q(q[41]) //o--
);


tri_fu_mul_bthmux u42(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[41]), //i--
.right(left[43]), //i--
.left(left[42]), //o--
.q(q[42]) //o--
);


tri_fu_mul_bthmux u43(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[42]), //i--
.right(left[44]), //i--
.left(left[43]), //o--
.q(q[43]) //o--
);


tri_fu_mul_bthmux u44(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[43]), //i--
.right(left[45]), //i--
.left(left[44]), //o--
.q(q[44]) //o--
);


tri_fu_mul_bthmux u45(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[44]), //i--
.right(left[46]), //i--
.left(left[45]), //o--
.q(q[45]) //o--
);


tri_fu_mul_bthmux u46(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[45]), //i--
.right(left[47]), //i--
.left(left[46]), //o--
.q(q[46]) //o--
);


tri_fu_mul_bthmux u47(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[46]), //i--
.right(left[48]), //i--
.left(left[47]), //o--
.q(q[47]) //o--
);


tri_fu_mul_bthmux u48(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[47]), //i--
.right(left[49]), //i--
.left(left[48]), //o--
.q(q[48]) //o--
);


tri_fu_mul_bthmux u49(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[48]), //i--
.right(left[50]), //i--
.left(left[49]), //o--
.q(q[49]) //o--
);


tri_fu_mul_bthmux u50(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[49]), //i--
.right(left[51]), //i--
.left(left[50]), //o--
.q(q[50]) //o--
);


tri_fu_mul_bthmux u51(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[50]), //i--
.right(left[52]), //i--
.left(left[51]), //o--
.q(q[51]) //o--
);


tri_fu_mul_bthmux u52(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[51]), //i--
.right(left[53]), //i--
.left(left[52]), //o--
.q(q[52]) //o--
);


tri_fu_mul_bthmux u53(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[52]), //i--
.right(left[54]), //i--
.left(left[53]), //o--
.q(q[53]) //o--
);


tri_fu_mul_bthmux u54(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[53]), //i--
.right(s_neg), //i--
.left(left[54]), //o--
.q(q[54]) //o--
);

// For negate -A = !A + 1 ... this term is the plus 1.
// this has same bit weight as LSB, so it jumps down a row to free spot in compressor tree.

assign hot_one = (s_neg & (s_x | s_x2));

endmodule

File diff suppressed because it is too large Load Diff

@ -0,0 +1,112 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILE NAME : tri_fu_tblmul_bthdcd.vhdl
// *! DESCRIPTION : Booth Decode
// *!****************************************************************

`include "tri_a2o.vh"

module tri_fu_tblmul_bthdcd(
i0,
i1,
i2,
s_neg,
s_x,
s_x2
);
input i0;
input i1;
input i2;
output s_neg;
output s_x;
output s_x2;

wire s_add;
wire sx1_a0_b;
wire sx1_a1_b;
wire sx1_t;
wire sx1_i;
wire sx2_a0_b;
wire sx2_a1_b;
wire sx2_t;
wire sx2_i;
wire i0_b;
wire i1_b;
wire i2_b;


//// -- 000 add sh1=0 sh2=0 sub_adj=0
//// -- 001 add sh1=1 sh2=0 sub_adj=0
//// -- 010 add sh1=1 sh2=0 sub_adj=0
//// -- 011 add sh1=0 sh2=1 sub_adj=0
//// -- 100 sub sh1=0 sh2=1 sub_adj=1
//// -- 101 sub sh1=1 sh2=0 sub_adj=1
//// -- 110 sub sh1=1 sh2=0 sub_adj=1
//// -- 111 sub sh1=0 sh2=0 sub_adj=0
////
//// s_neg <= ( i0 );
////
//// s_x <= ( not i1 and i2 ) or
//// ( i1 and not i2 );
//// s_x2 <= ( i0 and not i1 and not i2 ) or
//// ( not i0 and i1 and i2 );
////
//// sub_adj <= i0 and not( i1 and i2 );
////

// logically correct
//----------------------------------
// s_neg <= (i0);
// s_x <= ( not i1 and i2) or ( i1 and not i2);
// s_x2 <= (i0 and not i1 and not i2) or (not i0 and i1 and i2);

assign i0_b = (~(i0));
assign i1_b = (~(i1));
assign i2_b = (~(i2));

assign s_add = (~(i0));
assign s_neg = (~(s_add));

assign sx1_a0_b = (~(i1_b & i2));
assign sx1_a1_b = (~(i1 & i2_b));
assign sx1_t = (~(sx1_a0_b & sx1_a1_b));
assign sx1_i = (~(sx1_t));
assign s_x = (~(sx1_i));

assign sx2_a0_b = (~(i0 & i1_b & i2_b));
assign sx2_a1_b = (~(i0_b & i1 & i2));
assign sx2_t = (~(sx2_a0_b & sx2_a1_b));
assign sx2_i = (~(sx2_t));
assign s_x2 = (~(sx2_i));


endmodule

@ -0,0 +1,248 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

`include "tri_a2o.vh"

module tri_fu_tblmul_bthrow(
x,
s_neg,
s_x,
s_x2,
q
);

input [0:15] x; //
input s_neg; // negate the row
input s_x; // shift by 1
input s_x2; // shift by 2
output [0:16] q; // final output

// ENTITY


parameter tiup = 1'b1;
parameter tidn = 1'b0;

wire [0:16] left;
wire unused;

////################################################################
////# A row of the repeated part of the booth_mux row
////################################################################

assign unused = left[0];

tri_fu_mul_bthmux u00(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(tidn), //i-- ********
.left(left[0]), //o-- [n]
.right(left[1]), //i-- [n+1]
.q(q[0]) //o--
);


tri_fu_mul_bthmux u01(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[0]), //i-- [n-1]
.left(left[1]), //o-- [n]
.right(left[2]), //i-- [n+1]
.q(q[1]) //o--
);


tri_fu_mul_bthmux u02(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[1]), //i--
.left(left[2]), //o--
.right(left[3]), //i--
.q(q[2]) //o--
);


tri_fu_mul_bthmux u03(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[2]), //i--
.left(left[3]), //o--
.right(left[4]), //i--
.q(q[3]) //o--
);


tri_fu_mul_bthmux u04(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[3]), //i--
.left(left[4]), //o--
.right(left[5]), //i--
.q(q[4]) //o--
);


tri_fu_mul_bthmux u05(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[4]), //i--
.left(left[5]), //o--
.right(left[6]), //i--
.q(q[5]) //o--
);


tri_fu_mul_bthmux u06(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[5]), //i--
.left(left[6]), //o--
.right(left[7]), //i--
.q(q[6]) //o--
);


tri_fu_mul_bthmux u07(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[6]), //i--
.left(left[7]), //o--
.right(left[8]), //i--
.q(q[7]) //o--
);


tri_fu_mul_bthmux u08(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[7]), //i--
.left(left[8]), //o--
.right(left[9]), //i--
.q(q[8]) //o--
);


tri_fu_mul_bthmux u09(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[8]), //i--
.left(left[9]), //o--
.right(left[10]), //i--
.q(q[9]) //o--
);


tri_fu_mul_bthmux u10(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[9]), //i--
.left(left[10]), //o--
.right(left[11]), //i--
.q(q[10]) //o--
);


tri_fu_mul_bthmux u11(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[10]), //i--
.left(left[11]), //o--
.right(left[12]), //i--
.q(q[11]) //o--
);


tri_fu_mul_bthmux u12(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[11]), //i--
.left(left[12]), //o--
.right(left[13]), //i--
.q(q[12]) //o--
);


tri_fu_mul_bthmux u13(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[12]), //i--
.left(left[13]), //o--
.right(left[14]), //i--
.q(q[13]) //o--
);


tri_fu_mul_bthmux u14(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[13]), //i--
.left(left[14]), //o--
.right(left[15]), //i--
.q(q[14]) //o--
);


tri_fu_mul_bthmux u15(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[14]), //i--
.left(left[15]), //o--
.right(left[16]), //i--
.q(q[15]) //o--
);


tri_fu_mul_bthmux u16(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[15]), //i--
.left(left[16]), //o--
.right(s_neg), //i--
.q(q[16]) //o--
);

endmodule

@ -0,0 +1,61 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_inv.v
// *! DESCRIPTION : INVERTER gate
// *!****************************************************************

`include "tri_a2o.vh"

module tri_inv(
y,
a
);
parameter WIDTH = 1;
parameter BTR = "INV_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;

// tri_nand2
genvar i;

generate
begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w

not I0(y[i], a[i]);

end // block: w
end

endgenerate
endmodule

@ -0,0 +1,120 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME : tri_inv_nlats.v
// *! DESCRIPTION : n-bit scannable m/s latch, for bit stacking, with inv gate in front
// *!****************************************************************

`include "tri_a2o.vh"

module tri_inv_nlats(
vd,
gd,
lclk,
d1clk,
d2clk,
scanin,
scanout,
d,
qb
);
parameter OFFSET = 0;
parameter WIDTH = 1;
parameter INIT = 0;
parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch;
//0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
parameter SYNTHCLONEDLATCH = "";
parameter BTR = "NLI0001_X1_A12TH";
parameter NEEDS_SRESET = 1; // for inferred latches
parameter DOMAIN_CROSSING = 0;

inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] lclk;
input d1clk;
input d2clk;
input [OFFSET:OFFSET+WIDTH-1] scanin;
output [OFFSET:OFFSET+WIDTH-1] scanout;
input [OFFSET:OFFSET+WIDTH-1] d;
output [OFFSET:OFFSET+WIDTH-1] qb;

// tri_inv_nlats

parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};

generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
wire [0:WIDTH-1] din;
(* analysis_not_referenced="true" *)
wire unused;

if (NEEDS_SRESET == 1)
begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0;
end

assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign din = d; // Output is inverted, so don't invert here
assign int_din = (vsreset_b & din) | (vsreset & init_v);

assign vact = {WIDTH{d1clk}};
assign vact_b = {WIDTH{~d1clk}};

assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};


always @(posedge lclk[0])
begin: l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
assign qb = (~int_dout);
assign scanout = ZEROS;

assign unused = | {vd, gd, lclk, scanin};
end
endgenerate
endmodule

@ -0,0 +1,343 @@
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 fs / 1 fs

// *!****************************************************************
// *! FILENAME : tri_iuq_cpl_arr.v
// *! DESCRIPTION : iuq completion array (fpga model)
// *!****************************************************************

`include "tri_a2o.vh"

module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, force_t, thold_0_b, sg_0, scan_in, scan_out, re0, ra0, do0, re1, ra1, do1, we0, wa0, di0, we1, wa1, di1, perr);
parameter ADDRESSABLE_PORTS = 64; // number of addressable register in this array
parameter ADDRESSBUS_WIDTH = 6; // width of the bus to address all ports (2^ADDRESSBUS_WIDTH >= addressable_ports)
parameter PORT_BITWIDTH = 64; // bitwidth of ports
parameter LATCHED_READ = 1'b1;
parameter LATCHED_READ_DATA = 1'b1;
parameter LATCHED_WRITE = 1'b1;

// POWER PINS
(* ground_pin=1 *)
inout gnd;
(* power_pin=1 *)
inout vdd;

input [0:`NCLK_WIDTH-1] nclk;

//-------------------------------------------------------------------
// Pervasive
//-------------------------------------------------------------------
input delay_lclkr_dc;
input mpw1_dc_b;
input mpw2_dc_b;
input force_t;
input thold_0_b;
input sg_0;
input scan_in;
output scan_out;

//-------------------------------------------------------------------
// Functional
//-------------------------------------------------------------------
input re0;
input [0:ADDRESSBUS_WIDTH-1] ra0;
output [0:PORT_BITWIDTH-1] do0;

input re1;
input [0:ADDRESSBUS_WIDTH-1] ra1;
output [0:PORT_BITWIDTH-1] do1;

input we0;
input [0:ADDRESSBUS_WIDTH-1] wa0;
input [0:PORT_BITWIDTH-1] di0;

input we1;
input [0:ADDRESSBUS_WIDTH-1] wa1;
input [0:PORT_BITWIDTH-1] di1;

output perr;

reg re0_q;
reg we0_q;
reg [0:ADDRESSBUS_WIDTH-1] ra0_q;
reg [0:ADDRESSBUS_WIDTH-1] wa0_q;
reg [0:PORT_BITWIDTH-1] do0_q;
wire [0:PORT_BITWIDTH-1] do0_d;
reg [0:PORT_BITWIDTH-1] di0_q;

reg re1_q;
reg we1_q;
reg [0:ADDRESSBUS_WIDTH-1] ra1_q;
reg [0:ADDRESSBUS_WIDTH-1] wa1_q;
reg [0:PORT_BITWIDTH-1] do1_q;
wire [0:PORT_BITWIDTH-1] do1_d;
reg [0:PORT_BITWIDTH-1] di1_q;

wire correct_clk;
wire reset;
wire reset_hi;
reg reset_q;

wire [0:PORT_BITWIDTH-1] dout0; //std
wire wen0; //std
wire [0:ADDRESSBUS_WIDTH-1] addr_w0; //std
wire [0:ADDRESSBUS_WIDTH-1] addr_r0; //std
wire [0:PORT_BITWIDTH-1] din0; //std

wire [0:PORT_BITWIDTH-1] dout1; //std
wire wen1; //std
wire [0:ADDRESSBUS_WIDTH-1] addr_w1; //std
wire [0:ADDRESSBUS_WIDTH-1] addr_r1; //std
wire [0:PORT_BITWIDTH-1] din1; //std

reg we1_latch_q;
reg [0:ADDRESSBUS_WIDTH-1] wa1_latch_q;
reg [0:PORT_BITWIDTH-1] di1_latch_q;


(* analysis_not_referenced="true" *)
wire unused_SPO_0;
(* analysis_not_referenced="true" *)
wire unused_SPO_1;


generate
assign reset = nclk[1];
assign correct_clk = nclk[0];

assign reset_hi = reset;


// Slow Latches (nclk)

always @(posedge correct_clk or posedge reset)
begin: slatch
begin
if (reset == 1'b1)
we1_latch_q <= 1'b0;
else
begin
we1_latch_q <= we1_q;
wa1_latch_q <= wa1_q;
di1_latch_q <= di1_q;
end
end
end


// repower latches for resets
always @(posedge correct_clk)
begin: rlatch
reset_q <= reset_hi;
end

// need to select which array to write based on the lowest order bit of the address which will indicate odd or even itag
// when both we0 and we1 are both asserted it is assumed that the low order bit of wa0 will not be equal to the low order
// bit of wa1
assign addr_w0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? {wa1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {wa0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
assign wen0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? we1_q : we0_q;
assign din0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? di1_q : di0_q;
assign addr_r0 = (ra0_q[ADDRESSBUS_WIDTH-1]) ? {ra1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {ra0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };

assign addr_w1 = (wa1_q[ADDRESSBUS_WIDTH-1]) ? {wa1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {wa0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
assign wen1 = (wa1_q[ADDRESSBUS_WIDTH-1]) ? we1_q : we0_q;
assign din1 = (wa1_q[ADDRESSBUS_WIDTH-1]) ? di1_q : di0_q;
assign addr_r1 = (ra1_q[ADDRESSBUS_WIDTH-1]) ? {ra1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {ra0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };

assign perr = 1'b0;

begin : xhdl0
genvar i;
for (i = 0; i <= PORT_BITWIDTH - 1; i = i + 1)
begin : array_gen0
RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D0(
.DPO(dout0[i]),
.SPO(unused_SPO_0),

.A0(addr_w0[0]),
.A1(addr_w0[1]),
.A2(addr_w0[2]),
.A3(addr_w0[3]),
.A4(addr_w0[4]),
.A5(addr_w0[5]),

//.A(addr_w0),
.D(din0[i]),

.DPRA0(addr_r0[0]),
.DPRA1(addr_r0[1]),
.DPRA2(addr_r0[2]),
.DPRA3(addr_r0[3]),
.DPRA4(addr_r0[4]),
.DPRA5(addr_r0[5]),

//.DPRA(addr_r0),
.WCLK(correct_clk),
.WE(wen0)
);

RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D1(
.DPO(dout1[i]),
.SPO(unused_SPO_1),

.A0(addr_w1[0]),
.A1(addr_w1[1]),
.A2(addr_w1[2]),
.A3(addr_w1[3]),
.A4(addr_w1[4]),
.A5(addr_w1[5]),

//.A(addr_w1),
.D(din1[i]),

.DPRA0(addr_r1[0]),
.DPRA1(addr_r1[1]),
.DPRA2(addr_r1[2]),
.DPRA3(addr_r1[3]),
.DPRA4(addr_r1[4]),
.DPRA5(addr_r1[5]),

//.DPRA(addr_r1),
.WCLK(correct_clk),
.WE(wen1)
);


end
end

assign do0_d = (ra0_q[ADDRESSBUS_WIDTH-1]) ? dout1 : dout0;
assign do1_d = (ra1_q[ADDRESSBUS_WIDTH-1]) ? dout1 : dout0;
assign do0 = do0_q;
assign do1 = do1_q;

if (LATCHED_READ == 1'b0)
begin : read_latched_false
always @(*)
begin
re0_q <= re0;
ra0_q <= ra0;
re1_q <= re1;
ra1_q <= ra1;
end
end
if (LATCHED_READ == 1'b1)
begin : read_latched_true
always @(posedge correct_clk)
begin: read_latches
if (correct_clk == 1'b1)
begin
if (reset_q == 1'b1)
begin
re0_q <= 1'b0;
ra0_q <= {ADDRESSBUS_WIDTH{1'b0}};
re1_q <= 1'b0;
ra1_q <= {ADDRESSBUS_WIDTH{1'b0}};
end
else
begin
re0_q <= re0;
ra0_q <= ra0;
re1_q <= re1;
ra1_q <= ra1;
end
end
end
end

if (LATCHED_WRITE == 1'b0)
begin : write_latched_false
always @(*)
begin
we0_q <= we0;
wa0_q <= wa0;
di0_q <= di0;
we1_q <= we1;
wa1_q <= wa1;
di1_q <= di1;
end
end
if (LATCHED_WRITE == 1'b1)
begin : write_latched_true
always @(posedge correct_clk)
begin: write_latches
if (correct_clk == 1'b1)
begin
if (reset_q == 1'b1)
begin
we0_q <= 1'b0;
wa0_q <= {ADDRESSBUS_WIDTH{1'b0}};
di0_q <= {PORT_BITWIDTH{1'b0}};
we1_q <= 1'b0;
wa1_q <= {ADDRESSBUS_WIDTH{1'b0}};
di1_q <= {PORT_BITWIDTH{1'b0}};
end
else
begin
we0_q <= we0;
wa0_q <= wa0;
di0_q <= di0;
we1_q <= we1;
wa1_q <= wa1;
di1_q <= di1;
end
end
end
end

if (LATCHED_READ_DATA == 1'b0)
begin : read_data_latched_false
always @(*)
begin
do0_q <= do0_d;
do1_q <= do1_d;
end
end
if (LATCHED_READ_DATA == 1'b1)
begin : read_data_latched_true
always @(posedge correct_clk)
begin: read_data_latches
if (correct_clk == 1'b1)
begin
if (reset_q == 1'b1)
begin
do0_q <= {PORT_BITWIDTH{1'b0}};
do1_q <= {PORT_BITWIDTH{1'b0}};
end
else
begin
do0_q <= do0_d;
do1_q <= do1_d;
end
end
end
end
endgenerate
endmodule

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