synthesis scripting fixes

Fixed a commented out synthesis-breaking piece of logic related to 'define NCLK_WIDTH = 6, and changed synthesis script to the standard .ys extension

dev/verilog/trilib/tri.vh

@@ -37,7 +37,7 @@
 `define _tri_vh_
 
 // separate clk, rst now
-//`define  NCLK_WIDTH  6   // 0  1xClk, 1  Reset, 2  2xClk, 3  4xClk,  4  Even .5xClk,  5 Odd .5x Clk
+`define  NCLK_WIDTH  6   // 0  1xClk, 1  Reset, 2  2xClk, 3  4xClk,  4  Even .5xClk,  5 Odd .5x Clk
 `define  EXPAND_TYPE  1
 
 // Do NOT add any defines below this line