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rewrite trilib

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pull/18/head
openpowerwtf 2 years ago
parent c2914f2576
commit 4742892965
9 changed files with 88 additions and 192 deletions
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10
dev/verilog/trilib/tri_aoi22_nlats_wlcb.v
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@ -128,10 +128,12 @@ module tri_aoi22_nlats_wlcb(
assign vthold_b = {WIDTH{thold_b}}; assign vthold_b = {WIDTH{thold_b}};
assign vthold = {WIDTH{~thold_b}}; assign vthold = {WIDTH{~thold_b}};



always @(posedge nclk[0]) begin: l
always @(posedge nclk[0]) //int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
begin: l if (sreset)
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); int_dout <= int_din;
else if ((act | force_t) & thold_b)
int_dout <= int_din;
end end


assign qb = (~int_dout); assign qb = (~int_dout);

11
dev/verilog/trilib/tri_inv_nlats.v
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@ -106,11 +106,14 @@ module tri_inv_nlats(
assign vthold_b = {WIDTH{d2clk}}; assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}}; assign vthold = {WIDTH{~d2clk}};



always @(posedge lclk[0]) begin: l
always @(posedge lclk[0]) //int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
begin: l if (sreset)
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); int_dout <= int_din;
else if (d1clk & d2clk)
int_dout <= int_din;
end end

assign qb = (~int_dout); assign qb = (~int_dout);
assign scanout = ZEROS; assign scanout = ZEROS;



10
dev/verilog/trilib/tri_nand2_nlats.v
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@ -106,10 +106,14 @@ module tri_nand2_nlats(
assign vthold_b = {WIDTH{d2clk}}; assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}}; assign vthold = {WIDTH{~d2clk}};


always @(posedge lclk[0]) always @(posedge lclk[0]) begin: l
begin: l //int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); if (sreset)
int_dout <= int_din;
else if (d1clk & d2clk)
int_dout <= int_din;
end end

assign qb = (~int_dout); assign qb = (~int_dout);
assign scanout = ZEROS; assign scanout = ZEROS;



11
dev/verilog/trilib/tri_nlat.v
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@ -107,11 +107,14 @@ module tri_nlat(
assign vthold_b = {WIDTH{d2clk}}; assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}}; assign vthold = {WIDTH{~d2clk}};



always @(posedge lclk[0]) begin: l
always @(posedge lclk[0]) //int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
begin: l if (sreset)
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); int_dout <= int_din;
else if (d1clk & d2clk)
int_dout <= int_din;
end end

assign q = int_dout; assign q = int_dout;
assign q_b = (~int_dout); assign q_b = (~int_dout);
assign scan_out = 1'b0; assign scan_out = 1'b0;

11
dev/verilog/trilib/tri_nlat_scan.v
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@ -106,11 +106,14 @@ module tri_nlat_scan(
assign vthold_b = {WIDTH{d2clk}}; assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}}; assign vthold = {WIDTH{~d2clk}};



always @(posedge lclk[0]) begin: l
always @(posedge lclk[0]) //int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
begin: l if (sreset)
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); int_dout <= int_din;
else if (d1clk & d2clk)
int_dout <= int_din;
end end

assign q = int_dout; assign q = int_dout;
assign q_b = (~int_dout); assign q_b = (~int_dout);
assign scan_out = ZEROS; assign scan_out = ZEROS;

47
dev/verilog/trilib/tri_regk.v
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@ -77,53 +77,28 @@ module tri_regk(
output [OFFSET:OFFSET+WIDTH-1] dout; output [OFFSET:OFFSET+WIDTH-1] dout;


parameter [0:WIDTH-1] init_v = INIT; parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};

// tri_regk


generate generate
begin
wire sreset; wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout; reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire unused; wire unused;


if (NEEDS_SRESET == 1) assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0;
begin : rst
assign sreset = nclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0;
end

assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign int_din = (vsreset_b & din) | (vsreset & init_v);

assign vact = {WIDTH{act | force_t}};
assign vact_b = {WIDTH{~(act | force_t)}};


assign vthold_b = {WIDTH{thold_b}}; always @(posedge nclk[0]) begin: l
assign vthold = {WIDTH{~thold_b}}; if (sreset)

int_dout <= init_v;

else if (act & thold_b)
always @(posedge nclk[0]) int_dout <= din;
begin: l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end end

assign dout = int_dout; assign dout = int_dout;


assign scout = ZEROS; assign scout = {WIDTH{1'b0}};


assign unused = | {vd, gd, nclk, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin}; assign unused = | {vd, gd, nclk, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin} | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]);
end
endgenerate endgenerate

endmodule endmodule

53
dev/verilog/trilib/tri_regs.v
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@ -66,63 +66,26 @@ module tri_regs(
output [OFFSET:OFFSET+WIDTH-1] dout; output [OFFSET:OFFSET+WIDTH-1] dout;


parameter [0:WIDTH-1] init_v = INIT; parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};

// tri_regs


generate generate
begin
wire sreset; wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout; reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire unused; wire unused;


if (NEEDS_SRESET == 1) assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0;
begin : rst
assign sreset = nclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0;
end

assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};

assign int_din = (vsreset_b & int_dout) | (vsreset & init_v);

assign vact = {WIDTH{force_t}};
assign vact_b = {WIDTH{~force_t}};


assign vthold_b = {WIDTH{thold_b}}; always @(posedge nclk[0]) begin: l
assign vthold = {WIDTH{~thold_b}}; if (sreset)

int_dout <= init_v;

always @(posedge nclk[0])
begin: l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end end


if (IBUF == 1'b1) assign dout = (IBUF == 1'b1) ? ~int_dout : int_dout;
begin : cob
assign dout = (~int_dout);
end


if (IBUF == 1'b0) assign scout = {WIDTH{1'b0}};
begin : cnob
assign dout = int_dout;
end


assign scout = ZEROS; assign unused = |{vd, gd, delay_lclkr, scin} | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]);


assign unused = | {vd, gd, nclk, delay_lclkr, scin};
end
endgenerate endgenerate

endmodule endmodule

38
dev/verilog/trilib/tri_rlmlatch_p.v
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@ -71,42 +71,22 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl
(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire unused; wire unused;


if (NEEDS_SRESET == 1) assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0;
begin : rst
assign sreset = nclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0;
end


if (IBUF == 1'b1) assign int_din = IBUF ? ~din : din;
begin : cib
assign int_din = ((~sreset) & (~din)) | (sreset & init_v[0]);
end
if (IBUF == 1'b0)
begin : cnib
assign int_din = ((~sreset) & din) | (sreset & init_v[0]);
end


always @(posedge nclk[0]) always @(posedge nclk[0]) begin: l
begin: l if (sreset) // reset value
int_dout <= ((((act | force_t) & thold_b) | sreset) & int_din) | ((((~act) & (~force_t)) | (~thold_b)) & (~sreset) & int_dout); int_dout <= init_v[0];
else if ((act | force_t) & thold_b) // activate or force, and not clk off
int_dout <= int_din;
end end


if (IBUF == 1'b1) assign dout = IBUF ? ~int_dout : int_dout;
begin : cob
assign dout = (~int_dout);
end

if (IBUF == 1'b0)
begin : cnob
assign dout = int_dout;
end


assign scout = 1'b0; assign scout = 1'b0;


assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd | (|nclk); assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]);


endgenerate endgenerate
endmodule endmodule

59
dev/verilog/trilib/tri_rlmreg_p.v
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@ -67,68 +67,31 @@ module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
parameter [0:WIDTH-1] init_v = INIT; //wtf causes width mismatch warnings; would have to handle both greater and less than 32 bit cases parameter [0:WIDTH-1] init_v = INIT; //wtf causes width mismatch warnings; would have to handle both greater and less than 32 bit cases
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};

// tri_rlmreg_p


generate generate
wire sreset; wire sreset;
wire [0:WIDTH-1] int_din; wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout; reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire [0:WIDTH] unused; wire [0:WIDTH] unused;


if (NEEDS_SRESET == 1) assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0;
begin : rst
assign sreset = nclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0;
end

assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};

if (IBUF == 1'b1)
begin : cib
assign int_din = (vsreset_b & (~din)) | (vsreset & init_v);
end
if (IBUF == 1'b0)
begin : cnib
assign int_din = (vsreset_b & din) | (vsreset & init_v);
end

assign vact = {WIDTH{act | force_t | ALWAYS_ACT == 1}};
assign vact_b = {WIDTH{~(act | force_t | ALWAYS_ACT == 1)}};


assign vthold_b = {WIDTH{thold_b}}; assign int_din = sreset ? init_v : (IBUF == 1'b1) ? ~din : din; //wtf why is sreset needed here??? sim fails w/o it.
assign vthold = {WIDTH{~thold_b}};


always @(posedge nclk[0]) always @(posedge nclk[0]) begin: l
begin: l if (sreset) // reset value
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); int_dout <= init_v;
else if ((act | force_t) & thold_b) // activate or force, and not clk off
int_dout <= int_din;
end end


if (IBUF == 1'b1) assign dout = (IBUF == 1'b1) ? ~int_dout : int_dout;
begin : cob
assign dout = (~int_dout);
end

if (IBUF == 1'b0)
begin : cnob
assign dout = int_dout;
end


assign scout = ZEROS; assign scout = {WIDTH{1'b0}};


assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk); assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]);
assign unused[1:WIDTH] = scin; assign unused[1:WIDTH] = scin;


endgenerate endgenerate

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