microwatt/litesdcard/fusesoc-add-files.py

#!/usr/bin/python3
from fusesoc.capi2.generator import Generator
import os
import sys
import pathlib

class LiteSDCardGenerator(Generator):
    def run(self):
        vendor = self.config.get('vendor')
        clk = self.config.get('frequency')
        vf = vendor + "." + clk

        # Collect a bunch of directory path
        script_dir = os.path.dirname(sys.argv[0])
        gen_dir = os.path.join(script_dir, "generated", vf)

        print("Adding LiteSDCard for vendor... ", vendor)

        # Add files to fusesoc
        files = []
        f = os.path.join(gen_dir, "litesdcard_core.v")
        files.append({f : {'file_type' : 'verilogSource'}})

        self.add_files(files)

g = LiteSDCardGenerator()
g.run()
g.write()
arty_a7: Add litesdcard interface This adds litesdcard.v generated from the litex/litesdcard project, along with logic in top-arty.vhdl to connect it into the system. There is now a DMA wishbone coming in to soc.vhdl which is narrower than the other wishbone masters (it has 32-bit data rather than 64-bit) so there is a widening/narrowing adapter between it and the main wishbone master arbiter. Also, litesdcard generates a non-pipelined wishbone for its DMA connection, which needs to be converted to a pipelined wishbone. We have a latch on both the incoming and outgoing sides of the wishbone in order to help make timing (at the cost of two extra cycles of latency). litesdcard generates an interrupt signal which is wired up to input 3 of the ICS (IRQ 19). Signed-off-by: Paul Mackerras <paulus@ozlabs.org> 4 years ago			`#!/usr/bin/python3`
			`from fusesoc.capi2.generator import Generator`
			`import os`
			`import sys`
			`import pathlib`

			`class LiteSDCardGenerator(Generator):`
			`def run(self):`
litesdcard: Use vendor not board type litesdcard provides a macro per vendor (eg xilinx, lattice) and not per board, so modify the fusesoc generator to take a vendor. This will make it easier to add litesdcard to more boards. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 3 years ago			`vendor = self.config.get('vendor')`
litesdcard: Name targets by vendor.frequency, not just vendor In future we will want to support targets using the same vendor but running at different clock frequencies. Since the clock frequency is a parameter to the gateware generation process, we now name the target directories as "vendor.frequency", i.e., "xilinx.100e6" and "lattice.48e6" rather than "xilinx" and "lattice". Signed-off-by: Paul Mackerras <paulus@ozlabs.org> 8 months ago			`clk = self.config.get('frequency')`
			`vf = vendor + "." + clk`
arty_a7: Add litesdcard interface This adds litesdcard.v generated from the litex/litesdcard project, along with logic in top-arty.vhdl to connect it into the system. There is now a DMA wishbone coming in to soc.vhdl which is narrower than the other wishbone masters (it has 32-bit data rather than 64-bit) so there is a widening/narrowing adapter between it and the main wishbone master arbiter. Also, litesdcard generates a non-pipelined wishbone for its DMA connection, which needs to be converted to a pipelined wishbone. We have a latch on both the incoming and outgoing sides of the wishbone in order to help make timing (at the cost of two extra cycles of latency). litesdcard generates an interrupt signal which is wired up to input 3 of the ICS (IRQ 19). Signed-off-by: Paul Mackerras <paulus@ozlabs.org> 4 years ago
			`# Collect a bunch of directory path`
			`script_dir = os.path.dirname(sys.argv[0])`
litesdcard: Name targets by vendor.frequency, not just vendor In future we will want to support targets using the same vendor but running at different clock frequencies. Since the clock frequency is a parameter to the gateware generation process, we now name the target directories as "vendor.frequency", i.e., "xilinx.100e6" and "lattice.48e6" rather than "xilinx" and "lattice". Signed-off-by: Paul Mackerras <paulus@ozlabs.org> 8 months ago			`gen_dir = os.path.join(script_dir, "generated", vf)`
arty_a7: Add litesdcard interface This adds litesdcard.v generated from the litex/litesdcard project, along with logic in top-arty.vhdl to connect it into the system. There is now a DMA wishbone coming in to soc.vhdl which is narrower than the other wishbone masters (it has 32-bit data rather than 64-bit) so there is a widening/narrowing adapter between it and the main wishbone master arbiter. Also, litesdcard generates a non-pipelined wishbone for its DMA connection, which needs to be converted to a pipelined wishbone. We have a latch on both the incoming and outgoing sides of the wishbone in order to help make timing (at the cost of two extra cycles of latency). litesdcard generates an interrupt signal which is wired up to input 3 of the ICS (IRQ 19). Signed-off-by: Paul Mackerras <paulus@ozlabs.org> 4 years ago
litesdcard: Use vendor not board type litesdcard provides a macro per vendor (eg xilinx, lattice) and not per board, so modify the fusesoc generator to take a vendor. This will make it easier to add litesdcard to more boards. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 3 years ago			`print("Adding LiteSDCard for vendor... ", vendor)`
arty_a7: Add litesdcard interface This adds litesdcard.v generated from the litex/litesdcard project, along with logic in top-arty.vhdl to connect it into the system. There is now a DMA wishbone coming in to soc.vhdl which is narrower than the other wishbone masters (it has 32-bit data rather than 64-bit) so there is a widening/narrowing adapter between it and the main wishbone master arbiter. Also, litesdcard generates a non-pipelined wishbone for its DMA connection, which needs to be converted to a pipelined wishbone. We have a latch on both the incoming and outgoing sides of the wishbone in order to help make timing (at the cost of two extra cycles of latency). litesdcard generates an interrupt signal which is wired up to input 3 of the ICS (IRQ 19). Signed-off-by: Paul Mackerras <paulus@ozlabs.org> 4 years ago
			`# Add files to fusesoc`
			`files = []`
			`f = os.path.join(gen_dir, "litesdcard_core.v")`
			`files.append({f : {'file_type' : 'verilogSource'}})`

			`self.add_files(files)`

			`g = LiteSDCardGenerator()`
			`g.run()`
			`g.write()`