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--
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-- Set associative icache
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--
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-- TODO (in no specific order):
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--
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-- * Add debug interface to inspect cache content
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-- * Add snoop/invalidate path
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-- * Add multi-hit error detection
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-- * Pipelined bus interface (wb or axi)
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-- * Maybe add parity ? There's a few bits free in each BRAM row on Xilinx
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-- * Add optimization: service hits on partially loaded lines
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-- * Add optimization: (maybe) interrupt reload on fluch/redirect
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-- * Check if playing with the geometry of the cache tags allow for more
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-- efficient use of distributed RAM and less logic/muxes. Currently we
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-- write TAG_BITS width which may not match full ram blocks and might
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-- cause muxes to be inferred for "partial writes".
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-- * Check if making the read size of PLRU a ROM helps utilization
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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-- 64 bit direct mapped icache. All instructions are 4B aligned.
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entity icache is
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generic (
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-- Line size in bytes
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LINE_SIZE : positive := 64;
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-- Number of lines in a set
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NUM_LINES : positive := 32;
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-- Number of ways
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NUM_WAYS : positive := 4
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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i_in : in Fetch1ToIcacheType;
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i_out : out IcacheToFetch2Type;
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stall_out : out std_ulogic;
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flush_in : in std_ulogic;
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wishbone_out : out wishbone_master_out;
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wishbone_in : in wishbone_slave_out
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);
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end entity icache;
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architecture rtl of icache is
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function log2(i : natural) return integer is
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variable tmp : integer := i;
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variable ret : integer := 0;
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begin
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while tmp > 1 loop
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ret := ret + 1;
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tmp := tmp / 2;
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end loop;
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return ret;
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end function;
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function ispow2(i : integer) return boolean is
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begin
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if to_integer(to_unsigned(i, 32) and to_unsigned(i - 1, 32)) = 0 then
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return true;
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else
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return false;
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end if;
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end function;
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-- BRAM organisation: We never access more than wishbone_data_bits at
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-- a time so to save resources we make the array only that wide, and
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-- use consecutive indices for to make a cache "line"
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--
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-- ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
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constant ROW_SIZE : natural := wishbone_data_bits / 8;
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-- ROW_PER_LINE is the number of row (wishbone transactions) in a line
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constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
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-- BRAM_ROWS is the number of rows in BRAM needed to represent the full
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-- icache
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constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
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-- INSN_PER_ROW is the number of 32bit instructions per BRAM row
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constant INSN_PER_ROW : natural := wishbone_data_bits / 32;
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-- Bit fields counts in the address
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-- INSN_BITS is the number of bits to select an instruction in a row
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constant INSN_BITS : natural := log2(INSN_PER_ROW);
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-- ROW_BITS is the number of bits to select a row
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constant ROW_BITS : natural := log2(BRAM_ROWS);
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-- ROW_LINEBITS is the number of bits to select a row within a line
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constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
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-- LINE_OFF_BITS is the number of bits for the offset in a cache line
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constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
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-- ROW_OFF_BITS is the number of bits for the offset in a row
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constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
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-- INDEX_BITS is the number if bits to select a cache line
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constant INDEX_BITS : natural := log2(NUM_LINES);
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-- TAG_BITS is the number of bits of the tag part of the address
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constant TAG_BITS : natural := 64 - LINE_OFF_BITS - INDEX_BITS;
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-- WAY_BITS is the number of bits to select a way
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constant WAY_BITS : natural := log2(NUM_WAYS);
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-- Example of layout for 32 lines of 64 bytes:
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--
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-- .. tag |index| line |
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-- .. | row | |
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-- .. | | | |00| zero (2)
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-- .. | | |-| | INSN_BITS (1)
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-- .. | |---| | ROW_LINEBITS (3)
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-- .. | |--- - --| LINE_OFF_BITS (6)
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-- .. | |- --| ROW_OFF_BITS (3)
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-- .. |----- ---| | ROW_BITS (8)
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-- .. |-----| | INDEX_BITS (5)
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-- .. --------| | TAG_BITS (53)
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subtype row_t is integer range 0 to BRAM_ROWS-1;
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subtype index_t is integer range 0 to NUM_LINES-1;
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subtype way_t is integer range 0 to NUM_WAYS-1;
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-- The cache data BRAM organized as described above for each way
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subtype cache_row_t is std_ulogic_vector(wishbone_data_bits-1 downto 0);
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-- The cache tags LUTRAM has a row per set. Vivado is a pain and will
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-- not handle a clean (commented) definition of the cache tags as a 3d
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-- memory. For now, work around it by putting all the tags
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subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
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-- type cache_tags_set_t is array(way_t) of cache_tag_t;
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-- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
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constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
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subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
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type cache_tags_array_t is array(index_t) of cache_tags_set_t;
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-- The cache valid bits
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subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
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type cache_valids_t is array(index_t) of cache_way_valids_t;
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-- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
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signal cache_tags : cache_tags_array_t;
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signal cache_valids : cache_valids_t;
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attribute ram_style : string;
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attribute ram_style of cache_tags : signal is "distributed";
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-- Cache reload state machine
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type state_t is (IDLE, WAIT_ACK);
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type reg_internal_t is record
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-- Cache hit state (Latches for 1 cycle BRAM access)
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hit_way : way_t;
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hit_nia : std_ulogic_vector(63 downto 0);
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hit_smark : std_ulogic;
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hit_valid : std_ulogic;
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-- Cache miss state (reload state machine)
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state : state_t;
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wb : wishbone_master_out;
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store_way : way_t;
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store_index : index_t;
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end record;
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signal r : reg_internal_t;
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-- Async signals on incoming request
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signal req_index : index_t;
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signal req_row : row_t;
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signal req_hit_way : way_t;
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signal req_tag : cache_tag_t;
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signal req_is_hit : std_ulogic;
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signal req_is_miss : std_ulogic;
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-- Cache RAM interface
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type cache_ram_out_t is array(way_t) of cache_row_t;
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signal cache_out : cache_ram_out_t;
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-- PLRU output interface
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type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
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signal plru_victim : plru_out_t;
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-- Return the cache line index (tag index) for an address
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function get_index(addr: std_ulogic_vector(63 downto 0)) return index_t is
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begin
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return to_integer(unsigned(addr(63-TAG_BITS downto LINE_OFF_BITS)));
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end;
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-- Return the cache row index (data memory) for an address
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function get_row(addr: std_ulogic_vector(63 downto 0)) return row_t is
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begin
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return to_integer(unsigned(addr(63-TAG_BITS downto ROW_OFF_BITS)));
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end;
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-- Returns whether this is the last row of a line
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function is_last_row(addr: std_ulogic_vector(63 downto 0)) return boolean is
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constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
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begin
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return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones;
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end;
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-- Return the address of the next row in the current cache line
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function next_row_addr(addr: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
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variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
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variable result : std_ulogic_vector(63 downto 0);
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begin
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-- Is there no simpler way in VHDL to generate that 3 bits adder ?
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row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
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row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
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result := addr;
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result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
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return result;
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end;
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-- Read the instruction word for the given address in the current cache row
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function read_insn_word(addr: std_ulogic_vector(63 downto 0);
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data: cache_row_t) return std_ulogic_vector is
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variable word: integer range 0 to INSN_PER_ROW-1;
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begin
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word := to_integer(unsigned(addr(INSN_BITS+2-1 downto 2)));
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return data(31+word*32 downto word*32);
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end;
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-- Get the tag value from the address
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function get_tag(addr: std_ulogic_vector(63 downto 0)) return cache_tag_t is
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begin
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return addr(63 downto 64-TAG_BITS);
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end;
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-- Read a tag from a tag memory row
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function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
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begin
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return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
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end;
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-- Write a tag to tag memory row
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procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t;
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tag: cache_tag_t) is
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begin
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tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
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end;
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begin
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assert LINE_SIZE mod ROW_SIZE = 0;
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assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
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assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
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assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
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assert ispow2(INSN_PER_ROW) report "INSN_PER_ROW not power of 2" severity FAILURE;
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assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
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report "geometry bits don't add up" severity FAILURE;
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assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
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report "geometry bits don't add up" severity FAILURE;
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assert (64 = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
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report "geometry bits don't add up" severity FAILURE;
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assert (64 = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
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report "geometry bits don't add up" severity FAILURE;
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debug: process
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begin
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report "ROW_SIZE = " & natural'image(ROW_SIZE);
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report "ROW_PER_LINE = " & natural'image(ROW_PER_LINE);
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report "BRAM_ROWS = " & natural'image(BRAM_ROWS);
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report "INSN_PER_ROW = " & natural'image(INSN_PER_ROW);
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report "INSN_BITS = " & natural'image(INSN_BITS);
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report "ROW_BITS = " & natural'image(ROW_BITS);
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report "ROW_LINEBITS = " & natural'image(ROW_LINEBITS);
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report "LINE_OFF_BITS = " & natural'image(LINE_OFF_BITS);
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report "ROW_OFF_BITS = " & natural'image(ROW_OFF_BITS);
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report "INDEX_BITS = " & natural'image(INDEX_BITS);
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report "TAG_BITS = " & natural'image(TAG_BITS);
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report "WAY_BITS = " & natural'image(WAY_BITS);
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wait;
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end process;
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-- Generate a cache RAM for each way
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rams: for i in 0 to NUM_WAYS-1 generate
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signal do_read : std_ulogic;
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signal do_write : std_ulogic;
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signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
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signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
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signal dout : cache_row_t;
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begin
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way: entity work.cache_ram
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generic map (
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ROW_BITS => ROW_BITS,
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WIDTH => wishbone_data_bits
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)
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port map (
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clk => clk,
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rd_en => do_read,
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rd_addr => rd_addr,
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rd_data => dout,
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wr_en => do_write,
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wr_sel => (others => '1'),
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wr_addr => wr_addr,
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wr_data => wishbone_in.dat
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);
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process(all)
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begin
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do_read <= '1';
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do_write <= '0';
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if wishbone_in.ack = '1' and r.store_way = i then
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do_write <= '1';
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end if;
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cache_out(i) <= dout;
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rd_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
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wr_addr <= std_ulogic_vector(to_unsigned(get_row(r.wb.adr), ROW_BITS));
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end process;
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end generate;
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|
|
|
|
|
|
-- Generate PLRUs
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|
maybe_plrus: if NUM_WAYS > 1 generate
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begin
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plrus: for i in 0 to NUM_LINES-1 generate
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-- PLRU interface
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signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
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signal plru_acc_en : std_ulogic;
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signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
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begin
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plru : entity work.plru
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generic map (
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BITS => WAY_BITS
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)
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port map (
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clk => clk,
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rst => rst,
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acc => plru_acc,
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acc_en => plru_acc_en,
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lru => plru_out
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);
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process(req_index, req_is_hit, req_hit_way, req_is_hit, plru_out)
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|
|
begin
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|
|
-- PLRU interface
|
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|
|
if req_is_hit = '1' and req_index = i then
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|
plru_acc_en <= req_is_hit;
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|
else
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|
|
plru_acc_en <= '0';
|
|
|
|
end if;
|
|
|
|
plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS));
|
|
|
|
plru_victim(i) <= plru_out;
|
|
|
|
end process;
|
|
|
|
end generate;
|
|
|
|
end generate;
|
|
|
|
|
|
|
|
-- Cache hit detection, output to fetch2 and other misc logic
|
|
|
|
icache_comb : process(all)
|
|
|
|
variable is_hit : std_ulogic;
|
|
|
|
variable hit_way : way_t;
|
|
|
|
begin
|
|
|
|
-- Extract line, row and tag from request
|
|
|
|
req_index <= get_index(i_in.nia);
|
|
|
|
req_row <= get_row(i_in.nia);
|
|
|
|
req_tag <= get_tag(i_in.nia);
|
|
|
|
|
|
|
|
-- Test if pending request is a hit on any way
|
|
|
|
hit_way := 0;
|
|
|
|
is_hit := '0';
|
|
|
|
for i in way_t loop
|
|
|
|
if i_in.req = '1' and cache_valids(req_index)(i) = '1' then
|
|
|
|
if read_tag(i, cache_tags(req_index)) = req_tag then
|
|
|
|
hit_way := i;
|
|
|
|
is_hit := '1';
|
|
|
|
end if;
|
|
|
|
end if;
|
|
|
|
end loop;
|
|
|
|
|
|
|
|
-- Generate the "hit" and "miss" signals for the synchronous blocks
|
|
|
|
req_is_hit <= i_in.req and is_hit and not flush_in;
|
|
|
|
req_is_miss <= i_in.req and not is_hit and not flush_in;
|
|
|
|
req_hit_way <= hit_way;
|
|
|
|
|
|
|
|
-- Output instruction from current cache row
|
|
|
|
--
|
|
|
|
-- Note: This is a mild violation of our design principle of having pipeline
|
|
|
|
-- stages output from a clean latch. In this case we output the result
|
|
|
|
-- of a mux. The alternative would be output an entire row which
|
|
|
|
-- I prefer not to do just yet as it would force fetch2 to know about
|
|
|
|
-- some of the cache geometry information.
|
|
|
|
--
|
|
|
|
i_out.insn <= read_insn_word(r.hit_nia, cache_out(r.hit_way));
|
|
|
|
i_out.valid <= r.hit_valid;
|
|
|
|
i_out.nia <= r.hit_nia;
|
|
|
|
i_out.stop_mark <= r.hit_smark;
|
|
|
|
|
|
|
|
-- Stall fetch1 if we have a miss
|
|
|
|
stall_out <= not is_hit;
|
|
|
|
|
|
|
|
-- Wishbone requests output (from the cache miss reload machine)
|
|
|
|
wishbone_out <= r.wb;
|
|
|
|
end process;
|
|
|
|
|
|
|
|
-- Cache hit synchronous machine
|
|
|
|
icache_hit : process(clk)
|
|
|
|
begin
|
|
|
|
if rising_edge(clk) then
|
|
|
|
-- On a hit, latch the request for the next cycle, when the BRAM data
|
|
|
|
-- will be available on the cache_out output of the corresponding way
|
|
|
|
--
|
|
|
|
if req_is_hit = '1' then
|
|
|
|
r.hit_way <= req_hit_way;
|
|
|
|
r.hit_nia <= i_in.nia;
|
|
|
|
r.hit_smark <= i_in.stop_mark;
|
|
|
|
r.hit_valid <= '1';
|
|
|
|
|
|
|
|
report "cache hit nia:" & to_hstring(i_in.nia) &
|
|
|
|
" SM:" & std_ulogic'image(i_in.stop_mark) &
|
|
|
|
" idx:" & integer'image(req_index) &
|
|
|
|
" tag:" & to_hstring(req_tag) &
|
|
|
|
" way: " & integer'image(req_hit_way);
|
|
|
|
else
|
|
|
|
r.hit_valid <= '0';
|
|
|
|
|
|
|
|
-- Send stop marks down regardless of validity
|
|
|
|
r.hit_smark <= i_in.stop_mark;
|
|
|
|
end if;
|
|
|
|
end if;
|
|
|
|
end process;
|
|
|
|
|
|
|
|
-- Cache miss/reload synchronous machine
|
|
|
|
icache_miss : process(clk)
|
|
|
|
variable way : integer range 0 to NUM_WAYS-1;
|
|
|
|
variable tagset : cache_tags_set_t;
|
|
|
|
begin
|
|
|
|
if rising_edge(clk) then
|
|
|
|
-- On reset, clear all valid bits to force misses
|
|
|
|
if rst = '1' then
|
|
|
|
for i in index_t loop
|
|
|
|
cache_valids(i) <= (others => '0');
|
|
|
|
end loop;
|
|
|
|
r.state <= IDLE;
|
|
|
|
r.wb.cyc <= '0';
|
|
|
|
r.wb.stb <= '0';
|
|
|
|
|
|
|
|
-- We only ever do reads on wishbone
|
|
|
|
r.wb.dat <= (others => '0');
|
|
|
|
r.wb.sel <= "11111111";
|
|
|
|
r.wb.we <= '0';
|
|
|
|
|
|
|
|
-- Not useful normally but helps avoiding tons of sim warnings
|
|
|
|
r.wb.adr <= (others => '0');
|
|
|
|
else
|
|
|
|
-- Main state machine
|
|
|
|
case r.state is
|
|
|
|
when IDLE =>
|
|
|
|
-- We need to read a cache line
|
|
|
|
if req_is_miss = '1' then
|
|
|
|
way := to_integer(unsigned(plru_victim(req_index)));
|
|
|
|
|
|
|
|
report "cache miss nia:" & to_hstring(i_in.nia) &
|
|
|
|
" SM:" & std_ulogic'image(i_in.stop_mark) &
|
|
|
|
" idx:" & integer'image(req_index) &
|
|
|
|
" way:" & integer'image(way) &
|
|
|
|
" tag:" & to_hstring(req_tag);
|
|
|
|
|
|
|
|
-- Force misses on that way while reloading that line
|
|
|
|
cache_valids(req_index)(way) <= '0';
|
|
|
|
|
|
|
|
-- Store new tag in selected way
|
|
|
|
for i in 0 to NUM_WAYS-1 loop
|
|
|
|
if i = way then
|
|
|
|
tagset := cache_tags(req_index);
|
|
|
|
write_tag(i, tagset, req_tag);
|
|
|
|
cache_tags(req_index) <= tagset;
|
|
|
|
end if;
|
|
|
|
end loop;
|
|
|
|
|
|
|
|
-- Keep track of our index and way for subsequent stores
|
|
|
|
r.store_index <= req_index;
|
|
|
|
r.store_way <= way;
|
|
|
|
|
|
|
|
-- Prep for first wishbone read. We calculate the address of
|
|
|
|
-- the start of the cache line
|
|
|
|
--
|
|
|
|
r.wb.adr <= i_in.nia(63 downto LINE_OFF_BITS) &
|
|
|
|
(LINE_OFF_BITS-1 downto 0 => '0');
|
|
|
|
r.wb.cyc <= '1';
|
|
|
|
r.wb.stb <= '1';
|
|
|
|
|
|
|
|
r.state <= WAIT_ACK;
|
|
|
|
end if;
|
|
|
|
when WAIT_ACK =>
|
|
|
|
if wishbone_in.ack = '1' then
|
|
|
|
-- That was the last word ? We are done
|
|
|
|
if is_last_row(r.wb.adr) then
|
|
|
|
cache_valids(r.store_index)(way) <= '1';
|
|
|
|
r.wb.cyc <= '0';
|
|
|
|
r.wb.stb <= '0';
|
|
|
|
r.state <= IDLE;
|
|
|
|
else
|
|
|
|
-- Otherwise, calculate the next row address
|
|
|
|
r.wb.adr <= next_row_addr(r.wb.adr);
|
|
|
|
end if;
|
|
|
|
end if;
|
|
|
|
end case;
|
|
|
|
end if;
|
|
|
|
end if;
|
|
|
|
end process;
|
|
|
|
end;
|