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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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-- 64 bit direct mapped icache. All instructions are 4B aligned.
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entity icache is
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generic (
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-- Line size in 64bit doublewords
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LINE_SIZE_DW : natural := 8;
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-- Number of lines
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NUM_LINES : natural := 32
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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i_in : in Fetch1ToIcacheType;
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i_out : out IcacheToFetch2Type;
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stall_out : out std_ulogic;
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flush_in : in std_ulogic;
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wishbone_out : out wishbone_master_out;
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wishbone_in : in wishbone_slave_out
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);
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end entity icache;
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architecture rtl of icache is
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function log2(i : natural) return integer is
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variable tmp : integer := i;
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variable ret : integer := 0;
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begin
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while tmp > 1 loop
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ret := ret + 1;
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tmp := tmp / 2;
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end loop;
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return ret;
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end function;
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function ispow2(i : integer) return boolean is
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begin
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if to_integer(to_unsigned(i, 32) and to_unsigned(i - 1, 32)) = 0 then
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return true;
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else
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return false;
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end if;
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end function;
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constant LINE_SIZE : natural := LINE_SIZE_DW*8;
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constant OFFSET_BITS : natural := log2(LINE_SIZE);
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constant INDEX_BITS : natural := log2(NUM_LINES);
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constant TAG_BITS : natural := 64 - OFFSET_BITS - INDEX_BITS;
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subtype cacheline_type is std_logic_vector((LINE_SIZE*8)-1 downto 0);
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type cacheline_array is array(0 to NUM_LINES-1) of cacheline_type;
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subtype cacheline_tag_type is std_logic_vector(TAG_BITS-1 downto 0);
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type cacheline_tag_array is array(0 to NUM_LINES-1) of cacheline_tag_type;
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-- Storage. Hopefully "cachelines" is a BRAM, the rest is LUTs
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signal cachelines : cacheline_array;
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signal tags : cacheline_tag_array;
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signal tags_valid : std_ulogic_vector(NUM_LINES-1 downto 0);
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attribute ram_style : string;
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attribute ram_style of cachelines : signal is "block";
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attribute ram_decomp : string;
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attribute ram_decomp of cachelines : signal is "power";
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-- Cache reload state machine
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type state_type is (IDLE, WAIT_ACK);
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type reg_internal_type is record
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-- Cache hit state (1 cycle BRAM access)
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hit_line : cacheline_type;
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hit_nia : std_ulogic_vector(63 downto 0);
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hit_smark : std_ulogic;
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hit_valid : std_ulogic;
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-- Cache miss state (reload state machine)
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state : state_type;
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wb : wishbone_master_out;
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store_index : integer range 0 to (NUM_LINES-1);
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store_mask : std_ulogic_vector(LINE_SIZE_DW-1 downto 0);
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end record;
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signal r : reg_internal_type;
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-- Async signals decoding incoming requests
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signal req_index : integer range 0 to NUM_LINES-1;
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signal req_tag : std_ulogic_vector(TAG_BITS-1 downto 0);
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signal req_word : integer range 0 to LINE_SIZE_DW*2-1;
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signal req_is_hit : std_ulogic;
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-- Return the cache line index (tag index) for an address
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function get_index(addr: std_ulogic_vector(63 downto 0)) return integer is
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begin
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return to_integer(unsigned(addr((OFFSET_BITS+INDEX_BITS-1) downto OFFSET_BITS)));
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end;
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-- Return the word index in a cache line for an address
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function get_word(addr: std_ulogic_vector(63 downto 0)) return integer is
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begin
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return to_integer(unsigned(addr(OFFSET_BITS-1 downto 2)));
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end;
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-- Read a word in a cache line for an address
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function read_word(word: integer; data: cacheline_type) return std_ulogic_vector is
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begin
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return data((word+1)*32-1 downto word*32);
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end;
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-- Calculate the tag value from the address
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function get_tag(addr: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
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begin
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return addr(63 downto OFFSET_BITS+INDEX_BITS);
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end;
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begin
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assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
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assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
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icache_comb : process(all)
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begin
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-- Calculate next index and tag index
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req_index <= get_index(i_in.nia);
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req_tag <= get_tag(i_in.nia);
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req_word <= get_word(i_in.nia);
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-- Test if pending request is a hit
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if tags(req_index) = req_tag then
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req_is_hit <= tags_valid(req_index);
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else
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req_is_hit <= '0';
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end if;
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-- Output instruction from current cache line
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--
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-- Note: This is a mild violation of our design principle of having pipeline
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-- stages output from a clean latch. In this case we output the result
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-- of a mux. The alternative would be output an entire cache line
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-- which I prefer not to do just yet.
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--
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i_out.valid <= r.hit_valid;
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i_out.insn <= read_word(get_word(r.hit_nia), r.hit_line);
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i_out.nia <= r.hit_nia;
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i_out.stop_mark <= r.hit_smark;
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-- This needs to match the latching of a new request in icache_hit
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stall_out <= not req_is_hit;
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-- Wishbone requests output (from the cache miss reload machine)
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wishbone_out <= r.wb;
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end process;
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icache_hit : process(clk)
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begin
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if rising_edge(clk) then
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-- Assume we have nothing valid first
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r.hit_valid <= '0';
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-- Are we free to latch a new request ?
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--
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-- Note: this test needs to match the equation for generating stall_out
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--
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if i_in.req = '1' and req_is_hit = '1' and flush_in = '0' then
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-- Read the cache line (BRAM read port) and remember the NIA
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r.hit_line <= cachelines(req_index);
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r.hit_nia <= i_in.nia;
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r.hit_smark <= i_in.stop_mark;
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r.hit_valid <= '1';
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report "cache hit nia:" & to_hstring(i_in.nia) &
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" SM:" & std_ulogic'image(i_in.stop_mark) &
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" idx:" & integer'image(req_index) &
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" tag:" & to_hstring(req_tag);
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end if;
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-- Flush requested ? discard...
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if flush_in then
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r.hit_valid <= '0';
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end if;
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end if;
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end process;
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icache_miss : process(clk)
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variable store_dword : std_ulogic_vector(OFFSET_BITS-4 downto 0);
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begin
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if rising_edge(clk) then
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if rst = '1' then
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tags_valid <= (others => '0');
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r.store_mask <= (others => '0');
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r.state <= IDLE;
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r.wb.cyc <= '0';
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r.wb.stb <= '0';
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-- We only ever do reads on wishbone
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r.wb.dat <= (others => '0');
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r.wb.sel <= "11111111";
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r.wb.we <= '0';
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end if;
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-- State machine
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case r.state is
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when IDLE =>
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-- We need to read a cache line
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if i_in.req = '1' and req_is_hit = '0' then
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report "cache miss nia:" & to_hstring(i_in.nia) &
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" SM:" & std_ulogic'image(i_in.stop_mark) &
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" idx:" & integer'image(req_index) &
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" tag:" & to_hstring(req_tag);
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r.state <= WAIT_ACK;
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r.store_mask <= (0 => '1', others => '0');
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r.store_index <= req_index;
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-- Force misses while reloading that line
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tags_valid(req_index) <= '0';
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tags(req_index) <= req_tag;
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-- Prep for first dword read
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r.wb.adr <= i_in.nia(63 downto OFFSET_BITS) & (OFFSET_BITS-1 downto 0 => '0');
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r.wb.cyc <= '1';
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r.wb.stb <= '1';
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end if;
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when WAIT_ACK =>
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if wishbone_in.ack = '1' then
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-- Store the current dword in both the cache
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for i in 0 to LINE_SIZE_DW-1 loop
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if r.store_mask(i) = '1' then
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cachelines(r.store_index)(63 + i*64 downto i*64) <= wishbone_in.dat;
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end if;
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end loop;
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-- That was the last word ? We are done
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if r.store_mask(LINE_SIZE_DW-1) = '1' then
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r.state <= IDLE;
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tags_valid(r.store_index) <= '1';
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r.wb.cyc <= '0';
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r.wb.stb <= '0';
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else
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store_dword := r.wb.adr(OFFSET_BITS-1 downto 3);
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store_dword := std_ulogic_vector(unsigned(store_dword) + 1);
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r.wb.adr(OFFSET_BITS-1 downto 3) <= store_dword;
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end if;
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-- Advance to next word
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r.store_mask <= r.store_mask(LINE_SIZE_DW-2 downto 0) & '0';
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end if;
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end case;
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end if;
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end process;
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end;
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