Stores need to wait for wishbone write ack

I wasn't waiting to get a wishbone ack back on stores before continuing.
This creates all sorts of problems when we add pipelining and send
loads and stores down the pipe faster.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

loadstore2.vhdl

@@ -81,16 +81,15 @@ begin
 					m_tmp.cyc <= '1';
 					m_tmp.stb <= '1';
 
+					l_saved <= l_in;
+
 					if l_in.load = '1' then
 						m_tmp.we <= '0';
 
-						l_saved <= l_in;
 						state <= WAITING_FOR_READ_ACK;
 					else
 						m_tmp.we <= '1';
 
-						w_tmp.valid <= '1';
-
 						data := l_in.data;
 						if l_in.byte_reverse = '1' then
 							data := byte_reverse(data, to_integer(unsigned(l_in.length)));
@@ -100,12 +99,6 @@ begin
 
 						assert l_in.sign_extend = '0' report "sign extension doesn't make sense for stores" severity failure;
 
-						if l_in.update = '1' then
-							w_tmp.write_enable <= '1';
-							w_tmp.write_reg <= l_in.update_reg;
-							w_tmp.write_data <= l_in.addr;
-						end if;
-
 						state <= WAITING_FOR_WRITE_ACK;
 					end if;
 				end if;
@@ -154,6 +147,13 @@ begin
 
 			when WAITING_FOR_WRITE_ACK =>
 				if m_in.ack = '1' then
+					w_tmp.valid <= '1';
+					if l_saved.update = '1' then
+						w_tmp.write_enable <= '1';
+						w_tmp.write_reg <= l_saved.update_reg;
+						w_tmp.write_data <= l_saved.addr;
+					end if;
+
 					m_tmp <= wishbone_master_out_init;
 					state <= IDLE;
 				end if;