liteeth: Update yaml config

csr_data_width is no longer required. Add ntxslots and nrxslots parameters but set them to the default value. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago · 12efb51bcc
parent 458dfe01a6
commit 12efb51bcc
2 changed files with 4 additions and 2 deletions
--- a/liteeth/gen-src/arty.yml
+++ b/liteeth/gen-src/arty.yml
@ -8,8 +8,9 @@ vendor:     xilinx
 clk_freq:   100e6
 core:       wishbone
 endianness: little
+ntxslots:   2
+nrxslots:   2

 soc:
    mem_map:
        ethmac: 0x00010000
-    csr_data_width: 32
--- a/liteeth/gen-src/nexys-video.yml
+++ b/liteeth/gen-src/nexys-video.yml
@ -8,8 +8,9 @@ vendor:     xilinx
 clk_freq:   125e6
 core:       wishbone
 endianness: little
+ntxslots:   2
+nrxslots:   2

 soc:
    mem_map:
        ethmac: 0x00010000
-    csr_data_width: 32