pp_soc_uart: Fix rx synchronizers and ensure stable tx init state

The rx synchronizers were ... non existent. Someone forgot to add
a if rising_edge(clk) to the process.

For tx, ensure that we have a default value so that TX stays high
from TPGA configuration to the reset being sampled on the first clock
cycle.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
pull/177/head
Benjamin Herrenschmidt 4 years ago
parent bd42580a42
commit 13e84b0bbb

@ -111,6 +111,7 @@ architecture behaviour of pp_soc_uart is


signal rxd2 : std_logic := '1'; signal rxd2 : std_logic := '1';
signal rxd3 : std_logic := '1'; signal rxd3 : std_logic := '1';
signal txd2 : std_ulogic := '1';
begin begin


irq <= (irq_recv_enable and (not recv_buffer_empty)) irq <= (irq_recv_enable and (not recv_buffer_empty))
@ -123,9 +124,12 @@ begin
-- Add a few FFs on the RX input to avoid metastability issues -- Add a few FFs on the RX input to avoid metastability issues
process (clk) is process (clk) is
begin begin
rxd3 <= rxd2; if rising_edge(clk) then
rxd2 <= rxd; rxd3 <= rxd2;
rxd2 <= rxd;
end if;
end process; end process;
txd <= txd2;


uart_receive: process(clk) uart_receive: process(clk)
begin begin
@ -202,7 +206,7 @@ begin
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if reset = '1' then if reset = '1' then
txd <= '1'; txd2 <= '1';
tx_state <= IDLE; tx_state <= IDLE;
send_buffer_pop <= '0'; send_buffer_pop <= '0';
tx_current_bit <= 0; tx_current_bit <= 0;
@ -210,26 +214,26 @@ begin
case tx_state is case tx_state is
when IDLE => when IDLE =>
if send_buffer_empty = '0' and uart_tx_clk = '1' then if send_buffer_empty = '0' and uart_tx_clk = '1' then
txd <= '0'; txd2 <= '0';
send_buffer_pop <= '1'; send_buffer_pop <= '1';
tx_current_bit <= 0; tx_current_bit <= 0;
tx_state <= TRANSMIT; tx_state <= TRANSMIT;
elsif uart_tx_clk = '1' then elsif uart_tx_clk = '1' then
txd <= '1'; txd2 <= '1';
end if; end if;
when TRANSMIT => when TRANSMIT =>
if send_buffer_pop = '1' then if send_buffer_pop = '1' then
send_buffer_pop <= '0'; send_buffer_pop <= '0';
elsif uart_tx_clk = '1' and tx_current_bit = 7 then elsif uart_tx_clk = '1' and tx_current_bit = 7 then
txd <= tx_byte(tx_current_bit); txd2 <= tx_byte(tx_current_bit);
tx_state <= STOPBIT; tx_state <= STOPBIT;
elsif uart_tx_clk = '1' then elsif uart_tx_clk = '1' then
txd <= tx_byte(tx_current_bit); txd2 <= tx_byte(tx_current_bit);
tx_current_bit <= tx_current_bit + 1; tx_current_bit <= tx_current_bit + 1;
end if; end if;
when STOPBIT => when STOPBIT =>
if uart_tx_clk = '1' then if uart_tx_clk = '1' then
txd <= '1'; txd2 <= '1';
tx_state <= IDLE; tx_state <= IDLE;
end if; end if;
end case; end case;

Loading…
Cancel
Save