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Reformat simple_ram_behavioural

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/64/head
Anton Blanchard 5 years ago committed by Anton Blanchard
parent fd9e971b2c
commit 1d5e8c2eb4
3 changed files with 301 additions and 293 deletions
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114
simple_ram_behavioural.vhdl
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@ -8,70 +8,70 @@ use work.wishbone_types.all;
use work.simple_ram_behavioural_helpers.all; use work.simple_ram_behavioural_helpers.all;


entity mw_soc_memory is entity mw_soc_memory is
generic ( generic (
RAM_INIT_FILE : string; RAM_INIT_FILE : string;
MEMORY_SIZE : integer MEMORY_SIZE : integer
); );


port ( port (
clk : in std_ulogic; clk : in std_ulogic;
rst : in std_ulogic; rst : in std_ulogic;


wishbone_in : in wishbone_master_out; wishbone_in : in wishbone_master_out;
wishbone_out : out wishbone_slave_out wishbone_out : out wishbone_slave_out
); );
end mw_soc_memory; end mw_soc_memory;


architecture behave of mw_soc_memory is architecture behave of mw_soc_memory is
type wishbone_state_t is (IDLE, ACK); type wishbone_state_t is (IDLE, ACK);


signal state : wishbone_state_t := IDLE; signal state : wishbone_state_t := IDLE;
signal ret_ack : std_ulogic := '0'; signal ret_ack : std_ulogic := '0';
signal identifier : integer := behavioural_initialize(filename => RAM_INIT_FILE, size => MEMORY_SIZE); signal identifier : integer := behavioural_initialize(filename => RAM_INIT_FILE, size => MEMORY_SIZE);
signal reload : integer := 0; signal reload : integer := 0;
begin begin
wishbone_process: process(clk) wishbone_process: process(clk)
variable ret_dat: std_ulogic_vector(63 downto 0) := (others => '0'); variable ret_dat: std_ulogic_vector(63 downto 0) := (others => '0');
begin begin
wishbone_out.ack <= ret_ack and wishbone_in.cyc and wishbone_in.stb; wishbone_out.ack <= ret_ack and wishbone_in.cyc and wishbone_in.stb;
wishbone_out.dat <= ret_dat; wishbone_out.dat <= ret_dat;


if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
state <= IDLE; state <= IDLE;
ret_ack <= '0'; ret_ack <= '0';
else else
ret_dat := x"FFFFFFFFFFFFFFFF"; ret_dat := x"FFFFFFFFFFFFFFFF";


-- Active -- Active
if wishbone_in.cyc = '1' then if wishbone_in.cyc = '1' then
case state is case state is
when IDLE => when IDLE =>
if wishbone_in.stb = '1' then if wishbone_in.stb = '1' then
-- write -- write
if wishbone_in.we = '1' then if wishbone_in.we = '1' then
assert not(is_x(wishbone_in.dat)) and not(is_x(wishbone_in.adr)) severity failure; assert not(is_x(wishbone_in.dat)) and not(is_x(wishbone_in.adr)) severity failure;
report "RAM writing " & to_hstring(wishbone_in.dat) & " to " & to_hstring(wishbone_in.adr); report "RAM writing " & to_hstring(wishbone_in.dat) & " to " & to_hstring(wishbone_in.adr);
behavioural_write(wishbone_in.dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier); behavioural_write(wishbone_in.dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier);
reload <= reload + 1; reload <= reload + 1;
ret_ack <= '1'; ret_ack <= '1';
state <= ACK; state <= ACK;
else else
behavioural_read(ret_dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier, reload); behavioural_read(ret_dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier, reload);
report "RAM reading from " & to_hstring(wishbone_in.adr) & " returns " & to_hstring(ret_dat); report "RAM reading from " & to_hstring(wishbone_in.adr) & " returns " & to_hstring(ret_dat);
ret_ack <= '1'; ret_ack <= '1';
state <= ACK; state <= ACK;
end if; end if;
end if; end if;
when ACK => when ACK =>
ret_ack <= '0'; ret_ack <= '0';
state <= IDLE; state <= IDLE;
end case; end case;
else else
ret_ack <= '0'; ret_ack <= '0';
state <= IDLE; state <= IDLE;
end if; end if;
end if; end if;
end if; end if;
end process; end process;
end behave; end behave;

36
simple_ram_behavioural_helpers.vhdl
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@ -2,29 +2,29 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;


package simple_ram_behavioural_helpers is package simple_ram_behavioural_helpers is
function behavioural_initialize (filename: String; size: integer) return integer; function behavioural_initialize (filename: String; size: integer) return integer;
attribute foreign of behavioural_initialize : function is "VHPIDIRECT behavioural_initialize"; attribute foreign of behavioural_initialize : function is "VHPIDIRECT behavioural_initialize";


procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer; reload: integer); procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer; reload: integer);
attribute foreign of behavioural_read : procedure is "VHPIDIRECT behavioural_read"; attribute foreign of behavioural_read : procedure is "VHPIDIRECT behavioural_read";


procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer); procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer);
attribute foreign of behavioural_write : procedure is "VHPIDIRECT behavioural_write"; attribute foreign of behavioural_write : procedure is "VHPIDIRECT behavioural_write";
end simple_ram_behavioural_helpers; end simple_ram_behavioural_helpers;


package body simple_ram_behavioural_helpers is package body simple_ram_behavioural_helpers is
function behavioural_initialize (filename: String; size: integer) return integer is function behavioural_initialize (filename: String; size: integer) return integer is
begin begin
assert false report "VHPI" severity failure; assert false report "VHPI" severity failure;
end behavioural_initialize; end behavioural_initialize;


procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer; reload: integer) is procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer; reload: integer) is
begin begin
assert false report "VHPI" severity failure; assert false report "VHPI" severity failure;
end behavioural_read; end behavioural_read;


procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer) is procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer) is
begin begin
assert false report "VHPI" severity failure; assert false report "VHPI" severity failure;
end behavioural_write; end behavioural_write;
end simple_ram_behavioural_helpers; end simple_ram_behavioural_helpers;

444
simple_ram_behavioural_tb.vhdl
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@ -9,225 +9,233 @@ entity simple_ram_behavioural_tb is
end simple_ram_behavioural_tb; end simple_ram_behavioural_tb;


architecture behave of simple_ram_behavioural_tb is architecture behave of simple_ram_behavioural_tb is
signal clk : std_ulogic; signal clk : std_ulogic;
signal rst : std_ulogic := '1'; signal rst : std_ulogic := '1';


constant clk_period : time := 10 ns; constant clk_period : time := 10 ns;


signal w_in : wishbone_slave_out; signal w_in : wishbone_slave_out;
signal w_out : wishbone_master_out; signal w_out : wishbone_master_out;
begin begin
simple_ram_0: entity work.mw_soc_memory simple_ram_0: entity work.mw_soc_memory
generic map ( RAM_INIT_FILE => "simple_ram_behavioural_tb.bin", MEMORY_SIZE => 16 ) generic map (
port map (clk => clk, rst => rst, wishbone_out => w_in, wishbone_in => w_out); RAM_INIT_FILE => "simple_ram_behavioural_tb.bin",

MEMORY_SIZE => 16
clock: process )
begin port map (
clk <= '1'; clk => clk,
wait for clk_period / 2; rst => rst,
clk <= '0'; wishbone_out => w_in,
wait for clk_period / 2; wishbone_in => w_out
end process clock; );


stim: process clock: process
begin begin
w_out.adr <= (others => '0'); clk <= '1';
w_out.dat <= (others => '0'); wait for clk_period / 2;
w_out.cyc <= '0'; clk <= '0';
w_out.stb <= '0'; wait for clk_period / 2;
w_out.sel <= (others => '0'); end process clock;
w_out.we <= '0';

stim: process
wait for clk_period; begin
rst <= '0'; w_out.adr <= (others => '0');

w_out.dat <= (others => '0');
wait for clk_period; w_out.cyc <= '0';

w_out.stb <= '0';
w_out.cyc <= '1'; w_out.sel <= (others => '0');

w_out.we <= '0';
-- test various read lengths and alignments
w_out.stb <= '1'; wait for clk_period;
w_out.sel <= "00000001"; rst <= '0';
w_out.adr <= x"0000000000000000";
assert w_in.ack = '0'; wait for clk_period;
wait for clk_period;
assert w_in.ack = '1'; w_out.cyc <= '1';
assert w_in.dat(7 downto 0) = x"00" report to_hstring(w_in.dat);
w_out.stb <= '0'; -- test various read lengths and alignments
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00000001";

w_out.adr <= x"0000000000000000";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00000001"; wait for clk_period;
w_out.adr <= x"0000000000000001"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(7 downto 0) = x"00" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(7 downto 0) = x"01" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00000001";

w_out.adr <= x"0000000000000001";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00000001"; wait for clk_period;
w_out.adr <= x"0000000000000007"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(7 downto 0) = x"01" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(7 downto 0) = x"07" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00000001";

w_out.adr <= x"0000000000000007";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00000011"; wait for clk_period;
w_out.adr <= x"0000000000000000"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(7 downto 0) = x"07" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(15 downto 0) = x"0100" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00000011";

w_out.adr <= x"0000000000000000";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00000011"; wait for clk_period;
w_out.adr <= x"0000000000000001"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(15 downto 0) = x"0100" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(15 downto 0) = x"0201" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00000011";

w_out.adr <= x"0000000000000001";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00000011"; wait for clk_period;
w_out.adr <= x"0000000000000007"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(15 downto 0) = x"0201" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(15 downto 0) = x"0807" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00000011";

w_out.adr <= x"0000000000000007";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00001111"; wait for clk_period;
w_out.adr <= x"0000000000000000"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(15 downto 0) = x"0807" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(31 downto 0) = x"03020100" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00001111";

w_out.adr <= x"0000000000000000";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00001111"; wait for clk_period;
w_out.adr <= x"0000000000000001"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(31 downto 0) = x"03020100" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(31 downto 0) = x"04030201" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00001111";

w_out.adr <= x"0000000000000001";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00001111"; wait for clk_period;
w_out.adr <= x"0000000000000007"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(31 downto 0) = x"04030201" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(31 downto 0) = x"0A090807" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00001111";

w_out.adr <= x"0000000000000007";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "11111111"; wait for clk_period;
w_out.adr <= x"0000000000000000"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(31 downto 0) = x"0A090807" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(63 downto 0) = x"0706050403020100" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "11111111";

w_out.adr <= x"0000000000000000";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "11111111"; wait for clk_period;
w_out.adr <= x"0000000000000001"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(63 downto 0) = x"0706050403020100" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(63 downto 0) = x"0807060504030201" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "11111111";

w_out.adr <= x"0000000000000001";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "11111111"; wait for clk_period;
w_out.adr <= x"0000000000000007"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(63 downto 0) = x"0807060504030201" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(63 downto 0) = x"0E0D0C0B0A090807" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "11111111";

w_out.adr <= x"0000000000000007";
-- test various write lengths and alignments assert w_in.ack = '0';
w_out.stb <= '1'; wait for clk_period;
w_out.sel <= "00000001"; assert w_in.ack = '1';
w_out.adr <= x"0000000000000000"; assert w_in.dat(63 downto 0) = x"0E0D0C0B0A090807" report to_hstring(w_in.dat);
w_out.we <= '1'; w_out.stb <= '0';
w_out.dat(7 downto 0) <= x"0F"; wait for clk_period;
assert w_in.ack = '0'; assert w_in.ack = '0';
wait for clk_period;
assert w_in.ack = '1'; -- test various write lengths and alignments
w_out.stb <= '0'; w_out.stb <= '1';
wait for clk_period; w_out.sel <= "00000001";
assert w_in.ack = '0'; w_out.adr <= x"0000000000000000";

w_out.we <= '1';
w_out.stb <= '1'; w_out.dat(7 downto 0) <= x"0F";
w_out.sel <= "00000001"; assert w_in.ack = '0';
w_out.adr <= x"0000000000000000"; wait for clk_period;
w_out.we <= '0'; assert w_in.ack = '1';
assert w_in.ack = '0'; w_out.stb <= '0';
wait for clk_period; wait for clk_period;
assert w_in.ack = '1'; assert w_in.ack = '0';
assert w_in.dat(7 downto 0) = x"0F" report to_hstring(w_in.dat);
w_out.stb <= '0'; w_out.stb <= '1';
wait for clk_period; w_out.sel <= "00000001";
assert w_in.ack = '0'; w_out.adr <= x"0000000000000000";

w_out.we <= '0';
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "11111111"; wait for clk_period;
w_out.adr <= x"0000000000000007"; assert w_in.ack = '1';
w_out.we <= '1'; assert w_in.dat(7 downto 0) = x"0F" report to_hstring(w_in.dat);
w_out.dat <= x"BADC0FFEBADC0FFE"; w_out.stb <= '0';
assert w_in.ack = '0'; wait for clk_period;
wait for clk_period; assert w_in.ack = '0';
assert w_in.ack = '1';
w_out.stb <= '0'; w_out.stb <= '1';
wait for clk_period; w_out.sel <= "11111111";
assert w_in.ack = '0'; w_out.adr <= x"0000000000000007";

w_out.we <= '1';
w_out.stb <= '1'; w_out.dat <= x"BADC0FFEBADC0FFE";
w_out.sel <= "11111111"; assert w_in.ack = '0';
w_out.adr <= x"0000000000000007"; wait for clk_period;
w_out.we <= '0'; assert w_in.ack = '1';
assert w_in.ack = '0'; w_out.stb <= '0';
wait for clk_period; wait for clk_period;
assert w_in.ack = '1'; assert w_in.ack = '0';
assert w_in.dat = x"BADC0FFEBADC0FFE" report to_hstring(w_in.dat);
w_out.stb <= '0'; w_out.stb <= '1';
wait for clk_period; w_out.sel <= "11111111";
assert w_in.ack = '0'; w_out.adr <= x"0000000000000007";

w_out.we <= '0';
assert false report "end of test" severity failure; assert w_in.ack = '0';
wait; wait for clk_period;
end process; assert w_in.ack = '1';
assert w_in.dat = x"BADC0FFEBADC0FFE" report to_hstring(w_in.dat);
w_out.stb <= '0';
wait for clk_period;
assert w_in.ack = '0';

assert false report "end of test" severity failure;
wait;
end process;
end behave; end behave;

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