Add an icache testbench

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/60/head
Anton Blanchard 5 years ago committed by Anton Blanchard
parent d573748da0
commit 1e3e16e500

@ -2,7 +2,7 @@ GHDL=ghdl
GHDLFLAGS=--std=08 GHDLFLAGS=--std=08
CFLAGS=-O2 -Wall CFLAGS=-O2 -Wall


all = core_tb simple_ram_behavioural_tb soc_reset_tb all = core_tb simple_ram_behavioural_tb soc_reset_tb icache_tb
# XXX # XXX
# loadstore_tb fetch_tb # loadstore_tb fetch_tb


@ -27,6 +27,7 @@ glibc_random_helpers.o:
glibc_random.o: glibc_random_helpers.o glibc_random.o: glibc_random_helpers.o
helpers.o: helpers.o:
icache.o: common.o wishbone_types.o icache.o: common.o wishbone_types.o
icache_tb.o: common.o wishbone_types.o icache.o simple_ram_behavioural.o
insn_helpers.o: insn_helpers.o:
loadstore1.o: common.o loadstore1.o: common.o
loadstore2.o: common.o helpers.o wishbone_types.o loadstore2.o: common.o helpers.o wishbone_types.o
@ -54,6 +55,9 @@ core_tb: core_tb.o simple_ram_behavioural_helpers_c.o sim_console_c.o
fetch_tb: fetch_tb.o fetch_tb: fetch_tb.o
$(GHDL) -e $(GHDLFLAGS) $@ $(GHDL) -e $(GHDLFLAGS) $@


icache_tb: icache_tb.o
$(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o $@

loadstore_tb: loadstore_tb.o loadstore_tb: loadstore_tb.o
$(GHDL) -e $(GHDLFLAGS) $@ $(GHDL) -e $(GHDLFLAGS) $@



@ -0,0 +1,120 @@
library ieee;
use ieee.std_logic_1164.all;

library work;
use work.common.all;
use work.wishbone_types.all;

entity icache_tb is
end icache_tb;

architecture behave of icache_tb is
signal clk : std_ulogic;
signal rst : std_ulogic;

signal i_out : Fetch2ToIcacheType;
signal i_in : IcacheToFetch2Type;

signal wb_bram_in : wishbone_master_out;
signal wb_bram_out : wishbone_slave_out;

constant clk_period : time := 10 ns;
begin
icache0: entity work.icache
generic map(
LINE_SIZE_DW => 8,
NUM_LINES => 4
)
port map(
clk => clk,
rst => rst,
i_in => i_out,
i_out => i_in,
wishbone_out => wb_bram_in,
wishbone_in => wb_bram_out
);

-- BRAM Memory slave
bram0: entity work.mw_soc_memory
generic map(
MEMORY_SIZE => 128,
RAM_INIT_FILE => "icache_test.bin"
)
port map(
clk => clk,
rst => rst,
wishbone_in => wb_bram_in,
wishbone_out => wb_bram_out
);

clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

rst_process: process
begin
rst <= '1';
wait for 2*clk_period;
rst <= '0';
wait;
end process;

stim: process
begin
i_out.req <= '0';
i_out.addr <= (others => '0');

wait for 4*clk_period;

i_out.req <= '1';
i_out.addr <= x"0000000000000004";

wait for 30*clk_period;

assert i_in.ack = '1';
assert i_in.insn = x"00000001";

i_out.req <= '0';

wait for clk_period;

-- hit
i_out.req <= '1';
i_out.addr <= x"0000000000000008";
wait for clk_period/2;
assert i_in.ack = '1';
assert i_in.insn = x"00000002";
wait for clk_period/2;

-- another miss
i_out.req <= '1';
i_out.addr <= x"0000000000000040";

wait for 30*clk_period;

assert i_in.ack = '1';
assert i_in.insn = x"00000010";

-- test something that aliases
i_out.req <= '1';
i_out.addr <= x"0000000000000100";
wait for clk_period/2;
assert i_in.ack = '0';
wait for clk_period/2;

wait for 30*clk_period;

assert i_in.ack = '1';
assert i_in.insn = x"00000040";

i_out.req <= '0';

assert false report "end of test" severity failure;
wait;

end process;
end;
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