soc: Add defaults for some input signals

That way the top-level's don't need to assign them

Also remove generics that are set to the default anyways

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

core_dram_tb.vhdl

@@ -72,8 +72,6 @@ begin
 	port map(
 	    rst => soc_rst,
 	    system_clk => system_clk,
-	    uart0_rxd => '0',
-	    uart0_txd => open,
 	    wb_dram_in => wb_dram_in,
 	    wb_dram_out => wb_dram_out,
 	    wb_dram_ctrl_in => wb_dram_ctrl_in,

core_flash_tb.vhdl

@@ -46,8 +46,6 @@ begin
 	port map(
 	    rst => rst,
 	    system_clk => clk,
-	    uart0_rxd => '0',
-	    uart0_txd => open,
 	    wb_dram_in => wb_dram_in,
 	    wb_dram_out => wb_dram_out,
 	    wb_dram_ctrl_in => wb_dram_ctrl_in,
@@ -56,8 +54,7 @@ begin
             spi_flash_cs_n    => spi_cs_n,
             spi_flash_sdat_o  => spi_sdat_o,
             spi_flash_sdat_oe => spi_sdat_oe,
-            spi_flash_sdat_i  => spi_sdat_i,
+            spi_flash_sdat_i  => spi_sdat_i
-	    alt_reset => '0'
 	    );
 
     flash: entity work.s25fl128s

core_tb.vhdl

@@ -20,9 +20,6 @@ architecture behave of core_tb is
 	signal wb_dram_out : wishbone_slave_out;
 	signal wb_dram_ctrl_in : wb_io_master_out;
 	signal wb_dram_ctrl_out : wb_io_slave_out;
-
-        -- Dummy SPI
-        signal spi_sdat_i : std_ulogic_vector(0 downto 0);
 begin
 
     soc0: entity work.soc
@@ -30,26 +27,16 @@ begin
 	    SIM => true,
 	    MEMORY_SIZE => (384*1024),
 	    RAM_INIT_FILE => "main_ram.bin",
-	    CLK_FREQ => 100000000,
+	    CLK_FREQ => 100000000
-            HAS_SPI_FLASH => false
 	    )
 	port map(
 	    rst => rst,
 	    system_clk => clk,
-	    uart0_rxd => '0',
-	    uart0_txd => open,
-            spi_flash_sck => open,
-            spi_flash_cs_n => open,
-            spi_flash_sdat_o => open,
-            spi_flash_sdat_oe => open,
-            spi_flash_sdat_i => spi_sdat_i,
 	    wb_dram_in => wb_dram_in,
 	    wb_dram_out => wb_dram_out,
 	    wb_dram_ctrl_in => wb_dram_ctrl_in,
-	    wb_dram_ctrl_out => wb_dram_ctrl_out,
+	    wb_dram_ctrl_out => wb_dram_ctrl_out
-	    alt_reset => '0'
 	    );
-    spi_sdat_i(0) <= '1';
 
     clk_process: process
     begin

fpga/top-generic.vhdl

@@ -40,8 +40,6 @@ architecture behaviour of toplevel is
     -- DRAM control wishbone connection
     signal wb_dram_ctrl_in  : wb_io_master_out;
     signal wb_dram_ctrl_out : wb_io_slave_out;
-    signal wb_dram_is_csr   : std_ulogic;
-    signal wb_dram_is_init  : std_ulogic;
 
 begin
 
@@ -77,26 +75,17 @@ begin
 	    RAM_INIT_FILE => RAM_INIT_FILE,
 	    SIM           => false,
 	    CLK_FREQ      => CLK_FREQUENCY,
-	    DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
+	    DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE
-            HAS_SPI          => false
 	    )
 	port map (
 	    system_clk        => system_clk,
 	    rst               => soc_rst,
 	    uart0_txd         => uart0_txd,
 	    uart0_rxd         => uart0_rxd,
-            spi0_sck          => open,
-            spi0_cs_n         => open,
-            spi0_sdat_o       => open,
-            spi0_sdat_oe      => open,
-            spi0_sdat_i       => '1',
 	    wb_dram_in        => wb_dram_in,
 	    wb_dram_out       => wb_dram_out,
 	    wb_dram_ctrl_in   => wb_dram_ctrl_in,
-	    wb_dram_ctrl_out  => wb_dram_ctrl_out,
+	    wb_dram_ctrl_out  => wb_dram_ctrl_out
-	    wb_dram_is_csr    => wb_dram_is_csr,
-	    wb_dram_is_init   => wb_dram_is_init,
-	    alt_reset         => '0'
 	    );
 
     -- Dummy DRAM

soc.vhdl

@@ -56,17 +56,17 @@ entity soc is
 
 	-- UART0 signals:
 	uart0_txd    : out std_ulogic;
-	uart0_rxd    : in  std_ulogic;
+	uart0_rxd    : in  std_ulogic := '0';
 
         -- SPI Flash signals
         spi_flash_sck     : out std_ulogic;
         spi_flash_cs_n    : out std_ulogic;
         spi_flash_sdat_o  : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
         spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
-        spi_flash_sdat_i  : in  std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
+        spi_flash_sdat_i  : in  std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
 
 	-- DRAM controller signals
-	alt_reset    : in std_ulogic
+	alt_reset    : in std_ulogic := '0'
 	);
 end entity soc;