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@ -187,6 +187,7 @@ architecture behaviour of fpu is
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cycle_1_ar : std_ulogic;
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regsel : std_ulogic_vector(2 downto 0);
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is_nan_inf : std_ulogic;
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zero_fri : std_ulogic;
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end record;
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type lookup_table is array(0 to 1023) of std_ulogic_vector(17 downto 0);
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@ -1093,6 +1094,7 @@ begin
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v.quieten_nan := '1';
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v.int_result := '0';
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v.is_arith := '0';
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v.zero_fri := '0';
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case e_in.op is
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when OP_FP_ARITH =>
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fpin_a := e_in.valid_a;
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@ -1138,7 +1140,10 @@ begin
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when "01110" | "01111" => -- fcti*
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v.int_result := '1';
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v.result_sign := e_in.frb(63);
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when others => -- fri* and frsp
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when "01000" => -- fri*
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v.zero_fri := '1';
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v.result_sign := e_in.frb(63);
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when others => -- frsp
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v.result_sign := e_in.frb(63);
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end case;
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when OP_FP_CMP =>
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@ -2469,7 +2474,11 @@ begin
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opsel_mask <= '1';
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set_r := '1';
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round := fp_rounding(r.r, r.x, r.single_prec, r.round_mode, r.result_sign);
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v.fpscr(FPSCR_FR downto FPSCR_FI) := round;
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if r.zero_fri = '0' then
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v.fpscr(FPSCR_FR downto FPSCR_FI) := round;
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else
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v.fpscr(FPSCR_FR downto FPSCR_FI) := "00"; -- for fri* instructions
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end if;
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if round(1) = '1' then
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-- increment the LSB for the precision
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v.state := ROUND_INC;
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@ -2481,7 +2490,7 @@ begin
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else
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arith_done := '1';
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end if;
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if round(0) = '1' then
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if round(0) = '1' and r.zero_fri = '0' then
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v.fpscr(FPSCR_XX) := '1';
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if r.tiny = '1' then
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v.fpscr(FPSCR_UX) := '1';
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