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litedram: Remove old "VexRiscV" based initializations

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Support for this has bitrotted and would require refactoring of L2 to
be brought back. It's also not really needed anymore now that we ship
pre-generated litedram and that LiteX supports what we do.

So take it out, which simplifies some of the scripts as well. This also
fixes up CSR alignment the sim model.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
pull/190/head
Benjamin Herrenschmidt 4 years ago
parent eaf6883e57
commit 599fad117b
16 changed files with 358 additions and 4948 deletions
Show Stats Download Patch File Download Diff File

2
Makefile
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@ -95,7 +95,7 @@ SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -fa
sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
$(CC) $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@ $(CC) $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@


soc_dram_files = $(soc_files) litedram/extras/wrapper-mw-init.vhdl litedram/generated/sim/litedram-initmem.vhdl soc_dram_files = $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++ dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++

3967
litedram/extras/VexRiscv.v
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23
litedram/extras/fusesoc-add-files.py
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@ -17,15 +17,6 @@ class LiteDRAMGenerator(Generator):


print("Adding LiteDRAM for board... ", board) print("Adding LiteDRAM for board... ", board)


# Grab init-cpu.txt if it exists
cpu_file = os.path.join(gen_dir, "init-cpu.txt")
if os.path.exists(cpu_file):
cpu = pathlib.Path(cpu_file).read_text()
else:
cpu = "none"

print("CPU is ", cpu)

# Add files to fusesoc # Add files to fusesoc
files = [] files = []
f = os.path.join(gen_dir, "litedram_core.v") f = os.path.join(gen_dir, "litedram_core.v")
@ -34,18 +25,8 @@ class LiteDRAMGenerator(Generator):
files.append({f : {'file_type' : 'vhdlSource-2008'}}) files.append({f : {'file_type' : 'vhdlSource-2008'}})
f = os.path.join(gen_dir, "litedram_core.init") f = os.path.join(gen_dir, "litedram_core.init")
files.append({f : {'file_type' : 'user'}}) files.append({f : {'file_type' : 'user'}})

f = os.path.join(extras_dir, "litedram-wrapper-l2.vhdl")
# Look for init CPU types and add corresponding files files.append({f : {'file_type' : 'vhdlSource-2008'}})
if cpu == "vexriscv":
print("Adding VexRiscv files and wrapper")
f = os.path.join(extras_dir, "VexRiscv.v")
files.append({f : {'file_type' : 'verilogSource'}})
f = os.path.join(extras_dir, "wrapper-self-init.vhdl")
files.append({f : {'file_type' : 'vhdlSource-2008'}})
else:
print("Adding wrapper")
f = os.path.join(extras_dir, "wrapper-mw-init.vhdl")
files.append({f : {'file_type' : 'vhdlSource-2008'}})


self.add_files(files) self.add_files(files)



0
litedram/extras/wrapper-mw-init.vhdl → litedram/extras/litedram-wrapper-l2.vhdl
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225
litedram/extras/wrapper-self-init.vhdl
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@ -1,225 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

library work;
use work.wishbone_types.all;

entity litedram_wrapper is
generic (
DRAM_ABITS : positive;
DRAM_ALINES : positive
);
port(
-- LiteDRAM generates the system clock and reset
-- from the input clkin
clk_in : in std_ulogic;
rst : in std_ulogic;
system_clk : out std_ulogic;
system_reset : out std_ulogic;
core_alt_reset : out std_ulogic;
pll_locked : out std_ulogic;

-- Wishbone ports:
wb_in : in wishbone_master_out;
wb_out : out wishbone_slave_out;
wb_ctrl_in : in wb_io_master_out;
wb_ctrl_out : out wb_io_slave_out;
wb_ctrl_is_csr : in std_ulogic;
wb_ctrl_is_init : in std_ulogic;

-- Init core serial debug
serial_tx : out std_ulogic;
serial_rx : in std_ulogic;

-- Misc
init_done : out std_ulogic;
init_error : out std_ulogic;

-- DRAM wires
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
ddram_ba : out std_ulogic_vector(2 downto 0);
ddram_ras_n : out std_ulogic;
ddram_cas_n : out std_ulogic;
ddram_we_n : out std_ulogic;
ddram_cs_n : out std_ulogic;
ddram_dm : out std_ulogic_vector(1 downto 0);
ddram_dq : inout std_ulogic_vector(15 downto 0);
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
ddram_clk_p : out std_ulogic;
ddram_clk_n : out std_ulogic;
ddram_cke : out std_ulogic;
ddram_odt : out std_ulogic;
ddram_reset_n : out std_ulogic
end entity litedram_wrapper;

architecture behaviour of litedram_wrapper is

component litedram_core port (
clk : in std_ulogic;
rst : in std_ulogic;
serial_tx : out std_ulogic;
serial_rx : in std_ulogic;
pll_locked : out std_ulogic;
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
ddram_ba : out std_ulogic_vector(2 downto 0);
ddram_ras_n : out std_ulogic;
ddram_cas_n : out std_ulogic;
ddram_we_n : out std_ulogic;
ddram_cs_n : out std_ulogic;
ddram_dm : out std_ulogic_vector(1 downto 0);
ddram_dq : inout std_ulogic_vector(15 downto 0);
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
ddram_clk_p : out std_ulogic;
ddram_clk_n : out std_ulogic;
ddram_cke : out std_ulogic;
ddram_odt : out std_ulogic;
ddram_reset_n : out std_ulogic;
init_done : out std_ulogic;
init_error : out std_ulogic;
user_clk : out std_ulogic;
user_rst : out std_ulogic;
user_port_native_0_cmd_valid : in std_ulogic;
user_port_native_0_cmd_ready : out std_ulogic;
user_port_native_0_cmd_we : in std_ulogic;
user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
user_port_native_0_wdata_valid : in std_ulogic;
user_port_native_0_wdata_ready : out std_ulogic;
user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0);
user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0);
user_port_native_0_rdata_valid : out std_ulogic;
user_port_native_0_rdata_ready : in std_ulogic;
user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0)
);
end component;
signal user_port0_cmd_valid : std_ulogic;
signal user_port0_cmd_ready : std_ulogic;
signal user_port0_cmd_we : std_ulogic;
signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0);
signal user_port0_wdata_valid : std_ulogic;
signal user_port0_wdata_ready : std_ulogic;
signal user_port0_wdata_we : std_ulogic_vector(15 downto 0);
signal user_port0_wdata_data : std_ulogic_vector(127 downto 0);
signal user_port0_rdata_valid : std_ulogic;
signal user_port0_rdata_ready : std_ulogic;
signal user_port0_rdata_data : std_ulogic_vector(127 downto 0);

signal ad3 : std_ulogic;

signal dram_user_reset : std_ulogic;

type state_t is (CMD, MWRITE, MREAD);
signal state : state_t;

begin

-- Reset, lift it when init done, no alt core reset
system_reset <= dram_user_reset or not init_done;
core_alt_reset <= '0';

-- Control bus is unused
wb_ctrl_out.ack <= (wb_is_ctrl = '1' or wb_is_init = '1') and wb_ctrl_in.cyc;
else wb_init_out.ack;
wb_ctrl_out.dat <= (others => '0');
wb_ctrl_out.stall <= '0';

--
-- Data bus wishbone to LiteDRAM native port
--
-- Address bit 3 selects the top or bottom half of the data
-- bus (64-bit wishbone vs. 128-bit DRAM interface)
--
-- XXX TODO: Figure out how to pipeline this
--
ad3 <= wb_in.adr(3);

-- Wishbone port IN signals
user_port0_cmd_valid <= wb_in.cyc and wb_in.stb when state = CMD else '0';
user_port0_cmd_we <= wb_in.we when state = CMD else '0';
user_port0_wdata_valid <= '1' when state = MWRITE else '0';
user_port0_rdata_ready <= '1' when state = MREAD else '0';
user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4);
user_port0_wdata_data <= wb_in.dat & wb_in.dat;
user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else
"00000000" & wb_in.sel;

-- Wishbone OUT signals
wb_out.ack <= user_port0_wdata_ready when state = MWRITE else
user_port0_rdata_valid when state = MREAD else '0';

wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else
user_port0_rdata_data(63 downto 0);

-- We don't do pipelining yet.
wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;

-- DRAM user port State machine
sm: process(system_clk)
begin
if rising_edge(system_clk) then
if dram_user_reset = '1' then
state <= CMD;
else
case state is
when CMD =>
if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
state <= MWRITE when wb_in.we = '1' else MREAD;
end if;
when MWRITE =>
if user_port0_wdata_ready = '1' then
state <= CMD;
end if;
when MREAD =>
if user_port0_rdata_valid = '1' then
state <= CMD;
end if;
end case;
end if;
end if;
end process;

litedram: litedram_core
port map(
clk => clk_in,
rst => rst,
serial_tx => serial_tx,
serial_rx => serial_rx,
pll_locked => pll_locked,
ddram_a => ddram_a,
ddram_ba => ddram_ba,
ddram_ras_n => ddram_ras_n,
ddram_cas_n => ddram_cas_n,
ddram_we_n => ddram_we_n,
ddram_cs_n => ddram_cs_n,
ddram_dm => ddram_dm,
ddram_dq => ddram_dq,
ddram_dqs_p => ddram_dqs_p,
ddram_dqs_n => ddram_dqs_n,
ddram_clk_p => ddram_clk_p,
ddram_clk_n => ddram_clk_n,
ddram_cke => ddram_cke,
ddram_odt => ddram_odt,
ddram_reset_n => ddram_reset_n,
init_done => init_done,
init_error => init_error,
user_clk => system_clk,
user_rst => dram_user_reset,
user_port_native_0_cmd_valid => user_port0_cmd_valid,
user_port_native_0_cmd_ready => user_port0_cmd_ready,
user_port_native_0_cmd_we => user_port0_cmd_we,
user_port_native_0_cmd_addr => user_port0_cmd_addr,
user_port_native_0_wdata_valid => user_port0_wdata_valid,
user_port_native_0_wdata_ready => user_port0_wdata_ready,
user_port_native_0_wdata_we => user_port0_wdata_we,
user_port_native_0_wdata_data => user_port0_wdata_data,
user_port_native_0_rdata_valid => user_port0_rdata_valid,
user_port_native_0_rdata_ready => user_port0_rdata_ready,
user_port_native_0_rdata_data => user_port0_rdata_data
);

end architecture behaviour;

8
litedram/gen-src/arty.yml
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@ -3,8 +3,8 @@


{ {
# General ------------------------------------------------------------------ # General ------------------------------------------------------------------
"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32)
"cpu_variant":"minimal", "cpu_variant":"standard",
"speedgrade": -1, # FPGA speedgrade "speedgrade": -1, # FPGA speedgrade
"memtype": "DDR3", # DRAM type "memtype": "DDR3", # DRAM type


@ -37,6 +37,6 @@
}, },


# CSR Port ----------------------------------------------------------------- # CSR Port -----------------------------------------------------------------
"csr_base" : 0xc0100000, # For cpu=None only "csr_alignment" : 32,
csr_data_width : 32, "csr_data_width" : 32,
} }

30
litedram/gen-src/generate.py
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@ -74,7 +74,7 @@ def build_init_code(build_dir, is_sim):


return os.path.join(sw_dir, "obj", "sdram_init.hex") return os.path.join(sw_dir, "obj", "sdram_init.hex")


def generate_one(t, mw_init): def generate_one(t):


print("Generating target:", t) print("Generating target:", t)


@ -106,12 +106,6 @@ def generate_one(t, mw_init):
if k == "sdram_phy": if k == "sdram_phy":
core_config[k] = getattr(litedram_phys, core_config[k]) core_config[k] = getattr(litedram_phys, core_config[k])


# Override values for mw_init
if mw_init:
core_config["cpu"] = None
core_config["cpu_variant"] = "standard"
core_config["csr_alignment"] = 64

# Generate core # Generate core
if is_sim: if is_sim:
platform = SimPlatform("", io=[]) platform = SimPlatform("", io=[])
@ -131,24 +125,15 @@ def generate_one(t, mw_init):
# Grab generated gatewar dir # Grab generated gatewar dir
gw_dir = os.path.join(build_dir, "gateware") gw_dir = os.path.join(build_dir, "gateware")


# Generate init-cpu.txt and generate init code # Generate init code
cpu = core_config["cpu"] src_init_file = build_init_code(build_dir, is_sim)
if mw_init: src_initram_file = os.path.join(gen_src_dir, "dram-init-mem.vhdl")
write_to_file(os.path.join(t_dir, "init-cpu.txt"), "none")
src_init_file = build_init_code(build_dir, is_sim)
src_initram_file = os.path.join(gen_src_dir, "dram-init-mem.vhdl")
else:
write_to_file(os.path.join(t_dir, "init-cpu.txt"), cpu)
src_init_file = os.path.join(gw_dir, "mem.init")
src_initram_file = os.path.join(gen_src_dir, "no-init-mem.vhdl")


# Copy generated files to target dir, amend them if necessary # Copy generated files to target dir, amend them if necessary
initfile_name = "litedram_core.init" initfile_name = "litedram_core.init"
core_file = os.path.join(gw_dir, "litedram_core.v") core_file = os.path.join(gw_dir, "litedram_core.v")
dst_init_file = os.path.join(t_dir, initfile_name) dst_init_file = os.path.join(t_dir, initfile_name)
dst_initram_file = os.path.join(t_dir, "litedram-initmem.vhdl") dst_initram_file = os.path.join(t_dir, "litedram-initmem.vhdl")
if not mw_init:
replace_in_file(core_file, "mem.init", initfile_name)
shutil.copyfile(src_init_file, dst_init_file) shutil.copyfile(src_init_file, dst_init_file)
shutil.copyfile(src_initram_file, dst_initram_file) shutil.copyfile(src_initram_file, dst_initram_file)
if is_sim: if is_sim:
@ -159,13 +144,8 @@ def generate_one(t, mw_init):
def main(): def main():


targets = ['arty','nexys-video', 'sim'] targets = ['arty','nexys-video', 'sim']
# targets = ['sim']

# XXX Set mw_init to False to use a local VexRiscV for memory inits
for t in targets: for t in targets:
generate_one(t, mw_init = True) generate_one(t)

# XXX TODO: Remove build dir unless told not to via cmdline option
if __name__ == "__main__": if __name__ == "__main__":
main() main()

8
litedram/gen-src/nexys-video.yml
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@ -3,8 +3,8 @@


{ {
# General ------------------------------------------------------------------ # General ------------------------------------------------------------------
"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32)
"cpu_variant":"minimal", "cpu_variant":"standard",
"speedgrade": -1, # FPGA speedgrade "speedgrade": -1, # FPGA speedgrade
"memtype": "DDR3", # DRAM type "memtype": "DDR3", # DRAM type


@ -37,6 +37,6 @@
}, },


# CSR Port ----------------------------------------------------------------- # CSR Port -----------------------------------------------------------------
"csr_base" : 0xc0100000, # For cpu=None only "csr_alignment" : 32,
csr_data_width : 32, "csr_data_width" : 32,
} }

8
litedram/gen-src/sim.yml
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@ -4,10 +4,10 @@
{ {
# General ------------------------------------------------------------------ # General ------------------------------------------------------------------
"cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32)
"cpu_variant":"minimal", "cpu_variant":"standard",
"speedgrade": -1, # FPGA speedgrade "speedgrade": -1, # FPGA speedgrade
"memtype": "DDR3", # DRAM type "memtype": "DDR3", # DRAM type
"sim" : "True", "sim" : "True",


# PHY ---------------------------------------------------------------------- # PHY ----------------------------------------------------------------------
"cmd_delay": 0, # Command additional delay (in taps) "cmd_delay": 0, # Command additional delay (in taps)
@ -36,4 +36,8 @@
"type": "native", "type": "native",
}, },
}, },

# CSR Port -----------------------------------------------------------------
"csr_alignment" : 32,
"csr_data_width" : 32,
} }

1
litedram/generated/arty/init-cpu.txt
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@ -1 +0,0 @@
none

2
litedram/generated/arty/litedram_core.v
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@ -1,5 +1,5 @@
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:36 // Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:51
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
module litedram_core( module litedram_core(
input wire clk, input wire clk,

1
litedram/generated/nexys-video/init-cpu.txt
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@ -1 +0,0 @@
none

2
litedram/generated/nexys-video/litedram_core.v
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@ -1,5 +1,5 @@
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:37 // Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:52
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
module litedram_core( module litedram_core(
input wire clk, input wire clk,

1
litedram/generated/sim/init-cpu.txt
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@ -1 +0,0 @@
none

372
litedram/generated/sim/litedram_core.init
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@ -519,11 +519,11 @@ f8c101a838800140
38c101987c651b78 38c101987c651b78
7fe3fb78f8e101b0 7fe3fb78f8e101b0
f92101c0f90101b8 f92101c0f90101b8
48000d1df94101c8 48000cfdf94101c8
7c7e1b7860000000 7c7e1b7860000000
480008357fe3fb78 480008157fe3fb78
3821017060000000 3821017060000000
480012dc7fc3f378 480012bc7fc3f378
0100000000000000 0100000000000000
4e80002000000280 4e80002000000280
0000000000000000 0000000000000000
@ -534,256 +534,252 @@ f92101c0f90101b8
7c0802a63842955c 7c0802a63842955c
7d800026fbe1fff8 7d800026fbe1fff8
91810008f8010010 91810008f8010010
48000729f821ff91 48000709f821ff91
3c62ffff60000000 3c62ffff60000000
4bffff3538637d60 4bffff3538637d40
548400023880ffff 548400023880ffff
7c8026ea7c0004ac 7c8026ea7c0004ac
3fe0c0003c62ffff 3fe0c0003c62ffff
63ff000838637d80 63ff000838637d60
3c62ffff4bffff11 3c62ffff4bffff11
38637da07bff0020 38637d807bff0020
7c0004ac4bffff01 7c0004ac4bffff01
73e900017fe0feea 73e900017fe0feea
3c62ffff41820010 3c62ffff41820010
4bfffee538637db8 4bfffee538637d98
4d80000073e90002 4d80000073e90002
3c62ffff41820010 3c62ffff41820010
4bfffecd38637dc0 4bfffecd38637da0
4e00000073e90004 4e00000073e90004
3c62ffff41820010 3c62ffff41820010
4bfffeb538637dc8 4bfffeb538637da8
3bff7fc03fe2ffff 3bff7fa03fe2ffff
4bfffea57fe3fb78 4bfffea57fe3fb78
3c80c00041920028 3c80c00041920028
7884002060840010 7884002060840010
7c8026ea7c0004ac 7c8026ea7c0004ac
7884b2823c62ffff 7884b2823c62ffff
4bfffe7d38637dd0 4bfffe7d38637db0
3c80c000418e004c 3c80c000418e004c
7884002060840018 7884002060840018
7c8026ea7c0004ac 7c8026ea7c0004ac
788465023c62ffff 788465023c62ffff
4bfffe5538637df0 4bfffe5538637dd0
608400303c80c000 608400303c80c000
7c0004ac78840020 7c0004ac78840020
3c62ffff7c8026ea 3c62ffff7c8026ea
38637e107884b282 38637df07884b282
3d20c0004bfffe31 3d20c0004bfffe31
7929002061290020 7929002061290020
7d204eea7c0004ac 7d204eea7c0004ac
3c62ffff3c80000f 3c62ffff3c80000f
38637e3060844240 38637e1060844240
4bfffe057c892392 4bfffe057c892392
4bfffdfd7fe3fb78 4bfffdfd7fe3fb78
3ca2ffff418e0028 3ca2ffff418e0028
3c62ffff3c82ffff 3c62ffff3c82ffff
38847e6038a57e50 38847e4038a57e30
4bfffddd38637e68 4bfffddd38637e48
6000000048000455 6000000048000419
3c62ffff41920020 3c62ffff41920020
4bfffdc538637e98 4bfffdc538637e78
8181000838210070 8181000838210070
480010f87d818120 480010d87d818120
38637eb03c62ffff 38637e903c62ffff
3c80f0004bfffda9 3c80f0004bfffda9
6084400038a0ffff 6084400038a0ffff
7884002054a50422 7884002054a50422
480007cd3c604000 480007ad3c604000
3c62ffff60000000 3c62ffff60000000
4bfffd7d38637ed0 4bfffd7d38637eb0
e801001038210070 e801001038210070
ebe1fff881810008 ebe1fff881810008
7d8181207c0803a6 7d8181207c0803a6
000000004bfffde4 000000004bfffde4
0000018003000000 0000018003000000
7869c0223d40c010 612908043d20c010
794a0020614a080c
7d20572a7c0004ac
612908103d20c010
7c0004ac79290020 7c0004ac79290020
4e8000207c604f2a 3d40c0107c604f2a
614a080839200001
7c0004ac794a0020
4e8000207d20572a
0000000000000000 0000000000000000
3d20c01000000000 3c4c000100000000
7929002061290804 7c0802a63842930c
7c604f2a7c0004ac 614a08003d40c010
392000013d40c010 794a002039200001
794a0020614a0808 f821ffa1f8010010
7d20572a7c0004ac 7d20572a7c0004ac
000000004e800020 38637f803c62ffff
0000000000000000 600000004bfffce1
384292d03c4c0001 e801001038210060
3d40c0107c0802a6 4e8000207c0803a6
39200001614a0800 0100000000000000
f8010010794a0020 3c4c000100000080
7c0004acf821ffa1 7c0802a6384292b4
3c62ffff7d20572a 7d0903a639000080
4bfffca538637fa0 3d2040003d40aaaa
3821006060000000 48000f55614aaaaa
7c0803a6e8010010 91490000f821ff81
000000004e800020
0000008001000000
384292783c4c0001
390000807c0802a6
3d40aaaa7d0903a6
614aaaaa3d204000
f821ff8148000f39
3929000491490000
4bfffcc14200fff8
3940008060000000
7d4903a63d00aaaa
3be000003d204000
814900006108aaaa
419e000c7f8a4000
7fff07b43bff0001
4200ffe839290004
3d40555539000080
3d2040007d0903a6
91490000614a5555
4200fff839290004 4200fff839290004
600000004bfffc65 600000004bfffcfd
3d00555539400080 3d00aaaa39400080
3d2040007d4903a6 3d2040007d4903a6
8149000061085555 6108aaaa3be00000
419e000c7f8a4000 7f8a400081490000
7fff07b43bff0001 3bff0001419e000c
4200ffe839290004 392900047fff07b4
419e001c2fbf0000 390000804200ffe8
38a001003c62ffff 7d0903a63d405555
38637ee87fe4fb78 614a55553d204000
600000004bfffba1 3929000491490000
3ce0802039000100 4bfffca14200fff8
60e700037d0903a6 3940008060000000
392000013d404000 7d4903a63d005555
7928f84278e70020 610855553d204000
7d2900d0792907e0 7f8a400081490000
7d293838394a0004 3bff0001419e000c
912afffc7d294278 392900047fff07b4
4bfffbd14200ffe4 2fbf00004200ffe8
3c62ffff419e001c
7fe4fb7838a00100
4bfffbdd38637ec8
3900010060000000 3900010060000000
7d0903a63ce08020 7d0903a63ce08020
3d40400060e70003 3d40400060e70003
392000013ba00000 78e7002039200001
7928f84278e70020 792907e07928f842
7d2900d0792907e0 394a00047d2900d0
7d2942787d293838 7d2942787d293838
7f884840810a0000 4200ffe4912afffc
3bbd0001419e000c 600000004bfffc0d
394a00047fbd07b4 3ce0802039000100
2fbd00004200ffd4 60e700037d0903a6
3c62ffff419e001c 3ba000003d404000
7fa4eb7838a00100 78e7002039200001
4bfffaed38637f10 792907e07928f842
3920002060000000 7d2938387d2900d0
7d2903a639400000 810a00007d294278
794800203d2a1000 419e000c7f884840
394a000139290002 7fbd07b43bbd0001
9109000079291764 4200ffd4394a0004
4bfffb314200ffe8 419e001c2fbd0000
3920002060000000 38a001003c62ffff
7d2903a639400000 38637ef07fa4eb78
3d2a10003bc00000 600000004bfffb29
8129000879291764 3940000039200020
7f8950005529043e 3d2a10007d2903a6
3bde0001419e000c 3929000279480020
394a00017fde07b4 79291764394a0001
2fbe00004200ffdc 4200ffe891090000
3c62ffff419e001c 600000004bfffb6d
7fc4f37838a00020 3940000039200020
4bfffa6538637f38 3bc000007d2903a6
7fffea1460000000 792917643d2a1000
7ffff21438600000 5529043e81290008
409e00ac2f9f0000 419e000c7f895000
38637f603c62ffff 7fde07b43bde0001
600000004bfffa41 4200ffdc394a0001
394000807c9602a6 419e001c2fbe0000
7d4903a678840020 38a000203c62ffff
3d49080039200000 38637f187fc4f378
f92a0000794a1f24 600000004bfffaa1
4200fff039290001 386000007fffea14
7c9f20507ff602a6 2f9f00007ffff214
63ff80003fe0000c 3c62ffff409e00ac
4bfffa717fff2396 4bfffa7d38637f40
7bff002060000000 7c9602a660000000
390000807d3602a6 7884002039400080
7d0903a679290020 392000007d4903a6
e90a00003d404000 794a1f243d490800
4200fff8394a0008 39290001f92a0000
7d2548507cb602a6 7ff602a64200fff0
60a580003ca0000c 3fe0000c7c9f2050
7ca54b963c62ffff 7fff239663ff8000
38637f707fe4fb78 600000004bfffaad
4bfff9ad78a50320 7d3602a67bff0020
3860000160000000 7929002039000080
48000cc438210080 3d4040007d0903a6
0100000000000000 394a0008e90a0000
3c4c000100000380 7cb602a64200fff8
7c0802a638428f84 3ca0000c7d254850
38637fc83c62ffff 3c62ffff60a58000
f821ff7148000c49 7fe4fb787ca54b96
3bc000003f80c010 78a5032038637f50
7b9c0020639c1000 600000004bfff9e9
600000004bfff961 3821008038600001
7fc0e72a7c0004ac 0000000048000ce0
637b10043f60c010 0000038001000000
7c0004ac7b7b0020 38428fc03c4c0001
3fe0c0107fc0df2a 3c62ffff7c0802a6
63ff081438600000 48000c6138637fa8
7bff00204bfffbe1 3f60c010f821ff71
7fc0ff2a7c0004ac 637b10003be00000
3920000c3fa0c010 4bfff99d7b7b0020
7bbd002063bd0800 7c0004ac60000000
3f40c0107fe0df2a
7b5a0020635a1004
7fe0d72a7c0004ac
63bd080c3fa0c010
7c0004ac7bbd0020
3fc0c0107fe0ef2a
7bde002063de0810
7fe0f72a7c0004ac
3940000c3d20c010
7929002061290800
7d404f2a7c0004ac
7fe0ef2a7c0004ac
7fe0f72a7c0004ac
7c0004ac3940000e
392002007d404f2a
7d20ef2a7c0004ac 7d20ef2a7c0004ac
4bfffbb538600000 7c0004ac39200002
7fc0ff2a7c0004ac 3860000f7d20f72a
7c0004ac3920000e 7c0004ac4bfffbb1
386002007d20ef2a 392000037fe0ef2a
392000024bfffb99 7d20f72a7c0004ac
7d20ff2a7c0004ac 4bfffb953860000f
4bfffbc13860000f 7c0004ac39200006
4bfffb7d38600000 3b8000017d20ef2a
7c0004ac39200003 7f80f72a7c0004ac
3860000f7d20ff2a 4bfffb753860000f
4bfffba13ba00001 7c0004ac39200920
4bfffb5d38600006 7c0004ac7d20ef2a
7fa0ff2a7c0004ac 3860000f7fe0f72a
4bfffb893860000f 392004004bfffb59
4bfffb4538600920 7d20ef2a7c0004ac
7fc0ff2a7c0004ac 7fe0f72a7c0004ac
4bfffb713860000f 4bfffb3d38600003
4bfffb2d38600400 4bfffbd14bfffb7d
7fc0ff2a7c0004ac
4bfffb5938600003
4bfffbed4bfffb99
4082001c2c230000 4082001c2c230000
7fa0e72a7c0004ac 7f80df2a7c0004ac
7fa0df2a7c0004ac 7f80d72a7c0004ac
48000b6438210090 48000b6038210090
7fa0e72a7c0004ac 7f80df2a7c0004ac
4bffffec38600001 4bffffec38600001
0100000000000000 0100000000000000
3c4c000100000580 3c4c000100000680
3d20c00038428e1c 3d20c00038428e3c
6129200060000000 6129200060000000
f922803079290020 f922801079290020
612900203d20c000 612900203d20c000
7c0004ac79290020 7c0004ac79290020
3d40001c7d204eea 3d40001c7d204eea
7d295392614a2000 7d295392614a2000
394a0018e9428030 394a0018e9428010
7c0004ac3929ffff 7c0004ac3929ffff
4e8000207d2057ea 4e8000207d2057ea
0000000000000000 0000000000000000
3c4c000100000000 3c4c000100000000
6000000038428dbc 6000000038428ddc
39290010e9228030 39290010e9228010
7d204eea7c0004ac 7d204eea7c0004ac
4082ffe871290008 4082ffe871290008
e94280305469063e e94280105469063e
7d2057ea7c0004ac 7d2057ea7c0004ac
000000004e800020 000000004e800020
0000000000000000 0000000000000000
38428d783c4c0001 38428d983c4c0001
fbc1fff07c0802a6 fbc1fff07c0802a6
3bc3fffffbe1fff8 3bc3fffffbe1fff8
f821ffd1f8010010 f821ffd1f8010010
@ -857,7 +853,7 @@ f924000039290002
7c6307b43863ffe0 7c6307b43863ffe0
000000004e800020 000000004e800020
0000000000000000 0000000000000000
38428b283c4c0001 38428b483c4c0001
3d2037367c0802a6 3d2037367c0802a6
612935347d908026 612935347d908026
65293332792907c6 65293332792907c6
@ -891,7 +887,7 @@ fbfd00007fe9fa14
4bfffff07d29f392 4bfffff07d29f392
0300000000000000 0300000000000000
3c4c000100000580 3c4c000100000580
7c0802a638428a1c 7c0802a638428a3c
f821ffb1480006e9 f821ffb1480006e9
7c7f1b78eb630000 7c7f1b78eb630000
7cbd2b787c9c2378 7cbd2b787c9c2378
@ -907,7 +903,7 @@ f821ffb1480006e9
4bffffb8f93f0000 4bffffb8f93f0000
0100000000000000 0100000000000000
3c4c000100000580 3c4c000100000580
7c0802a63842899c 7c0802a6384289bc
f821ffa148000661 f821ffa148000661
7c9b23787c7d1b78 7c9b23787c7d1b78
388000007ca32b78 388000007ca32b78
@ -938,7 +934,7 @@ e95d00009b270000
f95d0000394a0001 f95d0000394a0001
000000004bffffa8 000000004bffffa8
0000078001000000 0000078001000000
384288a03c4c0001 384288c03c4c0001
480005397c0802a6 480005397c0802a6
7c741b79f821fed1 7c741b79f821fed1
38600000f8610060 38600000f8610060
@ -947,7 +943,7 @@ f95d0000394a0001
3ac4ffff3e42ffff 3ac4ffff3e42ffff
f92100703b410020 f92100703b410020
3ae0000060000000 3ae0000060000000
3a527fe039228028 3a527fc039228008
f92100783ba10060 f92100783ba10060
ebc1006089250000 ebc1006089250000
419e00102fa90000 419e00102fa90000

656
litedram/generated/sim/litedram_core.v
Unescape Escape View File

@ -1,5 +1,5 @@
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:39 // Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:54
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
module litedram_core( module litedram_core(
input wire clk, input wire clk,
@ -33,8 +33,8 @@ module litedram_core(


reg [13:0] litedramcore_adr = 14'd0; reg [13:0] litedramcore_adr = 14'd0;
reg litedramcore_we = 1'd0; reg litedramcore_we = 1'd0;
wire [7:0] litedramcore_dat_w; wire [31:0] litedramcore_dat_w;
wire [7:0] litedramcore_dat_r; wire [31:0] litedramcore_dat_r;
wire [29:0] litedramcore_wishbone_adr; wire [29:0] litedramcore_wishbone_adr;
wire [31:0] litedramcore_wishbone_dat_w; wire [31:0] litedramcore_wishbone_dat_w;
wire [31:0] litedramcore_wishbone_dat_r; wire [31:0] litedramcore_wishbone_dat_r;
@ -1638,8 +1638,8 @@ reg new_master_rdata_valid8 = 1'd0;
reg new_master_rdata_valid9 = 1'd0; reg new_master_rdata_valid9 = 1'd0;
wire [13:0] interface0_bank_bus_adr; wire [13:0] interface0_bank_bus_adr;
wire interface0_bank_bus_we; wire interface0_bank_bus_we;
wire [7:0] interface0_bank_bus_dat_w; wire [31:0] interface0_bank_bus_dat_w;
reg [7:0] interface0_bank_bus_dat_r = 8'd0; reg [31:0] interface0_bank_bus_dat_r = 32'd0;
wire csrbank0_init_done0_re; wire csrbank0_init_done0_re;
wire csrbank0_init_done0_r; wire csrbank0_init_done0_r;
wire csrbank0_init_done0_we; wire csrbank0_init_done0_we;
@ -1651,8 +1651,8 @@ wire csrbank0_init_error0_w;
wire csrbank0_sel; wire csrbank0_sel;
wire [13:0] interface1_bank_bus_adr; wire [13:0] interface1_bank_bus_adr;
wire interface1_bank_bus_we; wire interface1_bank_bus_we;
wire [7:0] interface1_bank_bus_dat_w; wire [31:0] interface1_bank_bus_dat_w;
reg [7:0] interface1_bank_bus_dat_r = 8'd0; reg [31:0] interface1_bank_bus_dat_r = 32'd0;
wire csrbank1_dfii_control0_re; wire csrbank1_dfii_control0_re;
wire [3:0] csrbank1_dfii_control0_r; wire [3:0] csrbank1_dfii_control0_r;
wire csrbank1_dfii_control0_we; wire csrbank1_dfii_control0_we;
@ -1661,199 +1661,87 @@ wire csrbank1_dfii_pi0_command0_re;
wire [5:0] csrbank1_dfii_pi0_command0_r; wire [5:0] csrbank1_dfii_pi0_command0_r;
wire csrbank1_dfii_pi0_command0_we; wire csrbank1_dfii_pi0_command0_we;
wire [5:0] csrbank1_dfii_pi0_command0_w; wire [5:0] csrbank1_dfii_pi0_command0_w;
wire csrbank1_dfii_pi0_address1_re;
wire [5:0] csrbank1_dfii_pi0_address1_r;
wire csrbank1_dfii_pi0_address1_we;
wire [5:0] csrbank1_dfii_pi0_address1_w;
wire csrbank1_dfii_pi0_address0_re; wire csrbank1_dfii_pi0_address0_re;
wire [7:0] csrbank1_dfii_pi0_address0_r; wire [13:0] csrbank1_dfii_pi0_address0_r;
wire csrbank1_dfii_pi0_address0_we; wire csrbank1_dfii_pi0_address0_we;
wire [7:0] csrbank1_dfii_pi0_address0_w; wire [13:0] csrbank1_dfii_pi0_address0_w;
wire csrbank1_dfii_pi0_baddress0_re; wire csrbank1_dfii_pi0_baddress0_re;
wire [2:0] csrbank1_dfii_pi0_baddress0_r; wire [2:0] csrbank1_dfii_pi0_baddress0_r;
wire csrbank1_dfii_pi0_baddress0_we; wire csrbank1_dfii_pi0_baddress0_we;
wire [2:0] csrbank1_dfii_pi0_baddress0_w; wire [2:0] csrbank1_dfii_pi0_baddress0_w;
wire csrbank1_dfii_pi0_wrdata3_re;
wire [7:0] csrbank1_dfii_pi0_wrdata3_r;
wire csrbank1_dfii_pi0_wrdata3_we;
wire [7:0] csrbank1_dfii_pi0_wrdata3_w;
wire csrbank1_dfii_pi0_wrdata2_re;
wire [7:0] csrbank1_dfii_pi0_wrdata2_r;
wire csrbank1_dfii_pi0_wrdata2_we;
wire [7:0] csrbank1_dfii_pi0_wrdata2_w;
wire csrbank1_dfii_pi0_wrdata1_re;
wire [7:0] csrbank1_dfii_pi0_wrdata1_r;
wire csrbank1_dfii_pi0_wrdata1_we;
wire [7:0] csrbank1_dfii_pi0_wrdata1_w;
wire csrbank1_dfii_pi0_wrdata0_re; wire csrbank1_dfii_pi0_wrdata0_re;
wire [7:0] csrbank1_dfii_pi0_wrdata0_r; wire [31:0] csrbank1_dfii_pi0_wrdata0_r;
wire csrbank1_dfii_pi0_wrdata0_we; wire csrbank1_dfii_pi0_wrdata0_we;
wire [7:0] csrbank1_dfii_pi0_wrdata0_w; wire [31:0] csrbank1_dfii_pi0_wrdata0_w;
wire csrbank1_dfii_pi0_rddata3_re; wire csrbank1_dfii_pi0_rddata_re;
wire [7:0] csrbank1_dfii_pi0_rddata3_r; wire [31:0] csrbank1_dfii_pi0_rddata_r;
wire csrbank1_dfii_pi0_rddata3_we; wire csrbank1_dfii_pi0_rddata_we;
wire [7:0] csrbank1_dfii_pi0_rddata3_w; wire [31:0] csrbank1_dfii_pi0_rddata_w;
wire csrbank1_dfii_pi0_rddata2_re;
wire [7:0] csrbank1_dfii_pi0_rddata2_r;
wire csrbank1_dfii_pi0_rddata2_we;
wire [7:0] csrbank1_dfii_pi0_rddata2_w;
wire csrbank1_dfii_pi0_rddata1_re;
wire [7:0] csrbank1_dfii_pi0_rddata1_r;
wire csrbank1_dfii_pi0_rddata1_we;
wire [7:0] csrbank1_dfii_pi0_rddata1_w;
wire csrbank1_dfii_pi0_rddata0_re;
wire [7:0] csrbank1_dfii_pi0_rddata0_r;
wire csrbank1_dfii_pi0_rddata0_we;
wire [7:0] csrbank1_dfii_pi0_rddata0_w;
wire csrbank1_dfii_pi1_command0_re; wire csrbank1_dfii_pi1_command0_re;
wire [5:0] csrbank1_dfii_pi1_command0_r; wire [5:0] csrbank1_dfii_pi1_command0_r;
wire csrbank1_dfii_pi1_command0_we; wire csrbank1_dfii_pi1_command0_we;
wire [5:0] csrbank1_dfii_pi1_command0_w; wire [5:0] csrbank1_dfii_pi1_command0_w;
wire csrbank1_dfii_pi1_address1_re;
wire [5:0] csrbank1_dfii_pi1_address1_r;
wire csrbank1_dfii_pi1_address1_we;
wire [5:0] csrbank1_dfii_pi1_address1_w;
wire csrbank1_dfii_pi1_address0_re; wire csrbank1_dfii_pi1_address0_re;
wire [7:0] csrbank1_dfii_pi1_address0_r; wire [13:0] csrbank1_dfii_pi1_address0_r;
wire csrbank1_dfii_pi1_address0_we; wire csrbank1_dfii_pi1_address0_we;
wire [7:0] csrbank1_dfii_pi1_address0_w; wire [13:0] csrbank1_dfii_pi1_address0_w;
wire csrbank1_dfii_pi1_baddress0_re; wire csrbank1_dfii_pi1_baddress0_re;
wire [2:0] csrbank1_dfii_pi1_baddress0_r; wire [2:0] csrbank1_dfii_pi1_baddress0_r;
wire csrbank1_dfii_pi1_baddress0_we; wire csrbank1_dfii_pi1_baddress0_we;
wire [2:0] csrbank1_dfii_pi1_baddress0_w; wire [2:0] csrbank1_dfii_pi1_baddress0_w;
wire csrbank1_dfii_pi1_wrdata3_re;
wire [7:0] csrbank1_dfii_pi1_wrdata3_r;
wire csrbank1_dfii_pi1_wrdata3_we;
wire [7:0] csrbank1_dfii_pi1_wrdata3_w;
wire csrbank1_dfii_pi1_wrdata2_re;
wire [7:0] csrbank1_dfii_pi1_wrdata2_r;
wire csrbank1_dfii_pi1_wrdata2_we;
wire [7:0] csrbank1_dfii_pi1_wrdata2_w;
wire csrbank1_dfii_pi1_wrdata1_re;
wire [7:0] csrbank1_dfii_pi1_wrdata1_r;
wire csrbank1_dfii_pi1_wrdata1_we;
wire [7:0] csrbank1_dfii_pi1_wrdata1_w;
wire csrbank1_dfii_pi1_wrdata0_re; wire csrbank1_dfii_pi1_wrdata0_re;
wire [7:0] csrbank1_dfii_pi1_wrdata0_r; wire [31:0] csrbank1_dfii_pi1_wrdata0_r;
wire csrbank1_dfii_pi1_wrdata0_we; wire csrbank1_dfii_pi1_wrdata0_we;
wire [7:0] csrbank1_dfii_pi1_wrdata0_w; wire [31:0] csrbank1_dfii_pi1_wrdata0_w;
wire csrbank1_dfii_pi1_rddata3_re; wire csrbank1_dfii_pi1_rddata_re;
wire [7:0] csrbank1_dfii_pi1_rddata3_r; wire [31:0] csrbank1_dfii_pi1_rddata_r;
wire csrbank1_dfii_pi1_rddata3_we; wire csrbank1_dfii_pi1_rddata_we;
wire [7:0] csrbank1_dfii_pi1_rddata3_w; wire [31:0] csrbank1_dfii_pi1_rddata_w;
wire csrbank1_dfii_pi1_rddata2_re;
wire [7:0] csrbank1_dfii_pi1_rddata2_r;
wire csrbank1_dfii_pi1_rddata2_we;
wire [7:0] csrbank1_dfii_pi1_rddata2_w;
wire csrbank1_dfii_pi1_rddata1_re;
wire [7:0] csrbank1_dfii_pi1_rddata1_r;
wire csrbank1_dfii_pi1_rddata1_we;
wire [7:0] csrbank1_dfii_pi1_rddata1_w;
wire csrbank1_dfii_pi1_rddata0_re;
wire [7:0] csrbank1_dfii_pi1_rddata0_r;
wire csrbank1_dfii_pi1_rddata0_we;
wire [7:0] csrbank1_dfii_pi1_rddata0_w;
wire csrbank1_dfii_pi2_command0_re; wire csrbank1_dfii_pi2_command0_re;
wire [5:0] csrbank1_dfii_pi2_command0_r; wire [5:0] csrbank1_dfii_pi2_command0_r;
wire csrbank1_dfii_pi2_command0_we; wire csrbank1_dfii_pi2_command0_we;
wire [5:0] csrbank1_dfii_pi2_command0_w; wire [5:0] csrbank1_dfii_pi2_command0_w;
wire csrbank1_dfii_pi2_address1_re;
wire [5:0] csrbank1_dfii_pi2_address1_r;
wire csrbank1_dfii_pi2_address1_we;
wire [5:0] csrbank1_dfii_pi2_address1_w;
wire csrbank1_dfii_pi2_address0_re; wire csrbank1_dfii_pi2_address0_re;
wire [7:0] csrbank1_dfii_pi2_address0_r; wire [13:0] csrbank1_dfii_pi2_address0_r;
wire csrbank1_dfii_pi2_address0_we; wire csrbank1_dfii_pi2_address0_we;
wire [7:0] csrbank1_dfii_pi2_address0_w; wire [13:0] csrbank1_dfii_pi2_address0_w;
wire csrbank1_dfii_pi2_baddress0_re; wire csrbank1_dfii_pi2_baddress0_re;
wire [2:0] csrbank1_dfii_pi2_baddress0_r; wire [2:0] csrbank1_dfii_pi2_baddress0_r;
wire csrbank1_dfii_pi2_baddress0_we; wire csrbank1_dfii_pi2_baddress0_we;
wire [2:0] csrbank1_dfii_pi2_baddress0_w; wire [2:0] csrbank1_dfii_pi2_baddress0_w;
wire csrbank1_dfii_pi2_wrdata3_re;
wire [7:0] csrbank1_dfii_pi2_wrdata3_r;
wire csrbank1_dfii_pi2_wrdata3_we;
wire [7:0] csrbank1_dfii_pi2_wrdata3_w;
wire csrbank1_dfii_pi2_wrdata2_re;
wire [7:0] csrbank1_dfii_pi2_wrdata2_r;
wire csrbank1_dfii_pi2_wrdata2_we;
wire [7:0] csrbank1_dfii_pi2_wrdata2_w;
wire csrbank1_dfii_pi2_wrdata1_re;
wire [7:0] csrbank1_dfii_pi2_wrdata1_r;
wire csrbank1_dfii_pi2_wrdata1_we;
wire [7:0] csrbank1_dfii_pi2_wrdata1_w;
wire csrbank1_dfii_pi2_wrdata0_re; wire csrbank1_dfii_pi2_wrdata0_re;
wire [7:0] csrbank1_dfii_pi2_wrdata0_r; wire [31:0] csrbank1_dfii_pi2_wrdata0_r;
wire csrbank1_dfii_pi2_wrdata0_we; wire csrbank1_dfii_pi2_wrdata0_we;
wire [7:0] csrbank1_dfii_pi2_wrdata0_w; wire [31:0] csrbank1_dfii_pi2_wrdata0_w;
wire csrbank1_dfii_pi2_rddata3_re; wire csrbank1_dfii_pi2_rddata_re;
wire [7:0] csrbank1_dfii_pi2_rddata3_r; wire [31:0] csrbank1_dfii_pi2_rddata_r;
wire csrbank1_dfii_pi2_rddata3_we; wire csrbank1_dfii_pi2_rddata_we;
wire [7:0] csrbank1_dfii_pi2_rddata3_w; wire [31:0] csrbank1_dfii_pi2_rddata_w;
wire csrbank1_dfii_pi2_rddata2_re;
wire [7:0] csrbank1_dfii_pi2_rddata2_r;
wire csrbank1_dfii_pi2_rddata2_we;
wire [7:0] csrbank1_dfii_pi2_rddata2_w;
wire csrbank1_dfii_pi2_rddata1_re;
wire [7:0] csrbank1_dfii_pi2_rddata1_r;
wire csrbank1_dfii_pi2_rddata1_we;
wire [7:0] csrbank1_dfii_pi2_rddata1_w;
wire csrbank1_dfii_pi2_rddata0_re;
wire [7:0] csrbank1_dfii_pi2_rddata0_r;
wire csrbank1_dfii_pi2_rddata0_we;
wire [7:0] csrbank1_dfii_pi2_rddata0_w;
wire csrbank1_dfii_pi3_command0_re; wire csrbank1_dfii_pi3_command0_re;
wire [5:0] csrbank1_dfii_pi3_command0_r; wire [5:0] csrbank1_dfii_pi3_command0_r;
wire csrbank1_dfii_pi3_command0_we; wire csrbank1_dfii_pi3_command0_we;
wire [5:0] csrbank1_dfii_pi3_command0_w; wire [5:0] csrbank1_dfii_pi3_command0_w;
wire csrbank1_dfii_pi3_address1_re;
wire [5:0] csrbank1_dfii_pi3_address1_r;
wire csrbank1_dfii_pi3_address1_we;
wire [5:0] csrbank1_dfii_pi3_address1_w;
wire csrbank1_dfii_pi3_address0_re; wire csrbank1_dfii_pi3_address0_re;
wire [7:0] csrbank1_dfii_pi3_address0_r; wire [13:0] csrbank1_dfii_pi3_address0_r;
wire csrbank1_dfii_pi3_address0_we; wire csrbank1_dfii_pi3_address0_we;
wire [7:0] csrbank1_dfii_pi3_address0_w; wire [13:0] csrbank1_dfii_pi3_address0_w;
wire csrbank1_dfii_pi3_baddress0_re; wire csrbank1_dfii_pi3_baddress0_re;
wire [2:0] csrbank1_dfii_pi3_baddress0_r; wire [2:0] csrbank1_dfii_pi3_baddress0_r;
wire csrbank1_dfii_pi3_baddress0_we; wire csrbank1_dfii_pi3_baddress0_we;
wire [2:0] csrbank1_dfii_pi3_baddress0_w; wire [2:0] csrbank1_dfii_pi3_baddress0_w;
wire csrbank1_dfii_pi3_wrdata3_re;
wire [7:0] csrbank1_dfii_pi3_wrdata3_r;
wire csrbank1_dfii_pi3_wrdata3_we;
wire [7:0] csrbank1_dfii_pi3_wrdata3_w;
wire csrbank1_dfii_pi3_wrdata2_re;
wire [7:0] csrbank1_dfii_pi3_wrdata2_r;
wire csrbank1_dfii_pi3_wrdata2_we;
wire [7:0] csrbank1_dfii_pi3_wrdata2_w;
wire csrbank1_dfii_pi3_wrdata1_re;
wire [7:0] csrbank1_dfii_pi3_wrdata1_r;
wire csrbank1_dfii_pi3_wrdata1_we;
wire [7:0] csrbank1_dfii_pi3_wrdata1_w;
wire csrbank1_dfii_pi3_wrdata0_re; wire csrbank1_dfii_pi3_wrdata0_re;
wire [7:0] csrbank1_dfii_pi3_wrdata0_r; wire [31:0] csrbank1_dfii_pi3_wrdata0_r;
wire csrbank1_dfii_pi3_wrdata0_we; wire csrbank1_dfii_pi3_wrdata0_we;
wire [7:0] csrbank1_dfii_pi3_wrdata0_w; wire [31:0] csrbank1_dfii_pi3_wrdata0_w;
wire csrbank1_dfii_pi3_rddata3_re; wire csrbank1_dfii_pi3_rddata_re;
wire [7:0] csrbank1_dfii_pi3_rddata3_r; wire [31:0] csrbank1_dfii_pi3_rddata_r;
wire csrbank1_dfii_pi3_rddata3_we; wire csrbank1_dfii_pi3_rddata_we;
wire [7:0] csrbank1_dfii_pi3_rddata3_w; wire [31:0] csrbank1_dfii_pi3_rddata_w;
wire csrbank1_dfii_pi3_rddata2_re;
wire [7:0] csrbank1_dfii_pi3_rddata2_r;
wire csrbank1_dfii_pi3_rddata2_we;
wire [7:0] csrbank1_dfii_pi3_rddata2_w;
wire csrbank1_dfii_pi3_rddata1_re;
wire [7:0] csrbank1_dfii_pi3_rddata1_r;
wire csrbank1_dfii_pi3_rddata1_we;
wire [7:0] csrbank1_dfii_pi3_rddata1_w;
wire csrbank1_dfii_pi3_rddata0_re;
wire [7:0] csrbank1_dfii_pi3_rddata0_r;
wire csrbank1_dfii_pi3_rddata0_we;
wire [7:0] csrbank1_dfii_pi3_rddata0_w;
wire csrbank1_sel; wire csrbank1_sel;
wire [13:0] adr; wire [13:0] adr;
wire we; wire we;
wire [7:0] dat_w; wire [31:0] dat_w;
wire [7:0] dat_r; wire [31:0] dat_r;
wire [24:0] slice_proxy0; wire [24:0] slice_proxy0;
wire [24:0] slice_proxy1; wire [24:0] slice_proxy1;
wire [24:0] slice_proxy2; wire [24:0] slice_proxy2;
@ -9892,217 +9780,105 @@ assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage; assign csrbank0_init_error0_w = init_error_storage;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0]; assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 1'd0)); assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd0));
assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 1'd0)); assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd0));
assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0]; assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 1'd1)); assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd1));
assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 1'd1)); assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd1));
assign litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0]; assign litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 2'd2)); assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd2));
assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 2'd2)); assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd2));
assign csrbank1_dfii_pi0_address1_r = interface1_bank_bus_dat_w[5:0]; assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0];
assign csrbank1_dfii_pi0_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 2'd3)); assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd3));
assign csrbank1_dfii_pi0_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 2'd3)); assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd3));
assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd4));
assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd4));
assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0]; assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd5)); assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd4));
assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd5)); assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd4));
assign csrbank1_dfii_pi0_wrdata3_r = interface1_bank_bus_dat_w[7:0]; assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi0_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd6)); assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd5));
assign csrbank1_dfii_pi0_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd6)); assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd5));
assign csrbank1_dfii_pi0_wrdata2_r = interface1_bank_bus_dat_w[7:0]; assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi0_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd7)); assign csrbank1_dfii_pi0_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd6));
assign csrbank1_dfii_pi0_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd7)); assign csrbank1_dfii_pi0_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd6));
assign csrbank1_dfii_pi0_wrdata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd8));
assign csrbank1_dfii_pi0_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd8));
assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd9));
assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd9));
assign csrbank1_dfii_pi0_rddata3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd10));
assign csrbank1_dfii_pi0_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd10));
assign csrbank1_dfii_pi0_rddata2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd11));
assign csrbank1_dfii_pi0_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd11));
assign csrbank1_dfii_pi0_rddata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd12));
assign csrbank1_dfii_pi0_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd12));
assign csrbank1_dfii_pi0_rddata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd13));
assign csrbank1_dfii_pi0_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd13));
assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0]; assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd14)); assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd7));
assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd14)); assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd7));
assign litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0]; assign litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd15)); assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd8));
assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd15)); assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd8));
assign csrbank1_dfii_pi1_address1_r = interface1_bank_bus_dat_w[5:0]; assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0];
assign csrbank1_dfii_pi1_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd16)); assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd9));
assign csrbank1_dfii_pi1_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd16)); assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd9));
assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd17));
assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd17));
assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0]; assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd18)); assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd10));
assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd18)); assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd10));
assign csrbank1_dfii_pi1_wrdata3_r = interface1_bank_bus_dat_w[7:0]; assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi1_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd19)); assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd11));
assign csrbank1_dfii_pi1_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd19)); assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd11));
assign csrbank1_dfii_pi1_wrdata2_r = interface1_bank_bus_dat_w[7:0]; assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi1_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd20)); assign csrbank1_dfii_pi1_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd12));
assign csrbank1_dfii_pi1_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd20)); assign csrbank1_dfii_pi1_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd12));
assign csrbank1_dfii_pi1_wrdata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd21));
assign csrbank1_dfii_pi1_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd21));
assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd22));
assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd22));
assign csrbank1_dfii_pi1_rddata3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd23));
assign csrbank1_dfii_pi1_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd23));
assign csrbank1_dfii_pi1_rddata2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd24));
assign csrbank1_dfii_pi1_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd24));
assign csrbank1_dfii_pi1_rddata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd25));
assign csrbank1_dfii_pi1_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd25));
assign csrbank1_dfii_pi1_rddata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd26));
assign csrbank1_dfii_pi1_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd26));
assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0]; assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd27)); assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd13));
assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd27)); assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd13));
assign litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0]; assign litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd28)); assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd14));
assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd28)); assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd14));
assign csrbank1_dfii_pi2_address1_r = interface1_bank_bus_dat_w[5:0]; assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0];
assign csrbank1_dfii_pi2_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd29)); assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd15));
assign csrbank1_dfii_pi2_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd29)); assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd15));
assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd30));
assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd30));
assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0]; assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd31)); assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd16));
assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd31)); assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd16));
assign csrbank1_dfii_pi2_wrdata3_r = interface1_bank_bus_dat_w[7:0]; assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi2_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd32)); assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd17));
assign csrbank1_dfii_pi2_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd32)); assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd17));
assign csrbank1_dfii_pi2_wrdata2_r = interface1_bank_bus_dat_w[7:0]; assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi2_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd33)); assign csrbank1_dfii_pi2_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd18));
assign csrbank1_dfii_pi2_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd33)); assign csrbank1_dfii_pi2_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd18));
assign csrbank1_dfii_pi2_wrdata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd34));
assign csrbank1_dfii_pi2_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd34));
assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd35));
assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd35));
assign csrbank1_dfii_pi2_rddata3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd36));
assign csrbank1_dfii_pi2_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd36));
assign csrbank1_dfii_pi2_rddata2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd37));
assign csrbank1_dfii_pi2_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd37));
assign csrbank1_dfii_pi2_rddata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd38));
assign csrbank1_dfii_pi2_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd38));
assign csrbank1_dfii_pi2_rddata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd39));
assign csrbank1_dfii_pi2_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd39));
assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0]; assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd40)); assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd19));
assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd40)); assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd19));
assign litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0]; assign litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd41)); assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd20));
assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd41)); assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd20));
assign csrbank1_dfii_pi3_address1_r = interface1_bank_bus_dat_w[5:0]; assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0];
assign csrbank1_dfii_pi3_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd42)); assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd21));
assign csrbank1_dfii_pi3_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd42)); assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd21));
assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd43));
assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd43));
assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0]; assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd44)); assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd22));
assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd44)); assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd22));
assign csrbank1_dfii_pi3_wrdata3_r = interface1_bank_bus_dat_w[7:0]; assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi3_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd45)); assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd23));
assign csrbank1_dfii_pi3_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd45)); assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd23));
assign csrbank1_dfii_pi3_wrdata2_r = interface1_bank_bus_dat_w[7:0]; assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi3_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd46)); assign csrbank1_dfii_pi3_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd24));
assign csrbank1_dfii_pi3_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd46)); assign csrbank1_dfii_pi3_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd24));
assign csrbank1_dfii_pi3_wrdata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd47));
assign csrbank1_dfii_pi3_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd47));
assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd48));
assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd48));
assign csrbank1_dfii_pi3_rddata3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd49));
assign csrbank1_dfii_pi3_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd49));
assign csrbank1_dfii_pi3_rddata2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd50));
assign csrbank1_dfii_pi3_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd50));
assign csrbank1_dfii_pi3_rddata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd51));
assign csrbank1_dfii_pi3_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd51));
assign csrbank1_dfii_pi3_rddata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd52));
assign csrbank1_dfii_pi3_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd52));
assign csrbank1_dfii_control0_w = litedramcore_storage[3:0]; assign csrbank1_dfii_control0_w = litedramcore_storage[3:0];
assign csrbank1_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; assign csrbank1_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
assign csrbank1_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[13:8]; assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0];
assign csrbank1_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; assign csrbank1_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
assign csrbank1_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24]; assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
assign csrbank1_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16]; assign csrbank1_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0];
assign csrbank1_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8]; assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata_we;
assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0];
assign csrbank1_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24];
assign csrbank1_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16];
assign csrbank1_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8];
assign csrbank1_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0];
assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata0_we;
assign csrbank1_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; assign csrbank1_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
assign csrbank1_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[13:8]; assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0];
assign csrbank1_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; assign csrbank1_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
assign csrbank1_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24]; assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
assign csrbank1_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16]; assign csrbank1_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0];
assign csrbank1_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8]; assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata_we;
assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0];
assign csrbank1_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24];
assign csrbank1_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16];
assign csrbank1_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8];
assign csrbank1_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0];
assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata0_we;
assign csrbank1_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; assign csrbank1_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
assign csrbank1_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[13:8]; assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0];
assign csrbank1_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; assign csrbank1_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
assign csrbank1_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24]; assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
assign csrbank1_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16]; assign csrbank1_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0];
assign csrbank1_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8]; assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata_we;
assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0];
assign csrbank1_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24];
assign csrbank1_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16];
assign csrbank1_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8];
assign csrbank1_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0];
assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata0_we;
assign csrbank1_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; assign csrbank1_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
assign csrbank1_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[13:8]; assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0];
assign csrbank1_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; assign csrbank1_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
assign csrbank1_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24]; assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
assign csrbank1_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16]; assign csrbank1_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
assign csrbank1_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8]; assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata_we;
assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0];
assign csrbank1_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24];
assign csrbank1_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16];
assign csrbank1_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8];
assign csrbank1_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0];
assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata0_we;
assign adr = litedramcore_adr; assign adr = litedramcore_adr;
assign we = litedramcore_we; assign we = litedramcore_we;
assign dat_w = litedramcore_dat_w; assign dat_w = litedramcore_dat_w;
@ -12768,7 +12544,7 @@ always @(posedge sys_clk) begin
init_error_re <= csrbank0_init_error0_re; init_error_re <= csrbank0_init_error0_re;
interface1_bank_bus_dat_r <= 1'd0; interface1_bank_bus_dat_r <= 1'd0;
if (csrbank1_sel) begin if (csrbank1_sel) begin
case (interface1_bank_bus_adr[5:0]) case (interface1_bank_bus_adr[4:0])
1'd0: begin 1'd0: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w; interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w;
end end
@ -12779,154 +12555,70 @@ always @(posedge sys_clk) begin
interface1_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; interface1_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
end end
2'd3: begin 2'd3: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address1_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
end end
3'd4: begin 3'd4: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
end end
3'd5: begin 3'd5: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
end end
3'd6: begin 3'd6: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata3_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w;
end end
3'd7: begin 3'd7: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata2_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
end end
4'd8: begin 4'd8: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata1_w; interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
end end
4'd9: begin 4'd9: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
end end
4'd10: begin 4'd10: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata3_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
end end
4'd11: begin 4'd11: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata2_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
end end
4'd12: begin 4'd12: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata1_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w;
end end
4'd13: begin 4'd13: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata0_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
end end
4'd14: begin 4'd14: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w; interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
end end
4'd15: begin 4'd15: begin
interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
end end
5'd16: begin 5'd16: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address1_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
end end
5'd17: begin 5'd17: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
end end
5'd18: begin 5'd18: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w;
end end
5'd19: begin 5'd19: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata3_w;
end
5'd20: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata2_w;
end
5'd21: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata1_w;
end
5'd22: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
end
5'd23: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata3_w;
end
5'd24: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata2_w;
end
5'd25: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata1_w;
end
5'd26: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata0_w;
end
5'd27: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
end
5'd28: begin
interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
end
5'd29: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address1_w;
end
5'd30: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
end
5'd31: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
end
6'd32: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata3_w;
end
6'd33: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata2_w;
end
6'd34: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata1_w;
end
6'd35: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
end
6'd36: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata3_w;
end
6'd37: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata2_w;
end
6'd38: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata1_w;
end
6'd39: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata0_w;
end
6'd40: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
end end
6'd41: begin 5'd20: begin
interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
end end
6'd42: begin 5'd21: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address1_w;
end
6'd43: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
end end
6'd44: begin 5'd22: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
end end
6'd45: begin 5'd23: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata3_w;
end
6'd46: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata2_w;
end
6'd47: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata1_w;
end
6'd48: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
end end
6'd49: begin 5'd24: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata3_w; interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w;
end
6'd50: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata2_w;
end
6'd51: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata1_w;
end
6'd52: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata0_w;
end end
endcase endcase
end end
@ -12938,112 +12630,64 @@ always @(posedge sys_clk) begin
litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r; litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r;
end end
litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re; litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
if (csrbank1_dfii_pi0_address1_re) begin
litedramcore_phaseinjector0_address_storage[13:8] <= csrbank1_dfii_pi0_address1_r;
end
if (csrbank1_dfii_pi0_address0_re) begin if (csrbank1_dfii_pi0_address0_re) begin
litedramcore_phaseinjector0_address_storage[7:0] <= csrbank1_dfii_pi0_address0_r; litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r;
end end
litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re; litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
if (csrbank1_dfii_pi0_baddress0_re) begin if (csrbank1_dfii_pi0_baddress0_re) begin
litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r; litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r;
end end
litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re; litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
if (csrbank1_dfii_pi0_wrdata3_re) begin
litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank1_dfii_pi0_wrdata3_r;
end
if (csrbank1_dfii_pi0_wrdata2_re) begin
litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank1_dfii_pi0_wrdata2_r;
end
if (csrbank1_dfii_pi0_wrdata1_re) begin
litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank1_dfii_pi0_wrdata1_r;
end
if (csrbank1_dfii_pi0_wrdata0_re) begin if (csrbank1_dfii_pi0_wrdata0_re) begin
litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank1_dfii_pi0_wrdata0_r; litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r;
end end
litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re; litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
if (csrbank1_dfii_pi1_command0_re) begin if (csrbank1_dfii_pi1_command0_re) begin
litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r; litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r;
end end
litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re; litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
if (csrbank1_dfii_pi1_address1_re) begin
litedramcore_phaseinjector1_address_storage[13:8] <= csrbank1_dfii_pi1_address1_r;
end
if (csrbank1_dfii_pi1_address0_re) begin if (csrbank1_dfii_pi1_address0_re) begin
litedramcore_phaseinjector1_address_storage[7:0] <= csrbank1_dfii_pi1_address0_r; litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r;
end end
litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re; litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
if (csrbank1_dfii_pi1_baddress0_re) begin if (csrbank1_dfii_pi1_baddress0_re) begin
litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r; litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r;
end end
litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re; litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
if (csrbank1_dfii_pi1_wrdata3_re) begin
litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank1_dfii_pi1_wrdata3_r;
end
if (csrbank1_dfii_pi1_wrdata2_re) begin
litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank1_dfii_pi1_wrdata2_r;
end
if (csrbank1_dfii_pi1_wrdata1_re) begin
litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank1_dfii_pi1_wrdata1_r;
end
if (csrbank1_dfii_pi1_wrdata0_re) begin if (csrbank1_dfii_pi1_wrdata0_re) begin
litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank1_dfii_pi1_wrdata0_r; litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r;
end end
litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re; litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
if (csrbank1_dfii_pi2_command0_re) begin if (csrbank1_dfii_pi2_command0_re) begin
litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r; litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r;
end end
litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re; litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
if (csrbank1_dfii_pi2_address1_re) begin
litedramcore_phaseinjector2_address_storage[13:8] <= csrbank1_dfii_pi2_address1_r;
end
if (csrbank1_dfii_pi2_address0_re) begin if (csrbank1_dfii_pi2_address0_re) begin
litedramcore_phaseinjector2_address_storage[7:0] <= csrbank1_dfii_pi2_address0_r; litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r;
end end
litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re; litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
if (csrbank1_dfii_pi2_baddress0_re) begin if (csrbank1_dfii_pi2_baddress0_re) begin
litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r; litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r;
end end
litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re; litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
if (csrbank1_dfii_pi2_wrdata3_re) begin
litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank1_dfii_pi2_wrdata3_r;
end
if (csrbank1_dfii_pi2_wrdata2_re) begin
litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank1_dfii_pi2_wrdata2_r;
end
if (csrbank1_dfii_pi2_wrdata1_re) begin
litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank1_dfii_pi2_wrdata1_r;
end
if (csrbank1_dfii_pi2_wrdata0_re) begin if (csrbank1_dfii_pi2_wrdata0_re) begin
litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank1_dfii_pi2_wrdata0_r; litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r;
end end
litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re; litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
if (csrbank1_dfii_pi3_command0_re) begin if (csrbank1_dfii_pi3_command0_re) begin
litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r; litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r;
end end
litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re; litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
if (csrbank1_dfii_pi3_address1_re) begin
litedramcore_phaseinjector3_address_storage[13:8] <= csrbank1_dfii_pi3_address1_r;
end
if (csrbank1_dfii_pi3_address0_re) begin if (csrbank1_dfii_pi3_address0_re) begin
litedramcore_phaseinjector3_address_storage[7:0] <= csrbank1_dfii_pi3_address0_r; litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r;
end end
litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re; litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
if (csrbank1_dfii_pi3_baddress0_re) begin if (csrbank1_dfii_pi3_baddress0_re) begin
litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r; litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r;
end end
litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re; litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
if (csrbank1_dfii_pi3_wrdata3_re) begin
litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank1_dfii_pi3_wrdata3_r;
end
if (csrbank1_dfii_pi3_wrdata2_re) begin
litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank1_dfii_pi3_wrdata2_r;
end
if (csrbank1_dfii_pi3_wrdata1_re) begin
litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank1_dfii_pi3_wrdata1_r;
end
if (csrbank1_dfii_pi3_wrdata0_re) begin if (csrbank1_dfii_pi3_wrdata0_re) begin
litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank1_dfii_pi3_wrdata0_r; litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r;
end end
litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re; litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
if (sys_rst) begin if (sys_rst) begin

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