Added support for Xilinx VCU 118 board, without litedram

1 month ago · 59f1b7f698
parent 7619df6b78
commit 59f1b7f698
5 changed files with 644 additions and 42212 deletions
--- a/fpga/firmware.hex
+++ b/fpga/firmware.hex
--- a/fpga/top-xilinx-vcu-118.vhdl
+++ b/fpga/top-xilinx-vcu-118.vhdl
@ -0,0 +1,227 @@
+-- VCU118 Debug Top-Level - Add heartbeat LED and basic diagnostics
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY unisim;
+USE unisim.vcomponents.ALL;
+
+LIBRARY work;
+USE work.wishbone_types.ALL;
+
+ENTITY toplevel IS
+    GENERIC (
+        MEMORY_SIZE : INTEGER := 16384; -- This can go up a lot more
+        DRAM_SIZE : INTEGER := 268435456;
+        RAM_INIT_FILE : STRING := "firmware.hex";
+        RESET_LOW : BOOLEAN := false; -- VCU118 reset button is active-high
+        CLK_INPUT : POSITIVE := 125000000; -- Match physical clock
+        CLK_FREQUENCY : POSITIVE := 125000000; -- Same as input (no PLL)
+        HAS_FPU : BOOLEAN := true;
+        HAS_BTC : BOOLEAN := true;
+        ICACHE_NUM_LINES : NATURAL := 64;
+        LOG_LENGTH : NATURAL := 512;
+        DISABLE_FLATTEN_CORE : BOOLEAN := false;
+        UART_IS_16550 : BOOLEAN := true;
+        NO_BRAM : BOOLEAN := false;
+        USE_LITEDRAM : BOOLEAN := false;
+        HAS_SPI_FLASH: BOOLEAN := false
+    );
+    PORT (
+        -- VCU118 differential clock input
+        ext_clk_p : IN STD_ULOGIC;
+        ext_clk_n : IN STD_ULOGIC;
+
+        -- VCU118 reset button
+        ext_rst : IN STD_ULOGIC;
+
+        -- UART0 signals
+        uart0_txd : OUT STD_ULOGIC;
+        uart0_rxd : IN STD_ULOGIC;
+
+        -- Debug LEDs (use some GPIO LEDs from VCU118)
+        debug_led0 : OUT STD_ULOGIC; -- Heartbeat - clock working
+        debug_led1 : OUT STD_ULOGIC; -- Reset state
+        debug_led2 : OUT STD_ULOGIC; -- SoC running
+        debug_led3 : OUT STD_ULOGIC; -- UART activity
+        debug_led4 : OUT STD_ULOGIC; -- Init done
+        debug_led5 : OUT STD_ULOGIC -- Init error
+
+    );
+END ENTITY toplevel;
+
+ARCHITECTURE behaviour OF toplevel IS
+
+    -- Reset signals
+    SIGNAL soc_rst : STD_ULOGIC;
+    SIGNAL pll_rst : STD_ULOGIC;
+
+    -- Internal clock signals
+    SIGNAL system_clk : STD_ULOGIC;
+    SIGNAL system_clk_locked : STD_ULOGIC;
+
+    -- Single-ended clock from differential input
+    SIGNAL ext_clk_single : STD_ULOGIC;
+
+    -- Debug signals
+    SIGNAL heartbeat_counter : unsigned(27 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL uart_activity : STD_ULOGIC := '0';
+    SIGNAL uart_activity_counter : unsigned(23 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL soc_run_out : STD_ULOGIC;
+     SIGNAL soc_run_outs : STD_ULOGIC_VECTOR(0 DOWNTO 0);  -- Add run_outs signal for NCPUS=1
+    SIGNAL init_done : STD_ULOGIC;
+    SIGNAL init_error : STD_ULOGIC;
+    -- Dummy DRAM wishbone interface (not used when USE_LITEDRAM = false)
+    SIGNAL wb_dram_in : wishbone_master_out;
+    SIGNAL wb_dram_out : wishbone_slave_out;
+    SIGNAL wb_ext_io_in : wb_io_master_out;
+    SIGNAL wb_ext_io_out : wb_io_slave_out;
+    SIGNAL wb_ext_is_dram_csr : STD_ULOGIC;
+    SIGNAL wb_ext_is_dram_init : STD_ULOGIC;
+    function get_bram_size return natural is
+    begin
+        if USE_LITEDRAM and NO_BRAM then
+            return 0;
+        else
+            return MEMORY_SIZE;
+        end if;
+    end function;
+    function get_payload_size return natural is
+    begin
+        if USE_LITEDRAM and NO_BRAM then
+            return MEMORY_SIZE;
+        else
+            return 0;
+        end if;
+    end function;
+    
+    constant BRAM_SIZE    : natural := get_bram_size;
+    constant PAYLOAD_SIZE : natural := get_payload_size;
+BEGIN
+    -- Convert differential clock to single-ended (MUST come before BUFG)
+    clk_ibufgds : IBUFGDS
+    PORT MAP(
+        I => ext_clk_p,
+        IB => ext_clk_n,
+        O => ext_clk_single
+    );
+    -- Clock buffering (no PLL for 125MHz passthrough)
+    clk_bufg : BUFG
+    PORT MAP(
+        I => ext_clk_single,
+        O => system_clk
+    );
+
+    -- Since we're not using a PLL, clock is always "locked"
+    system_clk_locked <= '1';
+
+    -- Use the soc_reset entity for proper reset sequencing
+    reset_controller : ENTITY work.soc_reset
+        GENERIC MAP(
+            RESET_LOW => RESET_LOW,
+            PLL_RESET_BITS => 18 -- Adjust as needed
+        )
+        PORT MAP(
+            ext_clk => ext_clk_single,
+            pll_clk => system_clk,
+            pll_locked_in => system_clk_locked,
+            ext_rst_in => ext_rst,
+            pll_rst_out => pll_rst,
+            rst_out => soc_rst
+        );
+    -- Heartbeat counter for LED - ~0.93Hz at 125MHz (2^27 / 125MHz)
+    heartbeat_proc : PROCESS (system_clk)
+    BEGIN
+        IF rising_edge(system_clk) THEN
+            IF soc_rst = '1' THEN
+                heartbeat_counter <= (OTHERS => '0');
+            ELSE
+                heartbeat_counter <= heartbeat_counter + 1;
+            END IF;
+        END IF;
+    END PROCESS;
+
+    -- UART activity detector with timeout
+    uart_activity_proc : PROCESS (system_clk)
+    BEGIN
+        IF rising_edge(system_clk) THEN
+            IF soc_rst = '1' THEN
+                uart_activity <= '0';
+                uart_activity_counter <= (OTHERS => '0');
+            ELSE
+                 -- Detect any UART transmit activity (start bit = '0')
+                IF uart0_txd = '0' THEN
+                    uart_activity <= '1';
+                    uart_activity_counter <= (OTHERS => '1');
+                ELSIF uart_activity_counter /= 0 THEN
+                    uart_activity_counter <= uart_activity_counter - 1;
+                ELSE
+                    uart_activity <= '0';
+                END IF;
+            END IF;
+        END IF;
+    END PROCESS;
+
+    -- Debug LED assignments
+    debug_led0 <= heartbeat_counter(27); -- Heartbeat - proves clock works
+    debug_led1 <= NOT soc_rst; -- ON when system running (not in reset)
+    debug_led2 <= soc_run_outs(0); -- SoC run status
+    debug_led3 <= uart_activity; -- UART activity indicator
+    debug_led4 <= init_done; -- Always '1' for no-DRAM config
+    debug_led5 <= init_error; -- Always '0' for no-DRAM config
+
+    -- Conditional DDR4 Generation
+    no_litedram_gen : IF NOT USE_LITEDRAM GENERATE
+
+        init_done <= '1';
+        init_error <= '0';
+        wb_dram_out.dat <= (OTHERS => '0');
+        wb_dram_out.ack <= '0';
+        wb_dram_out.stall <= '0';
+        wb_ext_io_out.dat <= (OTHERS => '0');
+        wb_ext_io_out.ack <= '0';
+        wb_ext_io_out.stall <= '0';
+        wb_ext_is_dram_csr <= '0';
+        wb_ext_is_dram_init <= '0';
+
+    END GENERATE no_litedram_gen;
+
+    -- Main SoC
+    soc0 : ENTITY work.soc
+        GENERIC MAP(
+            MEMORY_SIZE => BRAM_SIZE,
+            RAM_INIT_FILE => RAM_INIT_FILE,
+            HAS_SPI_FLASH => false,
+            SIM => false,
+            NCPUS => 1,
+            CLK_FREQ => CLK_FREQUENCY,
+            HAS_FPU => HAS_FPU,
+            HAS_BTC => HAS_BTC,
+            HAS_DRAM => USE_LITEDRAM,
+            DRAM_SIZE => DRAM_SIZE,
+            DRAM_INIT_SIZE => 0, -- No DRAM init when not using LiteDRAM
+            ICACHE_NUM_LINES => ICACHE_NUM_LINES,
+            LOG_LENGTH => LOG_LENGTH,
+            DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
+            UART0_IS_16550 => UART_IS_16550,
+            HAS_UART1 => false
+            
+        )
+        PORT MAP(
+            system_clk => system_clk,
+            rst => soc_rst,
+            uart0_txd => uart0_txd,
+            uart0_rxd => uart0_rxd,
+            -- DRAM wishbone (not used but needs to be connected)
+            wb_dram_in => wb_dram_in,
+            wb_dram_out => wb_dram_out,
+            wb_ext_io_in => wb_ext_io_in,
+            wb_ext_io_out => wb_ext_io_out,
+            wb_ext_is_dram_csr => wb_ext_is_dram_csr,
+            wb_ext_is_dram_init => wb_ext_is_dram_init,
+            -- Run status output
+            run_outs => soc_run_outs
+        );
+
+END ARCHITECTURE behaviour;
--- a/fpga/xilinx-vcu-118.xdc
+++ b/fpga/xilinx-vcu-118.xdc
@ -0,0 +1,180 @@
+# VCU118 Constraints for Debug Top-level
+
+# ========================================
+# SYSTEM CLOCK - 300MHz Differential
+# ========================================
+set_property -dict {PACKAGE_PIN AY24 IOSTANDARD LVDS} [get_ports ext_clk_p]
+set_property -dict {PACKAGE_PIN AY23 IOSTANDARD LVDS} [get_ports ext_clk_n]
+
+
+# Clock constraint - 125MHz input (8.000ns period)  
+create_clock -period 8.000 -name ext_clk [get_ports ext_clk_p]
+
+# ========================================
+# RESET - CPU Reset Button (active-high)
+# ========================================
+set_property PACKAGE_PIN L19 [get_ports "ext_rst"]
+set_property IOSTANDARD LVCMOS12 [get_ports "ext_rst"]
+
+# ========================================  
+# UART - USB-to-UART Bridge
+# ========================================
+set_property PACKAGE_PIN AW25 [get_ports "uart0_rxd"]
+set_property IOSTANDARD LVCMOS18 [get_ports "uart0_rxd"]
+
+set_property PACKAGE_PIN BB21 [get_ports "uart0_txd"]
+set_property IOSTANDARD LVCMOS18 [get_ports "uart0_txd"]
+
+# ========================================
+# DEBUG LEDs - Use GPIO LEDs from VCU118
+# From Table 3-29: GPIO_LED connections
+# ========================================
+set_property PACKAGE_PIN AT32 [get_ports "debug_led0"]
+set_property IOSTANDARD LVCMOS12 [get_ports "debug_led0"]
+
+set_property PACKAGE_PIN AV34 [get_ports "debug_led1"] 
+set_property IOSTANDARD LVCMOS12 [get_ports "debug_led1"]
+
+set_property PACKAGE_PIN AY30 [get_ports "debug_led2"]
+set_property IOSTANDARD LVCMOS12 [get_ports "debug_led2"]
+
+set_property PACKAGE_PIN BB32 [get_ports "debug_led3"]
+set_property IOSTANDARD LVCMOS12 [get_ports "debug_led3"]
+
+set_property PACKAGE_PIN BF32 [get_ports "debug_led4"]
+set_property IOSTANDARD LVCMOS12 [get_ports "debug_led4"]
+
+set_property PACKAGE_PIN AU37 [get_ports "debug_led5"]
+set_property IOSTANDARD LVCMOS12 [get_ports "debug_led5"]
+
+
+# ========================================
+# DDR4 C1 Interface - 40-bit (2.5 chips: U60, U61, U62, half of U63)
+# ========================================
+
+# DDR4 Address/Command Signals
+set_property PACKAGE_PIN D14 [get_ports "ddram_a[0]"]
+set_property PACKAGE_PIN B15 [get_ports "ddram_a[1]"]
+set_property PACKAGE_PIN B16 [get_ports "ddram_a[2]"]
+set_property PACKAGE_PIN C14 [get_ports "ddram_a[3]"]
+set_property PACKAGE_PIN C15 [get_ports "ddram_a[4]"]
+set_property PACKAGE_PIN A13 [get_ports "ddram_a[5]"]
+set_property PACKAGE_PIN A14 [get_ports "ddram_a[6]"]
+set_property PACKAGE_PIN A15 [get_ports "ddram_a[7]"]
+set_property PACKAGE_PIN A16 [get_ports "ddram_a[8]"]
+set_property PACKAGE_PIN B12 [get_ports "ddram_a[9]"]
+set_property PACKAGE_PIN C12 [get_ports "ddram_a[10]"]
+set_property PACKAGE_PIN B13 [get_ports "ddram_a[11]"]
+set_property PACKAGE_PIN C13 [get_ports "ddram_a[12]"]
+set_property PACKAGE_PIN D15 [get_ports "ddram_a[13]"]
+
+set_property PACKAGE_PIN G15 [get_ports "ddram_ba[0]"]
+set_property PACKAGE_PIN G13 [get_ports "ddram_ba[1]"]
+set_property PACKAGE_PIN H13 [get_ports "ddram_bg"]
+
+# DDR4 Command Signals - these are shared with address lines in DDR4
+ # Shared with A16
+set_property PACKAGE_PIN F15 [get_ports "ddram_ras_n"]
+# Shared with A15    
+set_property PACKAGE_PIN H15 [get_ports "ddram_cas_n"]   
+# Shared with A14
+set_property PACKAGE_PIN H14 [get_ports "ddram_we_n"]    
+set_property PACKAGE_PIN F13 [get_ports "ddram_cs_n"]
+set_property PACKAGE_PIN E13 [get_ports "ddram_act_n"]
+
+# DDR4 Clock - Single-ended, not differential
+set_property PACKAGE_PIN F14 [get_ports "ddram_clk_p"]
+set_property PACKAGE_PIN E14 [get_ports "ddram_clk_n"]
+
+# DDR4 Control
+set_property PACKAGE_PIN A10 [get_ports "ddram_cke"]
+set_property PACKAGE_PIN C8  [get_ports "ddram_odt"]
+set_property PACKAGE_PIN N20 [get_ports "ddram_reset_n"]
+
+# DDR4 Data - DQ[39:0] (First 2.5 chips: U60, U61, U62, half of U63)
+# Device U60 - DQ[15:0]
+set_property PACKAGE_PIN F11 [get_ports "ddram_dq[0]"]
+set_property PACKAGE_PIN E11 [get_ports "ddram_dq[1]"]
+set_property PACKAGE_PIN F10 [get_ports "ddram_dq[2]"]
+set_property PACKAGE_PIN F9  [get_ports "ddram_dq[3]"]
+set_property PACKAGE_PIN H12 [get_ports "ddram_dq[4]"]
+set_property PACKAGE_PIN G12 [get_ports "ddram_dq[5]"]
+set_property PACKAGE_PIN E9  [get_ports "ddram_dq[6]"]
+set_property PACKAGE_PIN D9  [get_ports "ddram_dq[7]"]
+set_property PACKAGE_PIN R19 [get_ports "ddram_dq[8]"]
+set_property PACKAGE_PIN P19 [get_ports "ddram_dq[9]"]
+set_property PACKAGE_PIN M18 [get_ports "ddram_dq[10]"]
+set_property PACKAGE_PIN M17 [get_ports "ddram_dq[11]"]
+set_property PACKAGE_PIN N19 [get_ports "ddram_dq[12]"]
+set_property PACKAGE_PIN N18 [get_ports "ddram_dq[13]"]
+set_property PACKAGE_PIN N17 [get_ports "ddram_dq[14]"]
+set_property PACKAGE_PIN M16 [get_ports "ddram_dq[15]"]
+
+# Device U61 - DQ[31:16]
+set_property PACKAGE_PIN L16 [get_ports "ddram_dq[16]"]
+set_property PACKAGE_PIN K16 [get_ports "ddram_dq[17]"]
+set_property PACKAGE_PIN L18 [get_ports "ddram_dq[18]"]
+set_property PACKAGE_PIN K18 [get_ports "ddram_dq[19]"]
+set_property PACKAGE_PIN J17 [get_ports "ddram_dq[20]"]
+set_property PACKAGE_PIN H17 [get_ports "ddram_dq[21]"]
+set_property PACKAGE_PIN H19 [get_ports "ddram_dq[22]"]
+set_property PACKAGE_PIN H18 [get_ports "ddram_dq[23]"]
+set_property PACKAGE_PIN F19 [get_ports "ddram_dq[24]"]
+set_property PACKAGE_PIN F18 [get_ports "ddram_dq[25]"]
+set_property PACKAGE_PIN E19 [get_ports "ddram_dq[26]"]
+set_property PACKAGE_PIN E18 [get_ports "ddram_dq[27]"]
+set_property PACKAGE_PIN G20 [get_ports "ddram_dq[28]"]
+set_property PACKAGE_PIN F20 [get_ports "ddram_dq[29]"]
+set_property PACKAGE_PIN E17 [get_ports "ddram_dq[30]"]
+set_property PACKAGE_PIN D16 [get_ports "ddram_dq[31]"]
+
+# Device U62 - DQ[39:32] (first 8 bits only)
+set_property PACKAGE_PIN D17 [get_ports "ddram_dq[32]"]
+set_property PACKAGE_PIN C17 [get_ports "ddram_dq[33]"]
+set_property PACKAGE_PIN C19 [get_ports "ddram_dq[34]"]
+set_property PACKAGE_PIN C18 [get_ports "ddram_dq[35]"]
+set_property PACKAGE_PIN D20 [get_ports "ddram_dq[36]"]
+set_property PACKAGE_PIN D19 [get_ports "ddram_dq[37]"]
+set_property PACKAGE_PIN C20 [get_ports "ddram_dq[38]"]
+set_property PACKAGE_PIN B20 [get_ports "ddram_dq[39]"]
+
+# DDR4 Data Strobes - DQS[4:0] (5 pairs for 2.5 chips)
+set_property PACKAGE_PIN D11 [get_ports "ddram_dqs_p[0]"]
+set_property PACKAGE_PIN D10 [get_ports "ddram_dqs_n[0]"]
+set_property PACKAGE_PIN P17 [get_ports "ddram_dqs_p[1]"]
+set_property PACKAGE_PIN P16 [get_ports "ddram_dqs_n[1]"]
+set_property PACKAGE_PIN K19 [get_ports "ddram_dqs_p[2]"]
+set_property PACKAGE_PIN J19 [get_ports "ddram_dqs_n[2]"]
+set_property PACKAGE_PIN F16 [get_ports "ddram_dqs_p[3]"]
+set_property PACKAGE_PIN E16 [get_ports "ddram_dqs_n[3]"]
+set_property PACKAGE_PIN A19 [get_ports "ddram_dqs_p[4]"]
+set_property PACKAGE_PIN A18 [get_ports "ddram_dqs_n[4]"]
+
+# DDR4 Data Mask - DM[4:0] (5 signals for 2.5 chips)
+set_property PACKAGE_PIN G11 [get_ports "ddram_dm[0]"]
+set_property PACKAGE_PIN R18 [get_ports "ddram_dm[1]"]
+set_property PACKAGE_PIN K17 [get_ports "ddram_dm[2]"]
+set_property PACKAGE_PIN G18 [get_ports "ddram_dm[3]"]
+set_property PACKAGE_PIN B18 [get_ports "ddram_dm[4]"]
+
+# IO Standards for DDR4
+set_property IOSTANDARD SSTL12_DCI [get_ports "ddram_a[*]"]
+set_property IOSTANDARD SSTL12_DCI [get_ports "ddram_ba[*]"]
+set_property IOSTANDARD SSTL12_DCI [get_ports "ddram_bg"]
+set_property IOSTANDARD SSTL12_DCI [get_ports "ddram_ras_n"]
+set_property IOSTANDARD SSTL12_DCI [get_ports "ddram_cas_n"]
+set_property IOSTANDARD SSTL12_DCI [get_ports "ddram_we_n"]
+set_property IOSTANDARD SSTL12_DCI [get_ports "ddram_cs_n"]
+set_property IOSTANDARD SSTL12_DCI [get_ports "ddram_act_n"]
+set_property IOSTANDARD SSTL12_DCI [get_ports "ddram_cke"]
+set_property IOSTANDARD SSTL12_DCI [get_ports "ddram_odt"]
+set_property IOSTANDARD LVCMOS12   [get_ports "ddram_reset_n"]
+
+# Clock signals use single-ended SSTL12_DCI (not differential)
+set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "ddram_clk_p"]
+set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "ddram_clk_n"]
+
+set_property IOSTANDARD POD12_DCI [get_ports "ddram_dq[*]"]
+set_property IOSTANDARD DIFF_POD12_DCI [get_ports "ddram_dqs_p[*]"]
+set_property IOSTANDARD DIFF_POD12_DCI [get_ports "ddram_dqs_n[*]"]
+set_property IOSTANDARD POD12_DCI [get_ports "ddram_dm[*]"]
--- a/hello_world/hello_world.elf
+++ b/hello_world/hello_world.elf
--- a/microwatt.core
+++ b/microwatt.core
@ -126,6 +126,11 @@ filesets:
      - fpga/cmod_a7-35.xdc : {file_type : xdc}
      - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
      - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
+  
+  xilinx-vcu-118:
+    files:
+      - fpga/xilinx-vcu-118.xdc : {file_type : xdc}
+      - fpga/top-xilinx-vcu-118.vhdl : {file_type : vhdlSource-2008}

  litedram:
      depend : [":microwatt:litedram"]
@ -440,6 +445,27 @@ targets:
      vivado: {part : xc7a35tcpg236-1}
    toplevel : toplevel

+  xilinx-vcu-118-no-dram:
+    default_tool: vivado
+    filesets: [core, xilinx-vcu-118, soc, fpga, uart16550, xilinx_specific, debug_xilinx]
+    parameters:
+      - memory_size
+      - ram_init_file=firmware.hex
+      - clk_input=125000000
+      - clk_frequency=125000000
+      - disable_flatten_core
+      - log_length=2048
+      - uart_is_16550
+      - has_uart1
+      - has_fpu
+      - has_btc
+      - use_litedram=false
+
+    generate: [git_hash]
+    tools:
+      vivado: {part : xcvu9p-flga2104-2-i}
+    toplevel : toplevel
+
  synth:
    filesets: [core, soc, xilinx_specific]
    generate: [git_hash]