Merge pull request #106 from paulusmack/master

wishbone_debug_master: Improve timing
pull/108/head
Anton Blanchard 5 years ago committed by GitHub
commit 640af89e72
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@ -90,9 +90,8 @@ begin
elsif dmi_addr = DBG_WB_CTRL then elsif dmi_addr = DBG_WB_CTRL then
reg_ctrl <= dmi_din(10 downto 0); reg_ctrl <= dmi_din(10 downto 0);
end if; end if;
end if; elsif state = WB_CYCLE and (wb_in.ack and reg_ctrl(8))= '1' then
-- Address register auto-increment -- Address register auto-increment
if state = WB_CYCLE and (wb_in.ack and reg_ctrl(8))= '1' then
reg_addr <= std_ulogic_vector(unsigned(reg_addr) + reg_addr <= std_ulogic_vector(unsigned(reg_addr) +
decode_autoinc(reg_ctrl(10 downto 9))); decode_autoinc(reg_ctrl(10 downto 9)));
end if; end if;

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