Hook up JTAG to ASIC top level

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
caravel-mpw7-20220822
Anton Blanchard 3 years ago
parent 5e025b5b15
commit 6745d9dd5f

@ -24,6 +24,7 @@ entity toplevel is
LOG_LENGTH : natural := 0; LOG_LENGTH : natural := 0;
UART_IS_16550 : boolean := true; UART_IS_16550 : boolean := true;
HAS_UART1 : boolean := false; HAS_UART1 : boolean := false;
HAS_JTAG : boolean := true;
ICACHE_NUM_LINES : natural := 4; ICACHE_NUM_LINES : natural := 4;
ICACHE_NUM_WAYS : natural := 1; ICACHE_NUM_WAYS : natural := 1;
ICACHE_TLB_SIZE : natural := 4; ICACHE_TLB_SIZE : natural := 4;
@ -54,6 +55,13 @@ entity toplevel is
gpio_out : out std_ulogic_vector(NGPIO - 1 downto 0); gpio_out : out std_ulogic_vector(NGPIO - 1 downto 0);
gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0); gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0);


-- JTAG signals:
jtag_tck : in std_ulogic;
jtag_tdi : in std_ulogic;
jtag_tms : in std_ulogic;
jtag_trst : in std_ulogic;
jtag_tdo : out std_ulogic;

-- Add an I/O pin to select fetching from flash on reset -- Add an I/O pin to select fetching from flash on reset
alt_reset : in std_ulogic alt_reset : in std_ulogic
); );
@ -91,6 +99,7 @@ begin
HAS_UART1 => HAS_UART1, HAS_UART1 => HAS_UART1,
HAS_GPIO => HAS_GPIO, HAS_GPIO => HAS_GPIO,
NGPIO => NGPIO, NGPIO => NGPIO,
HAS_JTAG => HAS_JTAG,
ICACHE_NUM_LINES => ICACHE_NUM_LINES, ICACHE_NUM_LINES => ICACHE_NUM_LINES,
ICACHE_NUM_WAYS => ICACHE_NUM_WAYS, ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
ICACHE_TLB_SIZE => ICACHE_TLB_SIZE, ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
@ -120,6 +129,13 @@ begin
gpio_out => gpio_out, gpio_out => gpio_out,
gpio_dir => gpio_dir, gpio_dir => gpio_dir,


-- JTAG signals
jtag_tck => jtag_tck,
jtag_tdi => jtag_tdi,
jtag_tms => jtag_tms,
jtag_trst => jtag_trst,
jtag_tdo => jtag_tdo,

-- Reset PC to flash offset 0 (ie 0xf000000) -- Reset PC to flash offset 0 (ie 0xf000000)
alt_reset => alt_reset alt_reset => alt_reset
); );

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