litedram: Test bench
The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>pull/190/head
Benjamin Herrenschmidt
4 years ago
parent
a3857aac94
commit
6828e93113
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity dram_tb is
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generic (
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DRAM_INIT_FILE : string := "";
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DRAM_INIT_SIZE : natural := 0
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);
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end dram_tb;
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architecture behave of dram_tb is
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signal clk, rst: std_logic;
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signal clk_in, soc_rst : std_ulogic;
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-- testbench signals
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constant clk_period : time := 10 ns;
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-- Sim DRAM
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signal wb_in : wishbone_master_out;
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signal wb_out : wishbone_slave_out;
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signal wb_ctrl_in : wb_io_master_out;
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subtype addr_t is std_ulogic_vector(wb_in.adr'left downto 0);
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subtype data_t is std_ulogic_vector(wb_in.dat'left downto 0);
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subtype sel_t is std_ulogic_vector(wb_in.sel'left downto 0);
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-- Counter for acks
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signal acks : integer := 0;
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signal reset_acks : std_ulogic;
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-- Read data fifo
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signal rd_ready : std_ulogic := '0';
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signal rd_valid : std_ulogic;
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signal rd_data : data_t;
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begin
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dram: entity work.litedram_wrapper
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generic map(
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DRAM_ABITS => 24,
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DRAM_ALINES => 1,
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PAYLOAD_FILE => DRAM_INIT_FILE,
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PAYLOAD_SIZE => DRAM_INIT_SIZE
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)
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port map(
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clk_in => clk_in,
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rst => rst,
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system_clk => clk,
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system_reset => soc_rst,
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core_alt_reset => open,
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pll_locked => open,
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wb_in => wb_in,
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wb_out => wb_out,
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wb_ctrl_in => wb_ctrl_in,
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wb_ctrl_out => open,
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wb_ctrl_is_csr => '0',
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wb_ctrl_is_init => '0',
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serial_tx => open,
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serial_rx => '1',
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init_done => open,
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init_error => open,
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ddram_a => open,
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ddram_ba => open,
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ddram_ras_n => open,
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ddram_cas_n => open,
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ddram_we_n => open,
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ddram_cs_n => open,
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ddram_dm => open,
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ddram_dq => open,
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ddram_dqs_p => open,
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ddram_dqs_n => open,
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ddram_clk_p => open,
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ddram_clk_n => open,
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ddram_cke => open,
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ddram_odt => open,
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ddram_reset_n => open
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);
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clk_process: process
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begin
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clk_in <= '0';
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wait for clk_period/2;
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clk_in <= '1';
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wait for clk_period/2;
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end process;
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rst_process: process
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begin
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rst <= '1';
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wait for 10*clk_period;
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rst <= '0';
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wait;
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end process;
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wb_ctrl_in.cyc <= '0';
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wb_ctrl_in.stb <= '0';
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-- Read data receive queue
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data_queue: entity work.sync_fifo
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generic map (
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DEPTH => 16,
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WIDTH => rd_data'length
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)
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port map (
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clk => clk,
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reset => soc_rst or reset_acks,
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rd_ready => rd_ready,
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rd_valid => rd_valid,
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rd_data => rd_data,
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wr_ready => open,
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wr_valid => wb_out.ack,
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wr_data => wb_out.dat
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);
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recv_acks: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' or reset_acks = '1' then
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acks <= 0;
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elsif wb_out.ack = '1' then
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acks <= acks + 1;
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-- report "WB ACK ! DATA=" & to_hstring(wb_out.dat);
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end if;
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end if;
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end process;
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sim: process
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procedure wb_write(addr: addr_t; data: data_t; sel: sel_t) is
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begin
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wb_in.adr <= addr;
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wb_in.sel <= sel;
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wb_in.dat <= data;
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wb_in.we <= '1';
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wb_in.stb <= '1';
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wb_in.cyc <= '1';
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loop
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wait until rising_edge(clk);
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if wb_out.stall = '0' then
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wb_in.stb <= '0';
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exit;
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end if;
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end loop;
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end procedure;
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procedure wb_read(addr: addr_t) is
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begin
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wb_in.adr <= addr;
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wb_in.sel <= x"ff";
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wb_in.we <= '0';
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wb_in.stb <= '1';
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wb_in.cyc <= '1';
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loop
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wait until rising_edge(clk);
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if wb_out.stall = '0' then
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wb_in.stb <= '0';
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exit;
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end if;
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end loop;
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end procedure;
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procedure wait_acks(count: integer) is
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begin
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wait until acks = count;
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wait until rising_edge(clk);
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end procedure;
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procedure clr_acks is
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begin
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reset_acks <= '1';
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wait until rising_edge(clk);
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reset_acks <= '0';
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end procedure;
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procedure read_data(data: out data_t) is
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begin
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assert rd_valid = '1' report "No data to read" severity failure;
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rd_ready <= '1';
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wait until rising_edge(clk);
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rd_ready <= '0';
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data := rd_data;
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end procedure;
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function add_off(a: addr_t; off: integer) return addr_t is
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begin
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return addr_t(unsigned(a) + off);
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end function;
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function make_pattern(num : integer) return data_t is
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variable r : data_t;
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variable t,b : integer;
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begin
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for i in 0 to (data_t'length/8)-1 loop
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t := (i+1)*8-1;
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b := i*8;
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r(t downto b) := std_ulogic_vector(to_unsigned(num+1, 8));
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end loop;
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return r;
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end function;
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procedure check_data(p: data_t) is
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variable d : data_t;
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begin
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read_data(d);
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assert d = p report "bad data, want " & to_hstring(p) &
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" got " & to_hstring(d) severity failure;
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end procedure;
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variable a : addr_t := (others => '0');
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variable d : data_t := (others => '0');
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variable d1 : data_t := (others => '0');
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begin
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reset_acks <= '0';
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rst <= '1';
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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rst <= '0';
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wait until rising_edge(clk_in);
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wait until soc_rst = '0';
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wait until rising_edge(clk);
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report "Simple write miss...";
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clr_acks;
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wb_write(a, x"0123456789abcdef", x"ff");
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wait_acks(1);
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report "Simple read miss...";
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clr_acks;
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wb_read(a);
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wait_acks(1);
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read_data(d);
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assert d = x"0123456789abcdef" report "bad data" severity failure;
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report "Simple read hit...";
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clr_acks;
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wb_read(a);
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wait_acks(1);
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read_data(d);
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assert d = x"0123456789abcdef" report "bad data" severity failure;
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report "Back to back 4 stores 4 reads on hit...";
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clr_acks;
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for i in 0 to 3 loop
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wb_write(add_off(a, i*8), make_pattern(i), x"ff");
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end loop;
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for i in 0 to 3 loop
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wb_read(add_off(a, i*8));
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end loop;
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wait_acks(8);
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for i in 0 to 7 loop
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if i < 4 then
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read_data(d);
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else
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check_data(make_pattern(i-4));
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end if;
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end loop;
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report "Back to back 4 stores 4 reads on miss...";
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a(10) := '1';
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clr_acks;
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for i in 0 to 3 loop
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wb_write(add_off(a, i*8), make_pattern(i), x"ff");
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end loop;
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for i in 0 to 3 loop
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wb_read(add_off(a, i*8));
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end loop;
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wait_acks(8);
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for i in 0 to 7 loop
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if i < 4 then
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read_data(d);
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else
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check_data(make_pattern(i-4));
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end if;
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end loop;
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report "Back to back interleaved 4 stores 4 reads on hit...";
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a(10) := '1';
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clr_acks;
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for i in 0 to 3 loop
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wb_write(add_off(a, i*8), make_pattern(i), x"ff");
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wb_read(add_off(a, i*8));
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end loop;
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wait_acks(8);
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for i in 0 to 3 loop
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read_data(d);
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check_data(make_pattern(i));
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end loop;
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std.env.finish;
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end process;
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end architecture;
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@ -0,0 +1,80 @@
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[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Sun May 31 12:53:52 2020
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[*]
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[dumpfile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/foo.ghw"
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[dumpfile_mtime] "Sun May 31 12:50:15 2020"
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[dumpfile_size] 1134118
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[savefile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/litedram/extras/wave_tb.gtkw"
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[timestart] 1312950000
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[size] 2509 1371
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[pos] -1 -1
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*-24.248457 1386890000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] top.
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[treeopen] top.dram_tb.
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[sst_width] 301
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[signals_width] 433
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[sst_expanded] 1
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[sst_vpaned_height] 410
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@28
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top.dram_tb.reset_acks
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@420
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top.dram_tb.acks
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@28
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top.dram_tb.rst
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top.dram_tb.clk
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@22
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#{top.dram_tb.wb_in.dat[63:0]} top.dram_tb.wb_in.dat[63] top.dram_tb.wb_in.dat[62] top.dram_tb.wb_in.dat[61] top.dram_tb.wb_in.dat[60] top.dram_tb.wb_in.dat[59] top.dram_tb.wb_in.dat[58] top.dram_tb.wb_in.dat[57] top.dram_tb.wb_in.dat[56] top.dram_tb.wb_in.dat[55] top.dram_tb.wb_in.dat[54] top.dram_tb.wb_in.dat[53] top.dram_tb.wb_in.dat[52] top.dram_tb.wb_in.dat[51] top.dram_tb.wb_in.dat[50] top.dram_tb.wb_in.dat[49] top.dram_tb.wb_in.dat[48] top.dram_tb.wb_in.dat[47] top.dram_tb.wb_in.dat[46] top.dram_tb.wb_in.dat[45] top.dram_tb.wb_in.dat[44] top.dram_tb.wb_in.dat[43] top.dram_tb.wb_in.dat[42] top.dram_tb.wb_in.dat[41] top.dram_tb.wb_in.dat[40] top.dram_tb.wb_in.dat[39] top.dram_tb.wb_in.dat[38] top.dram_tb.wb_in.dat[37] top.dram_tb.wb_in.dat[36] top.dram_tb.wb_in.dat[35] top.dram_tb.wb_in.dat[34] top.dram_tb.wb_in.dat[33] top.dram_tb.wb_in.dat[32] top.dram_tb.wb_in.dat[31] top.dram_tb.wb_in.dat[30] top.dram_tb.wb_in.dat[29] top.dram_tb.wb_in.dat[28] top.dram_tb.wb_in.dat[27] top.dram_tb.wb_in.dat[26] top.dram_tb.wb_in.dat[25] top.dram_tb.wb_in.dat[24] top.dram_tb.wb_in.dat[23] top.dram_tb.wb_in.dat[22] top.dram_tb.wb_in.dat[21] top.dram_tb.wb_in.dat[20] top.dram_tb.wb_in.dat[19] top.dram_tb.wb_in.dat[18] top.dram_tb.wb_in.dat[17] top.dram_tb.wb_in.dat[16] top.dram_tb.wb_in.dat[15] top.dram_tb.wb_in.dat[14] top.dram_tb.wb_in.dat[13] top.dram_tb.wb_in.dat[12] top.dram_tb.wb_in.dat[11] top.dram_tb.wb_in.dat[10] top.dram_tb.wb_in.dat[9] top.dram_tb.wb_in.dat[8] top.dram_tb.wb_in.dat[7] top.dram_tb.wb_in.dat[6] top.dram_tb.wb_in.dat[5] top.dram_tb.wb_in.dat[4] top.dram_tb.wb_in.dat[3] top.dram_tb.wb_in.dat[2] top.dram_tb.wb_in.dat[1] top.dram_tb.wb_in.dat[0]
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|
#{top.dram_tb.wb_in.adr[31:0]} top.dram_tb.wb_in.adr[31] top.dram_tb.wb_in.adr[30] top.dram_tb.wb_in.adr[29] top.dram_tb.wb_in.adr[28] top.dram_tb.wb_in.adr[27] top.dram_tb.wb_in.adr[26] top.dram_tb.wb_in.adr[25] top.dram_tb.wb_in.adr[24] top.dram_tb.wb_in.adr[23] top.dram_tb.wb_in.adr[22] top.dram_tb.wb_in.adr[21] top.dram_tb.wb_in.adr[20] top.dram_tb.wb_in.adr[19] top.dram_tb.wb_in.adr[18] top.dram_tb.wb_in.adr[17] top.dram_tb.wb_in.adr[16] top.dram_tb.wb_in.adr[15] top.dram_tb.wb_in.adr[14] top.dram_tb.wb_in.adr[13] top.dram_tb.wb_in.adr[12] top.dram_tb.wb_in.adr[11] top.dram_tb.wb_in.adr[10] top.dram_tb.wb_in.adr[9] top.dram_tb.wb_in.adr[8] top.dram_tb.wb_in.adr[7] top.dram_tb.wb_in.adr[6] top.dram_tb.wb_in.adr[5] top.dram_tb.wb_in.adr[4] top.dram_tb.wb_in.adr[3] top.dram_tb.wb_in.adr[2] top.dram_tb.wb_in.adr[1] top.dram_tb.wb_in.adr[0]
|
||||||
|
@23
|
||||||
|
#{top.dram_tb.wb_in.sel[7:0]} top.dram_tb.wb_in.sel[7] top.dram_tb.wb_in.sel[6] top.dram_tb.wb_in.sel[5] top.dram_tb.wb_in.sel[4] top.dram_tb.wb_in.sel[3] top.dram_tb.wb_in.sel[2] top.dram_tb.wb_in.sel[1] top.dram_tb.wb_in.sel[0]
|
||||||
|
@28
|
||||||
|
top.dram_tb.wb_in.cyc
|
||||||
|
top.dram_tb.wb_in.stb
|
||||||
|
top.dram_tb.wb_in.we
|
||||||
|
top.dram_tb.wb_out.ack
|
||||||
|
top.dram_tb.wb_out.stall
|
||||||
|
@22
|
||||||
|
#{top.dram_tb.wb_out.dat[63:0]} top.dram_tb.wb_out.dat[63] top.dram_tb.wb_out.dat[62] top.dram_tb.wb_out.dat[61] top.dram_tb.wb_out.dat[60] top.dram_tb.wb_out.dat[59] top.dram_tb.wb_out.dat[58] top.dram_tb.wb_out.dat[57] top.dram_tb.wb_out.dat[56] top.dram_tb.wb_out.dat[55] top.dram_tb.wb_out.dat[54] top.dram_tb.wb_out.dat[53] top.dram_tb.wb_out.dat[52] top.dram_tb.wb_out.dat[51] top.dram_tb.wb_out.dat[50] top.dram_tb.wb_out.dat[49] top.dram_tb.wb_out.dat[48] top.dram_tb.wb_out.dat[47] top.dram_tb.wb_out.dat[46] top.dram_tb.wb_out.dat[45] top.dram_tb.wb_out.dat[44] top.dram_tb.wb_out.dat[43] top.dram_tb.wb_out.dat[42] top.dram_tb.wb_out.dat[41] top.dram_tb.wb_out.dat[40] top.dram_tb.wb_out.dat[39] top.dram_tb.wb_out.dat[38] top.dram_tb.wb_out.dat[37] top.dram_tb.wb_out.dat[36] top.dram_tb.wb_out.dat[35] top.dram_tb.wb_out.dat[34] top.dram_tb.wb_out.dat[33] top.dram_tb.wb_out.dat[32] top.dram_tb.wb_out.dat[31] top.dram_tb.wb_out.dat[30] top.dram_tb.wb_out.dat[29] top.dram_tb.wb_out.dat[28] top.dram_tb.wb_out.dat[27] top.dram_tb.wb_out.dat[26] top.dram_tb.wb_out.dat[25] top.dram_tb.wb_out.dat[24] top.dram_tb.wb_out.dat[23] top.dram_tb.wb_out.dat[22] top.dram_tb.wb_out.dat[21] top.dram_tb.wb_out.dat[20] top.dram_tb.wb_out.dat[19] top.dram_tb.wb_out.dat[18] top.dram_tb.wb_out.dat[17] top.dram_tb.wb_out.dat[16] top.dram_tb.wb_out.dat[15] top.dram_tb.wb_out.dat[14] top.dram_tb.wb_out.dat[13] top.dram_tb.wb_out.dat[12] top.dram_tb.wb_out.dat[11] top.dram_tb.wb_out.dat[10] top.dram_tb.wb_out.dat[9] top.dram_tb.wb_out.dat[8] top.dram_tb.wb_out.dat[7] top.dram_tb.wb_out.dat[6] top.dram_tb.wb_out.dat[5] top.dram_tb.wb_out.dat[4] top.dram_tb.wb_out.dat[3] top.dram_tb.wb_out.dat[2] top.dram_tb.wb_out.dat[1] top.dram_tb.wb_out.dat[0]
|
||||||
|
@28
|
||||||
|
top.dram_tb.rd_valid
|
||||||
|
top.dram_tb.rd_ready
|
||||||
|
@22
|
||||||
|
#{top.dram_tb.rd_data[63:0]} top.dram_tb.rd_data[63] top.dram_tb.rd_data[62] top.dram_tb.rd_data[61] top.dram_tb.rd_data[60] top.dram_tb.rd_data[59] top.dram_tb.rd_data[58] top.dram_tb.rd_data[57] top.dram_tb.rd_data[56] top.dram_tb.rd_data[55] top.dram_tb.rd_data[54] top.dram_tb.rd_data[53] top.dram_tb.rd_data[52] top.dram_tb.rd_data[51] top.dram_tb.rd_data[50] top.dram_tb.rd_data[49] top.dram_tb.rd_data[48] top.dram_tb.rd_data[47] top.dram_tb.rd_data[46] top.dram_tb.rd_data[45] top.dram_tb.rd_data[44] top.dram_tb.rd_data[43] top.dram_tb.rd_data[42] top.dram_tb.rd_data[41] top.dram_tb.rd_data[40] top.dram_tb.rd_data[39] top.dram_tb.rd_data[38] top.dram_tb.rd_data[37] top.dram_tb.rd_data[36] top.dram_tb.rd_data[35] top.dram_tb.rd_data[34] top.dram_tb.rd_data[33] top.dram_tb.rd_data[32] top.dram_tb.rd_data[31] top.dram_tb.rd_data[30] top.dram_tb.rd_data[29] top.dram_tb.rd_data[28] top.dram_tb.rd_data[27] top.dram_tb.rd_data[26] top.dram_tb.rd_data[25] top.dram_tb.rd_data[24] top.dram_tb.rd_data[23] top.dram_tb.rd_data[22] top.dram_tb.rd_data[21] top.dram_tb.rd_data[20] top.dram_tb.rd_data[19] top.dram_tb.rd_data[18] top.dram_tb.rd_data[17] top.dram_tb.rd_data[16] top.dram_tb.rd_data[15] top.dram_tb.rd_data[14] top.dram_tb.rd_data[13] top.dram_tb.rd_data[12] top.dram_tb.rd_data[11] top.dram_tb.rd_data[10] top.dram_tb.rd_data[9] top.dram_tb.rd_data[8] top.dram_tb.rd_data[7] top.dram_tb.rd_data[6] top.dram_tb.rd_data[5] top.dram_tb.rd_data[4] top.dram_tb.rd_data[3] top.dram_tb.rd_data[2] top.dram_tb.rd_data[1] top.dram_tb.rd_data[0]
|
||||||
|
@200
|
||||||
|
-
|
||||||
|
-
|
||||||
|
-wrapper
|
||||||
|
@28
|
||||||
|
top.dram_tb.dram.accept_store
|
||||||
|
@420
|
||||||
|
top.dram_tb.dram.req_op
|
||||||
|
top.dram_tb.dram.state
|
||||||
|
@28
|
||||||
|
top.dram_tb.dram.read_ack_1
|
||||||
|
top.dram_tb.dram.read_ack_0
|
||||||
|
top.dram_tb.dram.storeq_wr_valid
|
||||||
|
top.dram_tb.dram.storeq_wr_ready
|
||||||
|
top.dram_tb.dram.storeq_rd_valid
|
||||||
|
top.dram_tb.dram.storeq_rd_ready
|
||||||
|
top.dram_tb.dram.user_port0_rdata_ready
|
||||||
|
top.dram_tb.dram.user_port0_rdata_valid
|
||||||
|
top.dram_tb.dram.user_port0_wdata_ready
|
||||||
|
top.dram_tb.dram.user_port0_wdata_valid
|
||||||
|
top.dram_tb.dram.user_port0_cmd_we
|
||||||
|
top.dram_tb.dram.user_port0_cmd_ready
|
||||||
|
top.dram_tb.dram.user_port0_cmd_valid
|
||||||
|
top.dram_tb.dram.refill_cmd_valid
|
||||||
|
@420
|
||||||
|
top.dram_tb.dram.req_index
|
||||||
|
top.dram_tb.dram.req_hit_way
|
||||||
|
@28
|
||||||
|
top.dram_tb.dram.req_ad3
|
||||||
|
@420
|
||||||
|
top.dram_tb.dram.refill_row
|
||||||
|
top.dram_tb.dram.refill_index
|
||||||
|
top.dram_tb.dram.refill_way
|
||||||
|
@28
|
||||||
|
top.dram_tb.dram.system_clk
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
||||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue