Reformat loadstore1

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/65/head
Anton Blanchard 5 years ago committed by Anton Blanchard
parent 6e442e07a5
commit 687051ecbb

@ -10,55 +10,55 @@ use work.helpers.all;
-- We calculate the address in the first cycle -- We calculate the address in the first cycle


entity loadstore1 is entity loadstore1 is
port ( port (
clk : in std_ulogic; clk : in std_ulogic;


l_in : in Decode2ToLoadstore1Type; l_in : in Decode2ToLoadstore1Type;


l_out : out Loadstore1ToLoadstore2Type l_out : out Loadstore1ToLoadstore2Type
); );
end loadstore1; end loadstore1;


architecture behave of loadstore1 is architecture behave of loadstore1 is
signal r, rin : Loadstore1ToLoadstore2Type; signal r, rin : Loadstore1ToLoadstore2Type;
signal lsu_sum : std_ulogic_vector(63 downto 0); signal lsu_sum : std_ulogic_vector(63 downto 0);
begin begin
-- Calculate the address in the first cycle -- Calculate the address in the first cycle
lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0'); lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0');


loadstore1_0: process(clk) loadstore1_0: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
r <= rin; r <= rin;
end if; end if;
end process; end process;


loadstore1_1: process(all) loadstore1_1: process(all)
variable v : Loadstore1ToLoadstore2Type; variable v : Loadstore1ToLoadstore2Type;
begin begin
v := r; v := r;


v.valid := l_in.valid; v.valid := l_in.valid;
v.load := l_in.load; v.load := l_in.load;
v.data := l_in.data; v.data := l_in.data;
v.write_reg := l_in.write_reg; v.write_reg := l_in.write_reg;
v.length := l_in.length; v.length := l_in.length;
v.byte_reverse := l_in.byte_reverse; v.byte_reverse := l_in.byte_reverse;
v.sign_extend := l_in.sign_extend; v.sign_extend := l_in.sign_extend;
v.update := l_in.update; v.update := l_in.update;
v.update_reg := l_in.update_reg; v.update_reg := l_in.update_reg;


-- byte reverse stores in the first cycle -- byte reverse stores in the first cycle
if v.load = '0' and l_in.byte_reverse = '1' then if v.load = '0' and l_in.byte_reverse = '1' then
v.data := byte_reverse(l_in.data, to_integer(unsigned(l_in.length))); v.data := byte_reverse(l_in.data, to_integer(unsigned(l_in.length)));
end if; end if;


v.addr := lsu_sum; v.addr := lsu_sum;


-- Update registers -- Update registers
rin <= v; rin <= v;


-- Update outputs -- Update outputs
l_out <= r; l_out <= r;
end process; end process;
end; end;

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