antmicro-artix-dc-scm: Formatting to match top-arty

Make it easier to follow what needs to be updated.

Signed-off-by: Joel Stanley <joel@jms.id.au>

fpga/top-antmicro-artix-dc-scm.vhdl

@@ -34,29 +34,30 @@ entity toplevel is
     port(
         ext_clk   : in  std_ulogic;
 
-        d11_led : out std_ulogic;
-        d12_led : out std_ulogic;
-        d13_led : out std_ulogic;
-
         -- UART0 signals:
         uart_main_tx : out std_ulogic;
         uart_main_rx : in  std_ulogic;
 
+        -- LEDs
+        d11_led : out std_ulogic;
+        d12_led : out std_ulogic;
+        d13_led : out std_ulogic;
+
         -- DRAM wires
-	ddram_a       : out std_logic_vector(14 downto 0);
-	ddram_ba      : out std_logic_vector(2 downto 0);
-	ddram_ras_n   : out std_logic;
-	ddram_cas_n   : out std_logic;
-	ddram_we_n    : out std_logic;
-	ddram_dm      : out std_logic_vector(1 downto 0);
-	ddram_dq      : inout std_logic_vector(15 downto 0);
-	ddram_dqs_p   : inout std_logic_vector(1 downto 0);
-	ddram_dqs_n   : inout std_logic_vector(1 downto 0);
-	ddram_clk_p   : out std_logic;
-	ddram_clk_n   : out std_logic;
-	ddram_cke     : out std_logic;
-	ddram_odt     : out std_logic;
-	ddram_reset_n : out std_logic
+        ddram_a       : out std_ulogic_vector(14 downto 0);
+        ddram_ba      : out std_ulogic_vector(2 downto 0);
+        ddram_ras_n   : out std_ulogic;
+        ddram_cas_n   : out std_ulogic;
+        ddram_we_n    : out std_ulogic;
+        ddram_dm      : out std_ulogic_vector(1 downto 0);
+        ddram_dq      : inout std_ulogic_vector(15 downto 0);
+        ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
+        ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
+        ddram_clk_p   : out std_ulogic;
+        ddram_clk_n   : out std_ulogic;
+        ddram_cke     : out std_ulogic;
+        ddram_odt     : out std_ulogic;
+        ddram_reset_n : out std_ulogic
         );
 end entity toplevel;
 
@@ -117,15 +118,15 @@ architecture behaviour of toplevel is
     signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
     signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
 
-    -- ddram clock signals as vectors
-    signal ddram_clk_p_vec : std_logic_vector(0 downto 0);
-    signal ddram_clk_n_vec : std_logic_vector(0 downto 0);
-
     -- GPIO
     signal gpio_in     : std_ulogic_vector(NGPIO - 1 downto 0);
     signal gpio_out    : std_ulogic_vector(NGPIO - 1 downto 0);
     signal gpio_dir    : std_ulogic_vector(NGPIO - 1 downto 0);
 
+    -- ddram clock signals as vectors
+    signal ddram_clk_p_vec : std_logic_vector(0 downto 0);
+    signal ddram_clk_n_vec : std_logic_vector(0 downto 0);
+
     -- Fixup various memory sizes based on generics
     function get_bram_size return natural is
     begin
@@ -148,6 +149,7 @@ architecture behaviour of toplevel is
     constant BRAM_SIZE    : natural := get_bram_size;
     constant PAYLOAD_SIZE : natural := get_payload_size;
 begin
+
     -- Main SoC
     soc0: entity work.soc
         generic map(
@@ -273,6 +275,7 @@ begin
         signal dram_init_done  : std_ulogic;
         signal dram_init_error : std_ulogic;
         signal dram_sys_rst    : std_ulogic;
+        signal rst_gen_rst     : std_ulogic;
     begin
 
         -- Eventually dig out the frequency from the generator