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@ -257,12 +257,16 @@ begin
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count_bit: process(clk)
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count_bit: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if start_cmd = '1' then
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if rst = '1' then
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bit_count <= cmd_clks_i;
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bit_count <= (others => '0');
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elsif state /= DATA then
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else
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bit_count <= (others => '1');
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if start_cmd = '1' then
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elsif sck_recv = '1' then
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bit_count <= cmd_clks_i;
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bit_count <= std_ulogic_vector(unsigned(bit_count) - 1);
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elsif state /= DATA then
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bit_count <= (others => '1');
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elsif sck_recv = '1' then
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bit_count <= std_ulogic_vector(unsigned(bit_count) - 1);
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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