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makefile: Simplify microwatt-verilator target, add Docker image

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Recent versions of verilator support the --build option, allowing
us to remove a step.

Also add a Docker image for verilator.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/319/head
Anton Blanchard 3 years ago committed by Anton Blanchard
parent 8cdb00652b
commit 7e2de602ee
1 changed files with 5 additions and 4 deletions
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9
Makefile
Unescape Escape View File

@ -1,7 +1,8 @@
GHDL ?= ghdl GHDL ?= ghdl
GHDLFLAGS=--std=08 GHDLFLAGS=--std=08
CFLAGS=-O3 -Wall CFLAGS=-O3 -Wall
VERILATOR_FLAGS=-O3 #--trace # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
VERILATOR_FLAGS=-O3 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
# It takes forever to build with optimisation, so disable by default # It takes forever to build with optimisation, so disable by default
#VERILATOR_CFLAGS=-O3 #VERILATOR_CFLAGS=-O3


@ -11,6 +12,7 @@ NEXTPNR ?= nextpnr-ecp5
ECPPACK ?= ecppack ECPPACK ?= ecppack
OPENOCD ?= openocd OPENOCD ?= openocd
VUNITRUN ?= python3 ./run.py VUNITRUN ?= python3 ./run.py
VERILATOR ?= verilator


# We need a version of GHDL built with either the LLVM or gcc backend. # We need a version of GHDL built with either the LLVM or gcc backend.
# Fedora provides this, but other distros may not. Another option is to use # Fedora provides this, but other distros may not. Another option is to use
@ -39,6 +41,7 @@ NEXTPNR = $(DOCKERBIN) $(DOCKERARGS) hdlc/nextpnr:ecp5 nextpnr-ecp5
ECPPACK = $(DOCKERBIN) $(DOCKERARGS) hdlc/prjtrellis ecppack ECPPACK = $(DOCKERBIN) $(DOCKERARGS) hdlc/prjtrellis ecppack
OPENOCD = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb hdlc/prog openocd OPENOCD = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb hdlc/prog openocd
VUNITRUN = $(DOCKERBIN) $(DOCKERARGS) ghdl/vunit:llvm python3 ./run.py VUNITRUN = $(DOCKERBIN) $(DOCKERARGS) ghdl/vunit:llvm python3 ./run.py
VERILATOR = $(DOCKERBIN) $(DOCKERARGS) verilator/verilator:latest
endif endif


VUNITARGS += -p10 VUNITARGS += -p10
@ -201,10 +204,8 @@ microwatt.json: $(synth_files) $(RAM_INIT_FILE)
microwatt.v: $(synth_files) $(RAM_INIT_FILE) microwatt.v: $(synth_files) $(RAM_INIT_FILE)
$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@" $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"


# Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
verilator $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc $< --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT $(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@
make -C obj_dir -f Vmicrowatt.mk
@cp -f obj_dir/microwatt-verilator microwatt-verilator @cp -f obj_dir/microwatt-verilator microwatt-verilator


microwatt_out.config: microwatt.json $(LPF) microwatt_out.config: microwatt.json $(LPF)

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