Merge pull request #459 from paulusmack/fixes

Bug fixes for the FPU and dcache

dcache.vhdl

@@ -1704,7 +1704,7 @@ begin
 		    end if;
 
                     -- If this is a touch, complete the instruction
-                    if r1.full = '1' and r1.req.touch = '1' then
+                    if r1.full = '1' and r1.req.touch = '1' and r1.req.hit_reload = '1' then
                         r1.full <= '0';
                         r1.slow_valid <= '1';
                         r1.ls_valid <= '1';
@@ -1730,7 +1730,7 @@ begin
                             get_row_of_line(r1.store_row) = get_row_of_line(get_row(req.real_addr)) then
                             r1.full <= '0';
                             r1.slow_valid <= '1';
-                            if r1.mmu_req = '0' then
+                            if req.mmu_req = '0' then
                                 r1.ls_valid <= '1';
                             else
                                 r1.mmu_done <= '1';
@@ -1891,7 +1891,7 @@ begin
                             r1.wb.stb & r1.wb.cyc &
                             d_out.error &
                             d_out.valid &
-                            req_op_load_miss & req_op_store & req_op_bad &
+                            req_op_load_miss & req_op_store & req_hit_reload &
                             stall_out &
                             std_ulogic_vector(resize(tlb_hit_way, 3)) &
                             valid_ra &

fpu.vhdl

@@ -2015,7 +2015,7 @@ begin
                 set_r := '0';
                 opsel_r <= RES_SHIFT;
                 re_sel2 <= REXP2_NE;
-                if (r.r(UNIT_BIT + 2) or r_hi_nz or r_lo_nz or (or (r.r(DP_LSB - 1 downto 0)))) = '0' then
+                if (or (r.r(UNIT_BIT + 3 downto 0))) = '0' then
                     -- R is all zeroes but there may be non-zero bits in S
                     -- so shift them into R and set S to 0
                     set_r := '1';

tests/fpu/fpu.c

@@ -1629,6 +1629,8 @@ struct fmavals {
 	  0x41fffffffff00000, 0xc3ffffffffe00000, 0xc1fffffffff00000, 0x43ffffffffe00000 },
 	{ 0x3ff0000000000000, 0x000060fbffffefc1, 0x000060fbffffefc1, FPS_RN_NEAR,
 	  0x0000c1f7ffffdf82, 0x0000000000000000, 0x8000c1f7ffffdf82, 0x8000000000000000 },
+	{ 0x80000000fffffffd, 0x3ff0000000000000, 0x8000000300000003, FPS_UE | FPS_RN_NEAR,
+	  0xdef0000000000000, 0x5ee0000000300000, 0x5ef0000000000000, 0xdee0000000300000 },
 };
 
 int test23(long arg)