execute1: Fix bug causing SRR0 to be set to 4 more than the correct value

If an scv (or sc) instruction is executed and an asynchronous
interrupt occurs on the following instruction (e.g. the first
instruction of the scv handler), the address written to SRR0 will be
the address of that following instruction + 4.  The reason is that
ex1.advance_nia will still be set from the execution of the sc[v].
Fix this by clearing v.advance_nia in execute1_1.

(This only shows up for asynchronous interrupts with scv, not sc,
because sc clears MSR[EE].  It should show up for synchronous
interrupts with both sc and scv, but that has not been demonstrated.)

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

execute1.vhdl

@@ -1734,6 +1734,7 @@ begin
             v.prefixed := e_in.prefixed;
             v.insn := e_in.insn;
             v.prefix := e_in.prefix;
+            v.advance_nia := '0';
         end if;
 
         lv := Execute1ToLoadstore1Init;