core: Add framework for an FPU
This adds the skeleton of a floating-point unit and implements the mffs and mtfsf instructions. Execute1 sends FP instructions to the FPU and receives busy, exception, FP interrupt and illegal interrupt signals from it. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>pull/245/head
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-- Floating-point unit for Microwatt
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.insn_helpers.all;
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use work.decode_types.all;
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use work.crhelpers.all;
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use work.helpers.all;
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use work.common.all;
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entity fpu is
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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e_in : in Execute1toFPUType;
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e_out : out FPUToExecute1Type;
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w_out : out FPUToWritebackType
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);
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end entity fpu;
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architecture behaviour of fpu is
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type state_t is (IDLE,
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DO_MFFS, DO_MTFSF);
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type reg_type is record
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state : state_t;
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busy : std_ulogic;
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instr_done : std_ulogic;
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do_intr : std_ulogic;
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op : insn_type_t;
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insn : std_ulogic_vector(31 downto 0);
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dest_fpr : gspr_index_t;
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fe_mode : std_ulogic;
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rc : std_ulogic;
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is_cmp : std_ulogic;
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single_prec : std_ulogic;
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fpscr : std_ulogic_vector(31 downto 0);
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b : std_ulogic_vector(63 downto 0);
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writing_back : std_ulogic;
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cr_result : std_ulogic_vector(3 downto 0);
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cr_mask : std_ulogic_vector(7 downto 0);
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end record;
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signal r, rin : reg_type;
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signal fp_result : std_ulogic_vector(63 downto 0);
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begin
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fpu_0: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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r.state <= IDLE;
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r.busy <= '0';
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r.instr_done <= '0';
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r.do_intr <= '0';
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r.fpscr <= (others => '0');
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r.writing_back <= '0';
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else
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assert not (r.state /= IDLE and e_in.valid = '1') severity failure;
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r <= rin;
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end if;
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end if;
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end process;
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e_out.busy <= r.busy;
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e_out.exception <= r.fpscr(FPSCR_FEX);
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e_out.interrupt <= r.do_intr;
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w_out.valid <= r.instr_done and not r.do_intr;
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w_out.write_enable <= r.writing_back;
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w_out.write_reg <= r.dest_fpr;
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w_out.write_data <= fp_result;
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w_out.write_cr_enable <= r.instr_done and r.rc;
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w_out.write_cr_mask <= r.cr_mask;
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w_out.write_cr_data <= r.cr_result & r.cr_result & r.cr_result & r.cr_result &
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r.cr_result & r.cr_result & r.cr_result & r.cr_result;
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fpu_1: process(all)
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variable v : reg_type;
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variable illegal : std_ulogic;
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variable j, k : integer;
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variable flm : std_ulogic_vector(7 downto 0);
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begin
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v := r;
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illegal := '0';
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v.busy := '0';
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-- capture incoming instruction
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if e_in.valid = '1' then
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v.insn := e_in.insn;
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v.op := e_in.op;
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v.fe_mode := or (e_in.fe_mode);
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v.dest_fpr := e_in.frt;
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v.single_prec := e_in.single;
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v.rc := e_in.rc;
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v.is_cmp := e_in.out_cr;
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v.cr_mask := num_to_fxm(1);
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v.b := e_in.frb;
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end if;
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v.writing_back := '0';
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v.instr_done := '0';
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case r.state is
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when IDLE =>
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if e_in.valid = '1' then
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case e_in.insn(5 downto 1) is
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when "00111" =>
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if e_in.insn(8) = '0' then
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v.state := DO_MFFS;
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else
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v.state := DO_MTFSF;
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end if;
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when others =>
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illegal := '1';
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end case;
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end if;
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when DO_MFFS =>
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v.writing_back := '1';
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case r.insn(20 downto 16) is
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when "00000" =>
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-- mffs
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when others =>
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illegal := '1';
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end case;
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v.instr_done := '1';
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v.state := IDLE;
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when DO_MTFSF =>
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if r.insn(25) = '1' then
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flm := x"FF";
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elsif r.insn(16) = '1' then
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flm := x"00";
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else
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flm := r.insn(24 downto 17);
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end if;
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for i in 0 to 7 loop
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k := i * 4;
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if flm(i) = '1' then
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v.fpscr(k + 3 downto k) := r.b(k + 3 downto k);
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end if;
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end loop;
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v.instr_done := '1';
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v.state := IDLE;
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end case;
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-- Data path.
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-- Just enough to read FPSCR for now.
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fp_result <= x"00000000" & r.fpscr;
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v.fpscr(FPSCR_VX) := (or (v.fpscr(FPSCR_VXSNAN downto FPSCR_VXVC))) or
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(or (v.fpscr(FPSCR_VXSOFT downto FPSCR_VXCVI)));
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v.fpscr(FPSCR_FEX) := or (v.fpscr(FPSCR_VX downto FPSCR_XX) and
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v.fpscr(FPSCR_VE downto FPSCR_XE));
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if r.rc = '1' then
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v.cr_result := v.fpscr(FPSCR_FX downto FPSCR_OX);
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end if;
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if illegal = '1' then
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v.instr_done := '0';
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v.do_intr := '0';
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v.writing_back := '0';
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v.busy := '0';
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v.state := IDLE;
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else
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v.do_intr := v.instr_done and v.fpscr(FPSCR_FEX) and r.fe_mode;
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if v.state /= IDLE or v.do_intr = '1' then
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v.busy := '1';
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end if;
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end if;
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rin <= v;
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e_out.illegal <= illegal;
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end process;
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end architecture behaviour;
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