Register outputs on writeback

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/42/head
Anton Blanchard 5 years ago committed by Anton Blanchard
parent c7aa683ba8
commit 9fe8d211eb

@ -21,74 +21,91 @@ entity writeback is
end entity writeback; end entity writeback;


architecture behaviour of writeback is architecture behaviour of writeback is
signal e : Execute2ToWritebackType; type reg_internal_type is record
signal l : Loadstore2ToWritebackType; complete : std_ulogic;
signal m : MultiplyToWritebackType; end record;
signal w_tmp : WritebackToRegisterFileType; type reg_type is record
signal c_tmp : WritebackToCrFileType; w : WritebackToRegisterFileType;
c : WritebackToCrFileType;
end record;
signal r, rin : reg_type;
signal r_int, rin_int : reg_internal_type;
begin begin
writeback_0: process(clk) writeback_0: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
e <= e_in; r <= rin;
l <= l_in; r_int <= rin_int;
m <= m_in;
end if; end if;
end process; end process;


w_out <= w_tmp;
c_out <= c_tmp;

complete_out <= '1' when e.valid or l.valid or m.valid else '0';

writeback_1: process(all) writeback_1: process(all)
variable x: std_ulogic_vector(0 downto 0); variable x: std_ulogic_vector(0 downto 0);
variable y: std_ulogic_vector(0 downto 0); variable y: std_ulogic_vector(0 downto 0);
variable z: std_ulogic_vector(0 downto 0); variable z: std_ulogic_vector(0 downto 0);
variable v : reg_type;
variable v_int : reg_internal_type;
begin begin
x := "" & e.valid; v := r;
y := "" & l.valid; v_int := r_int;
z := "" & m.valid;
x := "" & e_in.valid;
y := "" & l_in.valid;
z := "" & m_in.valid;
assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1; assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1;


x := "" & e.write_enable; x := "" & e_in.write_enable;
y := "" & l.write_enable; y := "" & l_in.write_enable;
z := "" & m.write_reg_enable; z := "" & m_in.write_reg_enable;
assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1; assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1;


assert not(e.write_cr_enable = '1' and m.write_cr_enable = '1'); assert not(e_in.write_cr_enable = '1' and m_in.write_cr_enable = '1');


w_tmp <= WritebackToRegisterFileInit; v.w := WritebackToRegisterFileInit;
c_tmp <= WritebackToCrFileInit; v.c := WritebackToCrFileInit;


if e.write_enable = '1' then v_int.complete := '0';
w_tmp.write_reg <= e.write_reg; if e_in.valid = '1' or l_in.valid = '1' or m_in.valid = '1' then
w_tmp.write_data <= e.write_data; v_int.complete := '1';
w_tmp.write_enable <= '1';
end if; end if;


if e.write_cr_enable = '1' then if e_in.write_enable = '1' then
c_tmp.write_cr_enable <= '1'; v.w.write_reg := e_in.write_reg;
c_tmp.write_cr_mask <= e.write_cr_mask; v.w.write_data := e_in.write_data;
c_tmp.write_cr_data <= e.write_cr_data; v.w.write_enable := '1';
end if; end if;


if l.write_enable = '1' then if e_in.write_cr_enable = '1' then
w_tmp.write_reg <= l.write_reg; v.c.write_cr_enable := '1';
w_tmp.write_data <= l.write_data; v.c.write_cr_mask := e_in.write_cr_mask;
w_tmp.write_enable <= '1'; v.c.write_cr_data := e_in.write_cr_data;
end if; end if;


if m.write_reg_enable = '1' then if l_in.write_enable = '1' then
w_tmp.write_enable <= '1'; v.w.write_reg := l_in.write_reg;
w_tmp.write_reg <= m.write_reg_nr; v.w.write_data := l_in.write_data;
w_tmp.write_data <= m.write_reg_data; v.w.write_enable := '1';
end if; end if;


if m.write_cr_enable = '1' then if m_in.write_reg_enable = '1' then
c_tmp.write_cr_enable <= '1'; v.w.write_enable := '1';
c_tmp.write_cr_mask <= m.write_cr_mask; v.w.write_reg := m_in.write_reg_nr;
c_tmp.write_cr_data <= m.write_cr_data; v.w.write_data := m_in.write_reg_data;
end if; end if;

if m_in.write_cr_enable = '1' then
v.c.write_cr_enable := '1';
v.c.write_cr_mask := m_in.write_cr_mask;
v.c.write_cr_data := m_in.write_cr_data;
end if;

-- Update registers
rin <= v;
rin_int <= v_int;

-- Update outputs
complete_out <= r_int.complete;
w_out <= r.w;
c_out <= r.c;
end process; end process;
end; end;

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